PL4310706T3 - 64-bitowe adresy wirtualne mające bit(y) metadanych i kontrola kanoniczności, która nie zakończy się niepowodzeniem z powodu niekanonicznych wartości bitu(-ów) metadanych - Google Patents
64-bitowe adresy wirtualne mające bit(y) metadanych i kontrola kanoniczności, która nie zakończy się niepowodzeniem z powodu niekanonicznych wartości bitu(-ów) metadanychInfo
- Publication number
- PL4310706T3 PL4310706T3 PL23215435.1T PL23215435T PL4310706T3 PL 4310706 T3 PL4310706 T3 PL 4310706T3 PL 23215435 T PL23215435 T PL 23215435T PL 4310706 T3 PL4310706 T3 PL 4310706T3
- Authority
- PL
- Poland
- Prior art keywords
- bit
- metadata
- canonicality
- check
- values
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1408—Protection against unauthorised use of memory or access to memory by using cryptography
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
- G06F12/145—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights
- G06F12/1466—Key-lock mechanism
- G06F12/1475—Key-lock mechanism in a virtual system, e.g. with translation means
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/0644—Management of space entities, e.g. partitions, extents, pools
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0662—Virtualisation aspects
- G06F3/0665—Virtualisation aspects at area level, e.g. provisioning of virtual or logical volumes
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/52—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
- G06F21/53—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow by executing in a restricted environment, e.g. sandbox or secure virtual machine
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1052—Security improvement
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/65—Details of virtual memory and virtual address translation
- G06F2212/657—Virtual address space management
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/68—Details of translation look-aside buffer [TLB]
- G06F2212/683—Invalidation
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Security & Cryptography (AREA)
- Human Computer Interaction (AREA)
- Software Systems (AREA)
- Quality & Reliability (AREA)
- Executing Machine-Instructions (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Storage Device Security (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17/133,570 US12032485B2 (en) | 2020-12-23 | 2020-12-23 | 64-bit virtual addresses having metadata bit(s) and canonicality check that does not fail due to non-canonical values of metadata bit(s) |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| PL4310706T3 true PL4310706T3 (pl) | 2025-09-22 |
Family
ID=77821591
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PL23215435.1T PL4310706T3 (pl) | 2020-12-23 | 2021-09-17 | 64-bitowe adresy wirtualne mające bit(y) metadanych i kontrola kanoniczności, która nie zakończy się niepowodzeniem z powodu niekanonicznych wartości bitu(-ów) metadanych |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US12032485B2 (pl) |
| EP (2) | EP4020237B1 (pl) |
| CN (2) | CN117908795A (pl) |
| PL (1) | PL4310706T3 (pl) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12450173B2 (en) * | 2021-12-17 | 2025-10-21 | Intel Corporation | Method and apparatus to set guest physical address mapping attributes for trusted domain |
| US12455757B2 (en) * | 2022-03-24 | 2025-10-28 | Intel Corporation | Hypervisor-managed linear address translation and memory integrity |
| CN118069224B (zh) * | 2024-04-19 | 2024-08-16 | 芯来智融半导体科技(上海)有限公司 | 地址生成方法、装置、计算机设备和存储介质 |
Family Cites Families (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6807616B1 (en) | 2001-08-09 | 2004-10-19 | Advanced Micro Devices, Inc. | Memory address checking in a proccesor that support both a segmented and a unsegmented address space |
| US6901505B2 (en) | 2001-08-09 | 2005-05-31 | Advanced Micro Devices, Inc. | Instruction causing swap of base address from segment register with address from another register |
| US6898697B1 (en) | 2002-03-29 | 2005-05-24 | Advanced Micro Devices, Inc. | Efficient method for mode change detection and synchronization |
| US7761674B2 (en) | 2005-12-30 | 2010-07-20 | Intel Corporation | Identifier associated with memory locations for managing memory accesses |
| US8732430B2 (en) | 2011-03-22 | 2014-05-20 | Oracle International Corporation | Method and apparatus for using unused bits in a memory pointer |
| US8572441B2 (en) | 2011-08-05 | 2013-10-29 | Oracle International Corporation | Maximizing encodings of version control bits for memory corruption detection |
| US9286245B2 (en) | 2011-12-30 | 2016-03-15 | Intel Corporation | Hardware enforced memory access permissions |
| US9043559B2 (en) | 2012-10-23 | 2015-05-26 | Oracle International Corporation | Block memory engine with memory corruption detection |
| US9858140B2 (en) | 2014-11-03 | 2018-01-02 | Intel Corporation | Memory corruption detection |
| US10073727B2 (en) | 2015-03-02 | 2018-09-11 | Intel Corporation | Heap management for memory corruption detection |
| US9619313B2 (en) | 2015-06-19 | 2017-04-11 | Intel Corporation | Memory write protection for memory corruption detection architectures |
| US9652375B2 (en) | 2015-06-22 | 2017-05-16 | Intel Corporation | Multiple chunk support for memory corruption detection architectures |
| US10162694B2 (en) | 2015-12-21 | 2018-12-25 | Intel Corporation | Hardware apparatuses and methods for memory corruption detection |
| US10515023B2 (en) * | 2016-02-29 | 2019-12-24 | Intel Corporation | System for address mapping and translation protection |
| US10761979B2 (en) | 2016-07-01 | 2020-09-01 | Intel Corporation | Bit check processors, methods, systems, and instructions to check a bit with an indicated check bit value |
| US10296416B2 (en) | 2016-07-02 | 2019-05-21 | Intel Corporation | Read from memory instructions, processors, methods, and systems, that do not take exception on defective data |
| US11630920B2 (en) | 2018-06-29 | 2023-04-18 | Intel Corporation | Memory tagging for side-channel defense, memory safety, and sandboxing |
| US10860709B2 (en) | 2018-06-29 | 2020-12-08 | Intel Corporation | Encoded inline capabilities |
| US10877897B2 (en) | 2018-11-02 | 2020-12-29 | Intel Corporation | System, apparatus and method for multi-cacheline small object memory tagging |
| US11288213B2 (en) | 2019-03-29 | 2022-03-29 | Intel Corporation | Memory protection with hidden inline metadata |
| US11868273B2 (en) | 2019-06-29 | 2024-01-09 | Intel Corporation | Memory protection with hidden inline metadata to indicate data type |
| US10891230B1 (en) | 2019-06-29 | 2021-01-12 | Intel Corporation | Apparatuses, methods, and systems for selective linear address masking based on processor privilege level and control register bits |
| US11580234B2 (en) | 2019-06-29 | 2023-02-14 | Intel Corporation | Implicit integrity for cryptographic computing |
| US11392503B2 (en) | 2019-12-27 | 2022-07-19 | Intel Corporation | Memory tagging apparatus and method |
| US11030113B1 (en) | 2019-12-27 | 2021-06-08 | Intel Corporation | Apparatus and method for efficient process-based compartmentalization |
| US11029957B1 (en) | 2020-03-27 | 2021-06-08 | Intel Corporation | Apparatuses, methods, and systems for instructions to compartmentalize code |
-
2020
- 2020-12-23 US US17/133,570 patent/US12032485B2/en active Active
-
2021
- 2021-09-17 PL PL23215435.1T patent/PL4310706T3/pl unknown
- 2021-09-17 EP EP21197309.4A patent/EP4020237B1/en active Active
- 2021-09-17 EP EP23215435.1A patent/EP4310706B1/en active Active
- 2021-12-17 CN CN202410091680.6A patent/CN117908795A/zh active Pending
- 2021-12-17 CN CN202111552213.1A patent/CN114661228A/zh active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| US12032485B2 (en) | 2024-07-09 |
| CN117908795A (zh) | 2024-04-19 |
| EP4310706B1 (en) | 2025-06-04 |
| EP4020237A1 (en) | 2022-06-29 |
| EP4310706A2 (en) | 2024-01-24 |
| EP4020237B1 (en) | 2024-01-17 |
| EP4310706A3 (en) | 2024-04-24 |
| US20220197822A1 (en) | 2022-06-23 |
| CN114661228A (zh) | 2022-06-24 |
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