PL428713A1 - Low-power voltage buffer - Google Patents

Low-power voltage buffer

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Publication number
PL428713A1
PL428713A1 PL428713A PL42871319A PL428713A1 PL 428713 A1 PL428713 A1 PL 428713A1 PL 428713 A PL428713 A PL 428713A PL 42871319 A PL42871319 A PL 42871319A PL 428713 A1 PL428713 A1 PL 428713A1
Authority
PL
Poland
Prior art keywords
transistor
low
power voltage
differential pair
voltage buffer
Prior art date
Application number
PL428713A
Other languages
Polish (pl)
Other versions
PL239981B1 (en
Inventor
Stanisław Szczepański
Jacek Jakusz
Robert Piotrowski
Original Assignee
Politechnika Gdańska
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Politechnika Gdańska filed Critical Politechnika Gdańska
Priority to PL428713A priority Critical patent/PL239981B1/en
Publication of PL428713A1 publication Critical patent/PL428713A1/en
Publication of PL239981B1 publication Critical patent/PL239981B1/en

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Abstract

Niskomocowy bufor napięciowy o zmniejszonym błędzie wzmocnienia jednostkowego wykorzystujący różnicowy wzmacniacz MOS sterowany z końcówek podłoża pierwszego tranzystora i drugiego tranzystora pary różnicowej, w którym do wspólnych końcówek źródeł pary różnicowej pierwszego tranzystora (sM1) drugiego tranzystora (sM2) podłączone są jedne z wrót aktywnego dwójnika (A) o jednostkowym wzmocnieniu napięciowym, zaś drugie wrota podłączone są do wyjścia bufora (WY), natomiast do wyjścia pierwszego tranzystora (dM1) pary różnicowej podłączony jest wzmacniacz (B) przenoszący sygnał do wyjścia bufora (WY).Low-power voltage buffer with reduced unit gain error using a differential MOS amplifier driven from the substrate terminals of the first transistor and the second differential pair transistor, in which to the common terminals of the sources of the differential pair of the first transistor (sM1) of the second transistor (sM2) are connected one of the gates of the active two-pole ( A) with a unit voltage gain, and the second gate is connected to the buffer output (WY), while the amplifier (B) is connected to the output of the first transistor (dM1) of the differential pair, transmitting the signal to the buffer output (WY).

PL428713A 2019-01-29 2019-01-29 Low-power voltage buffer PL239981B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PL428713A PL239981B1 (en) 2019-01-29 2019-01-29 Low-power voltage buffer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PL428713A PL239981B1 (en) 2019-01-29 2019-01-29 Low-power voltage buffer

Publications (2)

Publication Number Publication Date
PL428713A1 true PL428713A1 (en) 2020-08-10
PL239981B1 PL239981B1 (en) 2022-02-07

Family

ID=71943640

Family Applications (1)

Application Number Title Priority Date Filing Date
PL428713A PL239981B1 (en) 2019-01-29 2019-01-29 Low-power voltage buffer

Country Status (1)

Country Link
PL (1) PL239981B1 (en)

Also Published As

Publication number Publication date
PL239981B1 (en) 2022-02-07

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