PL3552108T3 - Urządzenia i sposoby dla architektury procesora - Google Patents

Urządzenia i sposoby dla architektury procesora

Info

Publication number
PL3552108T3
PL3552108T3 PL16923787T PL16923787T PL3552108T3 PL 3552108 T3 PL3552108 T3 PL 3552108T3 PL 16923787 T PL16923787 T PL 16923787T PL 16923787 T PL16923787 T PL 16923787T PL 3552108 T3 PL3552108 T3 PL 3552108T3
Authority
PL
Poland
Prior art keywords
apparatuses
methods
processor architecture
architecture
processor
Prior art date
Application number
PL16923787T
Other languages
English (en)
Inventor
Jason W. Brandt
Robert S. Chappell
Jesus Corbal
Edward T. Grochowski
Stephen H. Gunther
Buford M. Guy
Thomas R. Huff
Christopher J. Hughes
Elmoustapha OULD-AHMED-VALL
Ronak Singhal
Seyed Yahya Sotoudeh
Bret L. Toll
Lihu Rappoport
David Papworth
James D. Allen
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Publication of PL3552108T3 publication Critical patent/PL3552108T3/pl

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0828—Cache consistency protocols using directory methods with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0808—Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Executing Machine-Instructions (AREA)
PL16923787T 2016-12-12 2016-12-12 Urządzenia i sposoby dla architektury procesora PL3552108T3 (pl)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
PCT/US2016/066242 WO2018111228A1 (en) 2016-12-12 2016-12-12 Apparatuses and methods for a processor architecture
EP16923787.2A EP3552108B1 (en) 2016-12-12 2016-12-12 Apparatuses and methods for a processor architecture

Publications (1)

Publication Number Publication Date
PL3552108T3 true PL3552108T3 (pl) 2022-01-03

Family

ID=62559007

Family Applications (1)

Application Number Title Priority Date Filing Date
PL16923787T PL3552108T3 (pl) 2016-12-12 2016-12-12 Urządzenia i sposoby dla architektury procesora

Country Status (10)

Country Link
EP (2) EP3889787B1 (pl)
JP (1) JP7095208B2 (pl)
KR (1) KR102809573B1 (pl)
CN (1) CN109952566B (pl)
BR (1) BR112019009566A2 (pl)
DE (1) DE112016007516T5 (pl)
ES (1) ES2895266T3 (pl)
PL (1) PL3552108T3 (pl)
TW (2) TWI853207B (pl)
WO (1) WO2018111228A1 (pl)

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TWI779923B (zh) * 2021-11-11 2022-10-01 南亞科技股份有限公司 圖案驗證系統及其操作方法
CN114217854A (zh) * 2021-12-17 2022-03-22 广东赛昉科技有限公司 一种L2中queue的管理方式的实现方法及系统
CN115269199B (zh) * 2022-08-11 2025-09-05 北京奕斯伟计算技术股份有限公司 数据处理方法、装置、电子设备及计算机可读存储介质
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CN115858420B (zh) * 2023-02-23 2023-05-12 芯砺智能科技(上海)有限公司 用于支持多处理器架构的系统缓存架构和芯片
TWI863323B (zh) * 2023-06-01 2024-11-21 慧榮科技股份有限公司 存取快閃記憶體模組的方法及相關的快閃記憶體控制器與電子裝置
TWI850095B (zh) * 2023-09-01 2024-07-21 日商鎧俠股份有限公司 固態儲存裝置及其指令擷取方法
TWI902003B (zh) * 2023-09-11 2025-10-21 大陸商北京集創北方科技股份有限公司 數據傳輸處理方法、顯示裝置及資訊處理裝置
WO2025100733A1 (ko) * 2023-11-06 2025-05-15 삼성전자 주식회사 메모리 리소스를 관리하기 위한 전자 장치, 그 동작 방법 및 저장 매체
TWI884842B (zh) * 2024-08-02 2025-05-21 技嘉科技股份有限公司 配置終端裝置的散熱的電子裝置和方法
CN121070625B (zh) * 2025-11-03 2026-02-13 上海壁仞科技股份有限公司 一种指令同步方法及人工智能芯片

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Also Published As

Publication number Publication date
CN109952566B (zh) 2024-08-23
JP2020513605A (ja) 2020-05-14
EP3552108A4 (en) 2020-07-15
JP7095208B2 (ja) 2022-07-05
DE112016007516T5 (de) 2019-10-02
TW201823971A (zh) 2018-07-01
ES2895266T3 (es) 2022-02-18
EP3889787B1 (en) 2023-11-01
CN109952566A (zh) 2019-06-28
TW202219748A (zh) 2022-05-16
KR20190086669A (ko) 2019-07-23
TWI751222B (zh) 2022-01-01
TWI853207B (zh) 2024-08-21
KR102809573B1 (ko) 2025-05-20
BR112019009566A2 (pt) 2019-08-06
EP3889787A1 (en) 2021-10-06
EP3552108A1 (en) 2019-10-16
WO2018111228A1 (en) 2018-06-21
EP3552108B1 (en) 2021-08-18

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