PH26752A - Digital display system - Google Patents

Description

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DESCRIPTION

1, Field of the Invention

This invention relates to digital display systems, and in particular to such display systems employing a rater scanned cathode ray tube. More particularly, the present invention raletes to such a display system which performs automatic mode switchinge 2, Description of the Prior Art

The primary use of raster scanned cathode ray tubes “ - 10 has been in the television field. However, over the last . decade, such raster scanning has found increasing uses in the computer display field. At the present time, an over- whelming majority of computer aystems use such displays for communicating instructions and results to the opera= tor.

In both television and computer display, many modes of operation name been used and proposed. In television, for example, modes of operation with raster line struc- tures of 405, 525, 625 and 805 lines have been usede In both Britain and Francs, different elevision transmitters still generate signals using different line structures, 405 and 625 in Britain, and 805 and 625 in Franoeo In both of these countries, at least up to a few years ago0e receivers were provided with manual switching arrange ments to alter the horizontal time base frequency when switching between high and low line definition channels.

Some attempts were made to provide automatic switching . of the time base frequency based on the incoming signals, p as is illustrated in British Patent Fo, 1,188,294, In that patent, the horisontal synchronizing signals are applied to a circuit which is tuned to the frequency of these signals for one line definition standard (eege 405 lines). The circuit, therefore, provides different outputs in accordance with the different line structures required by the input signals, and these outputs are used to drive relays to switch the horizontal time base to correspond ing frequencies, :

A similar, but more complex arrangement is employed in the computer video display device described in published

European patent application No, 4798, In that arrangement, the video display device is adapted to eperate on different line standards in accordance with received video data. A phase locked loop tone generator which receives the come posite video signal ies tuned to the line frequency of one of the line standards. Accordingly, it provides different outputs in accordance with the line standard indicated by the video signale These outputs ars used to switch the horizontal time base frequency, ~The present invention is based on the realisation a TT 26752 s that in a digital display system in which signals for the display are develcped in a computer system, the polarity of the synch signals can be melected at will.

Consequently, switching of the display monitor oan be achieved by reference to the polarity of at least one of the synch signals. Note that in embodiments of the invention described hereinafter, the synch signals are defined as being of one polarity whem each synch pulse comprises a rise from a given referance level to a higher lsvel, and of the opposite polarity when each synch pulse . comprises a drop frem maid higheat level to the reference level. Thus, if the digital signals gemerated by the oem puter are for a first data format, at least ome of the synch signal trains, fer example the vertical synch sige nals, is of one polarity, and if the computer signals are . for a different format these synch signals are of the opposite polaritye The circuits which detect the polarity to provide the switching functions in the monitor, as they do not use tuned circuits, are simpler and more reliable than those of the prior art arrangements. In addition, the formats to be switched may be either the scanning fre- . quencies and/or the video signal format,

DISCLOSURE OF THE INVENTION

The present invention relates to a digital display 5 system including digital data processing means operable to develop a data set for display, and a monitor device, including a raster scenned cathode ray tube and video drive means responsive to said data set to generate a dig- play on the cathode ray tube, in which the data process— ing means is further operable to generate a series of syn— chronizing signals of polarity related to the format of said data set and the monitor device includes circuit means responsive to the polarity of said synchronizing signals to switch the raster scanning means of the monitor to correctly display a received data set,

F_DESC TON OF N

FIC. 1 is a block diagram of a display system in- cluding a display adapter coupled to a computer and a dis- play monitor.

FIG. 2 is a diagram of the display monitor embody- ing the inventions

FIG. 3 is a waveform diagram showing synchronizing signals applied to the monitor of FIG. 2 from ths display adapter shown in FIG. le

FIG. 4 khows a modification of the ménitor control circuit in FiG. 2. 1LED I0N QF 1 ION

FIG. 1 is a block diagram of a known digital data / “5 o-

display arrangement comprising a microcomputer 101 coupled to a display monitor 102. The microcomputer is shown in highly simplified form and comprises a central processing unit 103 coupled to a display adapter which } 5 comprises the components to the right of broken line 104,

The display adapter comprises a programmable CRT controller 108, a graphics processor 109, a buffer store 110, and a video processor 112, The CRT controller 108 is responsive to tuning and control signals from CPU 103 on a bus 105 to generate synch signals on a bus 113, address signals for buffer 110 on a bus 111 and control signals for video pro- cessor 112 on a bus 115, CPU 103 also provides address oo signals for the buffer 110 over a bus 106. Output digital signals from video processor 112 are applied over a bus 114 to video circuits 116 in the display monitor which, in response to these signals, generate the color drive signals for a CRT 119, The synch signals from the CRT controller 108 on bus 113 are used to drive time base gene- rators 117 which provides signals for the deflection coils of CRT 119 in a known manner,

In operation, graphics processor 109 processes graphics data from CPU 103 and places the processed signals intc buffer store 110, These processed signals may be stored in buffer 110 in an all points addressable mode, in which each picture element to be displayed is represented, in the buffer, by digital data representing the color and intensity of that element. Alternatively, the buffer store may receive character data (sither alphanumeric or graphic) which is subsequently decoded to provide the pic- ture element data. Data is stored in the buffer at addresses defined by the CFU over bus 106s This data is subsequently read from the buffer by address signels from the CRT con troller, passed to the video processor for any required conversion, and then applied over bus 114 to the monitor 102, Thus the data in buffer 110 is updated under the control of the CFU and transmitted to the monitor under the control of the CRT controller 108, which also provides - the synch signals. CRT controller 108, as it is program- mable, can control the display adapter to operate in dif ferent modes, such as the above mentioned all points addressable and character generator modes. In addition, it is programmed to determine the format of the aynoh pulses applied to the monitor.

FIG. 2 shows, in simplified form, the major com- ponents of a digital video display monitor embodying the invention. The ménitor includes a buffer 1 coupled to receive digital color signals on lines 2 through 7, hori- zontal synchronizing signals on a line 8 and earth poten tial on a line 10 which is also coupled to screen the lines 2 through 9 in a coupling cable. Color signal outputs from -T =

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EL ; pu ii. wy buffer 1 are applied, over lines 11 through 16, to logic 3 qu

Bt : reans 19, Logic means 19 is shown as a read-only memory, y ge ' gi . lo goof Co but it may be any other type of logic device, for exam N i int co - ple a programmable logic array, which is adapted te per- ya: _ 1 ksi S08 ‘form the logic which will be described later, : 1 i ; hii Ga EER In response to the input color signals, which, as : 4 [1 AE Lo : VT | cde ; § gd © 0 :% :wAll be seen later, will either be on lines 1} through Et

Be Der | i by Shit 14 or en lies 11 through 16, logic means 19 generates :

WE : ; ig uhh Lt digital cooler drive signals on lines 20 through 25. These - TE 1 lh Th . CL Ee ’ i 3 Coy . bd

Bie ah Ly CATE - Cet So yo 2 Li p 30 i." | signals are applied as inputs to video drive asplitiere “ d hid ... 26 through 28 which respectively provide analog outputs 1 .. gH Rt a Sd AY Ps ST , ! } , Co } Sa : i

Ey ry © to drive the red, green and blue guna of a color cathode ’ petit fi oo ray tube (not shown) over lines 29, 30 and 31. Each of oo ! bei Ciel fil "these amplifiers has un intensified color inpit (R, G and vB

Ry iat : grr v8 B) and a non-intenaified color input (re go ») and oan, : (i polo Lo "y

Bs wi’. therefore, generate any of four intensities depsnding on : or : { a to : ‘the values of the pair of digital inpute. Thus, the amw-, ~~ _ +

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FE fib plifiers together are capable of selecting 64 different ! . pu | SE

Ads 0 00lexr drives. : bn aarde oo | et i fo bls 80, Referring back to register 1, putput line 17 oar ) homme, 0 - i §

Lo ©" ries the horizontal synch signals. These are coupled to ; 8 PARLE a horizontsl time base generator 32 which provides hori~ yY

It i WR . * ; : J } : in Lo 7 sontal deflection currents for the horisontal deflection

Ered FR i . " * ’ } pa of. 0. soils of the CKT ovex/ Lines 50 and 51. Vertical synch’ Cl a Lip aH . : ' ' " : ' N : b vi v8. signals from register 1 are applied over line 16, turough

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Bp } . . } . het oo 4p genio + bl 8 . . cp an exclusive NOR (XNOR) gate 41 and line 47, to a ver- tical time base generator 33 to drive the vertical de- flection coils of the CRT over lines 52 and 53. As will be seen later,the purpose of XNOR 41 is to ensure that the polarity of the synch signals applied to time base gene- rator 33 is constant irrespective of the polarity of these signals on line 18.

The vertical synch signals on line 18 are also applied to a control circuit which develops control signals for logic means 19, the time base generators 32 and 33, and XNOR 41 in accordance with the polarity of these synch sigoals. Line 18 is coupled, through an inverter 34 and integrator circuit comprising reaistor 35 and capacitor 36, to the negative input of a differential amplifier 39.

The positive input of differential emplifier receives the signals from line 18 uninverted but integrated by an in~ tegrator cowprising resistor 38 and capacitor 37. The output of amplifier 39 provides control signals to logic means 19 and XNOR 41 over a line 40. These signals on jine 40 are also applied, through a potentiometer network comprising resistor 42 and 43, to the base of NDN tran gistor 44. The collector of transistor 44 is coupled to a positive potential through resistor 45 amd directly over line 46, to a control input of the time base genera- tor 32.

One example of the operation of the FI1G, 2 system will now be detailed to agsist in the understand- ing of the invention, The monitor system shown in FIG. 2 is, of course, adapted to present displays on the CRT in response to the digital signals received over lines 3 through 9. These signals are generated by a display adapter within a computer system as shown in FIG. 1 which assembles the digital data and provides sequences of this data for display. The primary object of the invention is to effect automatic switching within the monitor for dif- ferent data formats. In the present example, two switched

Tome Lo ‘ modes corresponding to two specific data formats will be ’ described, though it will become clear later that switch- ing between up to four modes could be achieved by modi fication of the F1G. 2 system. In the present example, in the first of the switched modes, MODEl, the monitor is adapted to display 640 x 200 pels, each with any of 16 colors. In the second mode, MODE 2, the monitor is adapted to display 640 x 350 pels, each with any of 64 colors IN

MODE 1, the monitor responds to positive horizontal and vertical synch pulses and to color signals on only four of the input lines, for example lines 2 through 5, in FIG. 2.

In NCDE 2, the monitor responds to positive horizontal and negative vertical synch pulses from the adapter and 2% to color signals on all of the input lines 2 through 7 in

F1G. 2. Thus it should be noted that the polarity of the synch pulses, generated by the display adapter of the computer, must correspond to the data format, If the adapter can provide a signal format suitable for

MODE 1 only, then it is designed to provide positive synch pulses. If the adapter provides the MODE 2 signal format, then it generates positive horizontal and negative vertical synch pulses, With the automatic awitching between modes, the monitor system of Fig. 2 can, therefore be coupled to either of these adapter types and operate without manual adjustment, Alternatively an adapter card may be able to switch between the data formats. An example of such an adapter would be one which can be switched between a low definition character generator operation, corresponding to

MODE 1 in the monitor, and a high definition all points : addressable operation corresponding to KODE 2 in the moni- tors Alternatively, the adapter card could use character generation and all points addressable operations in both modes, with low definition in the first mode and high de- finition in the second mode, With such a switchable adapter, it is clear that reversal of the polarity of the vertical synch pulses can be easily achieved during switch- ings ln order to display the 640 x 200 pels in MODE 1, the vertical time base frequency is set to 60 Hz, the hori zontal to 15,7 kHz. In this node the horizontal time base “ll ~ width control is set to overscan the CRT and to adjust for the difference in the aspect ratio of the display data between the two modes. In MODE 2, the vertical time base frequency remains at 60 Hz, the horizontal time base frequency hs set to 22 kHg and the width is set for normal scan.

Referring back to F1G. 2, the input signals on lines 2 through 9 are passed through buffer 1 to the logic means 19, the horizontal time base 32, and, over line 18, the vertical synch signals are applied to XNOR gate 41 and to ) Co Wl inverter 34. In MODE 1, the synch signals are positive, as shown at waveform A of FIG. 3. Inverter 34 provides an output signal the inverse of waveform A, that is, a signal with a normally high level which drops during each synch pulses This output signal is applied to the integrator, comprising resistor 35 and capacitor 36, which has a time constant considerably longer than the period of each aynch pulse. Thus, 3 substantially constant high level signal is applied from the integrator to the negative input of differential amplifier 39. At the same time, the uni- verted signal of waveform A of FIG. 3 is applied to the integrator cowprising resistor 38 and capacitor 37, which is similar to integrator 35, 36. Thus, a substantially constant low level signal is applied from integrator 38, 37 to the positive input of differential amplifier 39. -12 - BAD ORIGINAL Pb)

In response to these inputs, differential amplifier 39 provides a substantially constant low level output. This low level output is applied over line 40 to XNOR gato 41 which, therefore inverts the positive synch pulses applied to its other input to provide negative synch pulses to ‘vertical time base generator 33. The low output on line 40 is coupled to logic means 19, for the purpose to be des-— cribed below, and, through network 42, 43, to transistor 44.

This pransistor ie therefore set to a low current level, so a positive potential through resistor 45 is applied to line 46. This line is coupled within time base generator 32 to electronic switches which are set by the positive potential "on the line. When set, these switches couple frequency determining and width determining components into the time base to set it to 15 kHz and overscan as required for MODE 1.

In MODE 2, the vertical synch pulses on line 18 are negative, as shown at waveform B of FIG. 3, Thus, in- verter 34 applies a normally lew level output, which rises for each synch pulse, to integrator 36, 36. This inte- ’ grator therefore delivers a substantially congtant low level signal to the negative input of integrator 39, The univerted waveform B is applied to integrator 38, 37 to provide a substantially constant high level signal to the positive input of differential amplifier 39. The output of this amplifier, in response to these input signal levels, is a substantially constant high level. This is applied, over line 40, to XNUR gate 41 so that the nega- tive going synch pulses applied to the other input of this gate pass through the gate univerted. The vertical time base generator, therefore, still receives negative going synch pulses over line 47. Now, however, the signal level on line 40 applied to logic means 19 is high, the effect of which will be described later. This high level is alao applied through ne work 42, 43 to cause transistor 44 to conduct heavily, bringing the potential on line 46 near to zero. This resets the electronic switches in the horizontal time base generator 32 to cut out the above men tioned frequency and width determining components for MODE 1 and bring in further such components to set this time base to 22 kHz and normal scan widths Thus, the system, a8 80 far deacribed, automatically switches the CRT dee flection system to allow for the different modes in accords ance with the polraity of the vertical synch signals while providing common polarity synch signals for the vertioal time base generator in both modes. .

As has been mentioned above, line 40 from dif- ferential amplifier 39 is also applied as an input to logic means 19, It will be recalled that this line is set to a low level in MODE 1 and a high level in MODE 2, In MODE 1 the color signals from the adapter arrive over line 2 through 5, These signals may represent intensity, red, green and blue (I.R.G.B.) digital signals on the rea~ pective lines to provide 16 colors on the C,R.T: In

MODE 2 six lines, 2 through 7 carry respectively high intensity red, red, high intensity green, green, high in- tensity blue, and blue (RrGgBb) digital signals to provide 64 colors, In MODE 1 the extraneous lines, that is lines 6 and 7 may either bes earthed at the adapter or provide don't care inputs to logic means 19,

In MODE 2, logic means 19 responds to the high level on line 40 by gating the signals from register 1 over lines 11 through 16 directly to the corresponding

RrGgBb inputs to amplifiers 26 through 28 over lines 20 through 25,

In MODE 1, the low level on line 40 is applied to logic means 19. This causes logic means 19 to decode the

IRGB signals on lines 11 through 14 from register 1 as fol- lowss .

ee —————————— 1 R G B Rrr Gge Bbb Color 0 0 0 0 00 00 00 Black 0 0 0 1 00 00 0 Blue 0 0 1 0 00 20 00 Green - 0 0 | 1 00 10 20 Cyan 0 1 0 0 10 00 00 Red 0 1 0 1 10 00 10 Magenta 0 1 1 0 10 01 00 Brown 0 l 1 l 10° 10 10 White 1 0 0 0 01 01 01 Gray 1 0 1 0 01 11 01 Light green to 1 0 1 1 01 11 11 Ligh oyan 1 1 0 0 11 01 01 Light red 1 1 0 1 11 01 11 Ligh magenta : 1 1 1 0 11 11 01 Light yellow } 1 1 1 1 l1 11 11 High Inten- sity & White ee

Thus, in NODE 1, logic means 19 decodes the four parallel input signals to apply a selection of 16 of the possible 64 drive combinations to amplifiers 26 through 28. In

ODE 2, logic weans effects a straight gating operation to pass the six parallel input signals directly to ampli- 5 fiers 26 through 28. As in the case of the time base control the chosen operation is selected in accordance with the polarity of the vertical synch signals received from the adapter. As indicated in FIG. 2, logic means 19 comprises a read-only memory, but it may be in the form of a prgrammable logic array device, Suitably pro- gramming either of these devices to perform the logical operations defined above would present no difficulty to one skilled in the art. Alternatively, logic means 19 could be implemented by tristate gates or multiplexers and simple switching logics

The components 34 through 47 in the control circuit of FIG. 2, may be replaced by other circuitry performing the same functions One other form of this control circuit is shown in FlG. 40 There, the vertical synch pulses are applied to a single integrator comprising resistor 60 and capacitor 61s This integrator is similar to those in FIG. ) 2, and has a long time constant compared with the period of the synch pulses, The integrator output is applied to one input of an AND gate 62; the other input of which is coupled to a constant positive level. Thus, when the ver : tical synch pulses are high, as shown at A in FlG. 3, the integrator output is low, so the output of AND gate 62 is

Jowe With the low synch pulses shown at B in FIG. 2, the output of the infgegrator is high, so the output of AND 5 gate 62 is highs Accordingly, ss with the FIG. 2 system,

the F1G. 4 system provides a substantially donstant low output on control line 40, a high output on line 46 and negative vertical synch pulses on line 47 in response te the positive synch pulses of waveffrm A of FIG, 3. appear- ing on line 18, In response to the negative vertical synch pulses, line 40 goes high, line 46 goes low, and the synch pulses on line 47 still remain negative. Alternatively,

AND gate 62 could be replaced by a single input threshold switching buffer device to provide the same outputs on line 40,

It is clear that, with the systems shown in FIGS. 2 oo © % 7 and 4, if the vertical time base generator requires pomi-~ © Coen tive synch pulses this can essily bs achieved by replacing

XNOR 41 by an exclusive OR gate.

Whilst in the systems shown in FIG, 2 and 4, switch- ing between only two moldes has been shown, it will be evi- dent to one skilled in the art that swigching between up to four modes can be achieved by looking at combinations of the polarity of both the horizontal and vertical synch signals. Thus, by expanding the control circuitry to be responsive to the polarity of both synch signals, up to four horizontal time base frequencies could be selected,

In addition, by also controlling the vertical time base frequencyy the four modes could encompass various display formats with widely varying displeys. Furthermore, by the use of two control lines to the color logic means, line structures of up to four differing color signal formats could be used.

While the invention has been described by reference to specific embodiments, it will be clear to persons skilled in the art that various other modifications in form and de- tail may be made without deparing from the spirit and scope of the following claims, / ; wo 19 w

Claims (1)

1. WE CLAlMs. le A digital display aystem including a com puter display adapter for generating color signals in parallel form and horizontal end vertical synchroniging pulses, and a dizplay monitor for generating a raster scan display on a mthode ray tube in response to said signals and pulses, said monitor including comtrel cir cuit means responsive to positive—going and negative «—go- ing vertical synchroniging pulsea for providing first and second control signals respectively, and a horizontal time Cow . base generator coupled to receive said control signals for - EE operation at first and second frequencies in response res- pectively to said first and second control signals where~ by the line structure of the raster scan display varies in accordance with the pelarity of vertical synchronizing pulses generated by said adapter,

   2. A digital display system according to Claim 1, including a plurality of lines for coupling said color signale from the adaptor to the display monitor, said adapter generating said color signals selectively as first groups on all, or as second groups on some, but less than all, of said lines, with the polarity of generated vertical synchronizing pulses varying in correspondence with the groups, in which said monitor includes logic means receiwv- ing maid plurality of lines, having a like plurality of - 20 w output lines and having a further input line for re- ceiving outputs from said control circuit means indie cative of the polarity of received vertical synchronig- ing pulses, said logic means being responsive to said out- puts to pass said first groups of color signals to said output lines unchanged and to encode the sscond groups into signals on all the output lines, 3e A dgital display system according to Claim 2 ip which said logic means comprises a read only memorys 4, A digital display system including a display monitor coupled to receive parallel digital color signals oo end horizontal and vertical synchronizing pulses trains from a computer display adapter to develop a raster scan display on a cathode ray tube, comprising control cire cuit means in the monitor, responsive differentially te positive-going and negative~-going vertical synchroniging pulse trains to generate respective control signals for switching the frequency of horizontal time base generator means and thereby altering the line structure of the dis- playe 5, A digital display system according to Claim 4, comprising a plurality of signal lines for carrying said parallel digital signals and logic means having inputs coupled to said lines, a further input for receiving con— Vv] trol signals from said control circuit means and output “ 2h ve lines corresponding to said signal lines and switchable in response to sets of parallel digital signals on all the signal lines accompanied by firat control signals to direct the sets of parallel signals to the output lines unchanged and in response to sets of parallel digital signals to some, but less than all, the signal lines and accourpanied by second control signals to encode the sets of parallel signals for generating corresponding sets of out put signals on all the output lines.

   6. A digital display system according to Claim 4, tro ett vw oomprising means for coupling control signals from said . i. control circuit means to width control means in said hori- zontal time base generator to switch the width of said raster scan display in response to said control signals, Te A digital display system according to Claim 4 comprising further logic means receiving said vertical synchronizing pulses and said control signals to develop vertical synchronization pulses of fixed polarity for input to vertical time base generating means. 8, A digital display system according to Claim

   . Ts in which said further logic means consiste of an ex clusive NOR circuit, DARWIN Fo BRACKLEY JESUS A. SAENZ ; PAUL S, YOSIM Inventors