OA20478A - "Vertical light-emitting diode" - Google Patents

Abstract

A light-emitting diode according to one embodiment comprises: a first conductive semiconductor layer; an upper insulating layer positioned on the first conductive semiconductor layer; a mesa, which comprises an active layer and a second conductive semiconductor layer, is positioned under a certain region of the first conductive semiconductor layer so as to expose the edge of the first conductive semiconductor layer, and comprises first and second through holes through which the first conductive semiconductor layer is exposed; a first electrode comprising first contact parts electrically connected to the first conductive semiconductor layer through the first through holes and second contact parts electrically connected to the first conductive semiconductor layer through the second through holes; a second electrode electrically connected to the second conductive semiconductor layer; and at least one upper electrode pad connected to the second electrode, wherein the first through holes are arranged in a region encompassed by the edge of the mesa, the second through holes are arranged along the edge of the mesa so that some of the second through holes are encompassed by the active layer and the second conductive semiconductor layer, respectively, and the upper insulating layer comprises a plurality of material layers.

Description

VERTICAL LIGHT-EMITTING DIODE

[Technical Field]

[1] Embodiments of the présent disclosure relate to a light emitting diodeand, more particularly, to a vertical light emitting diode having improved current spreading performance.

[Background Art]

[2] In general, group IH-based nitride semiconductors, such as gallium nitride (GaN) and aluminum nitride (AIN), hâve good thermal stability and a direct transition energy-band structure, and thus hâve been spotlighted as materials for light emitting devices emitting light in the visible range and in the UV range.

[3] Such group Ill-based nitride semiconductor layers are grown on a heterogeneous substrate having a similar crystal structure by métal organic Chemical vapor déposition (MOCVD) or molecular beam epitaxy (MBE) due to diffïculty in fabrication of a homogeneous substrate capable of growing the group Ill-based nitride semiconductor layers. As the heterogeneous substrate, a sapphire substrate having a hexagonal crystal structure is generally used. However, since sapphire is an electrically non-conductive material, sapphire restricts the structure of a light emitting diode. Accordingly, there hâve been developed a technique for manufacturing a high efficiency vertical light emitting diode, in which épitaxial layers such as nitride semiconductor layers are grown on a heterogeneous substrate, such as a sapphire substrate, and a support substrate is bonded to the épitaxial layers, followed by separating the heterogeneous substrate through laser lift-off or the like.

[4] Generally, a vertical light emitting diode has better current spreading performance than a typical latéral type light emitting diode and exhibits good heat dissipation performance through adoption of a support substrate having higher thermal conductivity than sapphire. In addition, a reflective métal layer may be formed between the support substrate and the semiconductor layers to reflect light traveling towards the support substrate, thereby improving light extraction efficiency. [5] Further, the vertical light emitting diode can improve light extraction efficiency through a roughened surface of an épitaxial layer (n-type semiconductor layer) through which light is emitted. To this end, the épitaxial layers are subjected to wet etching such as photo-enhanced Chemical (PEC) etching. The roughened surface of the épitaxial layer must be protected from an external environment. In particular, since a light emitting diode emitting short wavelength UV light including a nitride épitaxial layer containing Al, such as AlGaN, is vulnérable to moisture, there is a need for protection of the light emitting diode.

[6] The vertical light emitting diode generally employs a conductive support substrate and includes an anode pad on the support substrate and a cathode pad on the épitaxial layers. In addition, an electrode extension extending from the cathode pad and electrically contacting the épitaxial layers is used to assist in current spreading within the épitaxial layers. The electrode extension may be formed not only in a central région of the light emitting diode, but also near edges of the épitaxial layers to evenly distribute the current over a large area of the épitaxial layers. However, since the cathode pad and the electrode extension are disposed on an épitaxial layer through which light is emitted, light émission is blocked by the cathode pad and the electrode extension, thereby deteriorating luminous efficacy of the light emitting diode.

[Disclosure]

[Technical Problem]

[7] Embodiments of the present disclosure provide a vertical light emitting diode having a new structure capable of achieving more uniform current spreading over a large area.

[8] Embodiments of the present disclosure provide a light emitting diode having a vertical structure capable of preventing moisture intrusion from an external environment.

[Technical Solution]

[9] In accordance with one embodiment of the présent disclosure, a light emitting diode includes: a support substrate; a first conductivity type semiconductor layer disposed on the support substrate; an upper insulation layer disposed on the first conductivity type semiconductor layer; and a mesa including an active layer and a second conductivity type semiconductor layer and disposed under a partial région of the first conductivity type semiconductor layer to expose an edge of the first conductivity type semiconductor layer, the mesa having first through-holes and the second through-holes exposing the first conductivity type semiconductor layer through the second conductivity type semiconductor layer and the active layer; a first electrode disposed between the second conductivity type semiconductor layer and the support substrate and including first contact portions electrically connected to the first conductivity type semiconductor layer through the first through-holes and second contact portions electrically connected to the first conductivity type semiconductor layer through the second through-holes; a second electrode disposed between the first electrode and the second conductivity type semiconductor layer and electrically connected to the second conductivity type semiconductor layer; and at least one upper electrode pad disposed adjacent to the first conductivity type semiconductor layer and connected to the second electrode, wherein each of the first through-holes is surrounded by the active layer and the second conductivity type semiconductor layer and is disposed within a région surrounded by edges of the mesa, each of the second through-holes is partially surrounded by the active layer and the second conductivity type semiconductor layer and is disposed along the edge of the mesa, and the upper insulation layer includes a plurality of material layers.

[Advantageous Effects]

[10] Embodiments of the présent disclosure provide a vertical light emitting diode that can achieve even spreading of electric current over the entire région of a mesa through first contact portions formed in first through-holes arranged along an edge of a mesa. Further, the vertical light emitting diode includes an upper insulation layer composed of a plurality of material layers to prevent nitride semiconductor layers from being damaged due to an extemal environment, such as moisture and the like, thereby improving reliability of the light emitting diode.

[11] The above and other features and advantages of the présent disclosure will become apparent from the following detailed description.

[Description of Drawings]

[12] FIG. 1 is a schematic plan view of a light emitting diode according to one embodiment of the présent disclosure.

[13] FIG. 2is a cross-sectional view taken along line A-A of FIG. 1.

[14] FIG. 3A, FIG. 3B, FIG. 4A, FIG. 4B, FIG. 5A, FIG. 5B, FIG. 6A, FIG. 6B,

FIG. 7A, andFIG. 7B are plan views and sectional views illustrating a method of manufacturing the light emitting diode according to the one embodiment of the présent disclosure.

[15] FIG. 8is a schematic plan view of a light emitting diode according to another embodiment of the présent disclosure.

[16] FIG. 9shows images of luminous patterns of typical light emitting diodes and a light emitting diode according to one embodiment of the présent disclosure.

[17] FIG. 10 is an exploded perspective view of a lighting apparatus to which a light emitting diode according to embodiments of the présent disclosure is applied.

[18] FIG. 11 is a cross-sectional view of one embodiment of a display apparatus to which a light emitting diode according to embodiments of the présent disclosure is applied.

[19] FIG. 12 is a cross-sectional view of another embodiment of a display apparatus to which a light emitting diode according to embodiments of the présent disclosure is applied.

[20] FIG. 13 is a cross-sectional view of a headlight to which a light emitting diode according to embodiments of the présent disclosure is applied.

[Best Mode]

[21] Hereinafter, embodiments of the présent disclosure will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so as to fully convey the spirit of the présent disclosure to those skilled in the art to which the présent disclosure pertains. Accordingly, the présent disclosure is not limited to the embodiments disclosed herein and can also be implemented in different forms. In the drawings, widths, lengths, thicknesses, and the like of éléments can be exaggerated for clarity and descriptive purposes.

[22] In accordance with one embodiment of the présent disclosure, a light emitting diode includes: a support substrate; a first conductivity type semiconductor layer disposed on the support substrate; an upper insulation layer disposed on the first conductivity type semiconductor layer; a mesa including an active layer and a second conductivity type semiconductor layer disposed under a partial région of the first conductivity type semiconductor layer to expose an edge of the first conductivity type semiconductor layer, the mesa having first through-holes and the second through-holes exposing the first conductivity type semiconductor layer through the second conductivity type semiconductor layer and the active layer; a first electrode disposed between the second conductivity type semiconductor layer and the support substrate and including first contact portions electrically connected to the first conductivity type semiconductor layer through the first through-holes and second contact portions electrically connected to the first conductivity type semiconductor layer through the second through-holes; a second electrode disposed between the first electrode and the second conductivity type semiconductor layer and electrically connected to the second conductivity type semiconductor layer; and at least one upper electrode pad disposed adjacent to the first conductivity type semiconductor layer and connected to the second electrode, wherein each of the first through-holes are surrounded by the active layer and the second conductivity type semiconductor layer and is disposed within a région surrounded by an edge of the mesa, each of the second through-holes is partially surrounded by the active layer and the second conductivity type semiconductor layer and is disposed along the edge of the mesa, and the upper insulation layer includes a plurality of material layers.

[23] The first conductivity type semiconductor layer may hâve a roughened surface. In one embodiment, the upper insulation layer may include a first layer covering the roughened surface of the first conductivity type semiconductor layer, a second layer covering the first layer and having a higher refractive index than the first layer, and a third layer covering the second layer and having a lower refractive index than the second layer. For example, the first layer and the third layer may include SiChand the second layer may include AI2O3. The first layer may hâve a greater thickness than the second layer and the third layer. The upper insulation layer may include an AbOslayer covering the roughened surface of the first conductivity type semiconductor layer and a SiO₂ layer covering the A1₂O₃ layer.

[24] The first conductivity type semiconductor layer may include an Alcontaining nitride semiconductor layer.

[25] The support substrate may hâve a rectangular shape. In one embodiment, the upper electrode pad may extend along one edge of the support substrate to be longitudinally disposed between one edge of the mesa and one edge of the support substrate. Furthermore, some of the second through-holes may be disposed between the upper electrode pad and the mesa.

[26] In another embodiment, two upper electrode pads may be disposed near opposite corners of the support substrate along one edge of the support substrate. Further, a partial région of the mesa may be disposed between the two upper electrode pads and some of the second through-holes may be formed in the partial région of the mesa disposed between the two upper electrode pads.

[27] The second through-holes may be arranged to be disposed adjacent four edges of the support substrate.

[28] The light emitting diode may hâve a mirror symmetry structure. With this structure, the light emitting diode can symmetrically spread electric current.

[29] The light emitting diode may further include: a first insulation layer insulating the first electrode from the first conductivity type semiconductor layer; and a second insulation layer interposed between the first electrode and the second electrode. Further, the light emitting diode may further include a reflection layer disposed between the second insulation layer and the first electrode. The reflection layer may include a distributed Bragg reflector.

[30] The light emitting diode may further include: a bonding métal layer interposed between the first electrode and the support substrate; and a first electrodeprotecting métal layer interposed between the bonding métal layer and the first electrode and covering the first electrode.

[31 ] The second electrode may include an ohmic reflection layer forming ohmic contact with the second conductivity type semiconductor layer and a protective métal layer protecting the ohmic reflection layer. The protective métal layer may extend outside the first conductivity type semiconductor layer and the upper electrode pad may be connected to the protective métal layer. In one embodiment, the upper electrode pad may be connected to the protective métal layer through the upper insulation layer and the first insulation layer.

[32] The light emitting diode may further include a second insulation layer interposed between the first electrode and the second electrode and covering a side surface of the protective métal layer.

[33] Hereinafter, embodiments of the présent disclosure will be described in detail with reference to the accompanying drawings.

[34] FIG. lis a schematic plan view of a light emitting diode according to one embodiment of the présent disclosure and FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1.

[35] Referring to FIG. landFIG. 2, a light emitting diode 100 includes a support substrate51, a semiconductor stack structure30, a first insulation layer31, a second insulation layer37, a first electrode39, a second electrode34, a first electrodeprotecting métal layer41, a bonding métal layer45, an upper insulation layer53, and upper electrode pads55. The semiconductor stack structure 30 may include a first conductivity type semiconductor layer 25, an active layer 27 and a second conductivity type semiconductor layer 29, and the second electrode 34 may include an ohmic reflection layer 33 and a protective métal layer 35.

[36] The support substrate 51 is distinguished from a growth substrate for growing compound semiconductor layers and refers to a secondary substrate attached to the grown compound semiconductor layers. The support substrate 51 may be a conductive substrate, such as a métal substrate or a semiconductor substrate, without being limited thereto. Alternatively, the support substrate 51 may be an insulating substrate, such as a sapphire substrate. The support substrate 51 may hâve a substantially rectangular shape, specifically a square shape.

[37] The semiconductor stack structure 30 is disposed on the support substrate 51 and includes the second conductivity type semiconductor layer 29, the active layer 27 and the first conductivity type semiconductor layer 25. The second conductivity type semiconductor layer 29 may be a p-type nitride semiconductor layer and the first conductivity type semiconductor layer 25 may be an n-type nitride semiconductor layer, or vice versa. The semiconductor stack structure 30 is disposed in some région of the support substrate 51. That is, the support substrate 51 has a larger area than the semiconductor stack structure 30 and the semiconductor stack structure 30 is disposed within a région surrounded by an edge of the support substrate 51.

[38] The first conductivity type semiconductor layer 25, the active layer 27 and the second conductivity type semiconductor layer 29 may be formed of III-N based compound semiconductors, for example, (Al,Ga,In)N semiconductors. Each of the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 29 may be composed of a single layer or multiple layers. For example, the first conductivity type semiconductor layer 25 and/or the second conductivity type semiconductor layer 29 may include a contact layer and a clad layer, and may also include a super-lattice layer. In addition, a roughened surface R may be formed on an upper surface of the first conductivity type semiconductor layer 25. The active layer 27 may hâve a single quantum well structure or a multiple quantum well structure. In one embodiment, the active layer may be adapted to émit UV light and the first conductivity type semiconductor layer may include an Alcontaining nitride semiconductor layer, such as AlGaN or AlInGaN.

[39] The semiconductor stack structure 30 may include a mesa M disposed under the first conductivity type semiconductor layer 25. The mesa M includes the second conductivity type semiconductor layer 29 and the active layer 27 and is disposed under some région of the first conductivity type semiconductor layer 25. With this structure, a lower surface of the first conductivity type semiconductor layer 25 is exposed around the mesa M. The mesa M also has first through-holes32a and second through-holes32bformed through the second conductivity type semiconductor layer 29 and the active layer 27 to expose the first conductivity type semiconductor layer 25.

[40] The first through-holes 32a are disposed within a région surrounded by an edge of the mesa M. Each of the first through-holes 32a is surrounded by the active layer 27 and the second conductivity type semiconductor layer 29. The first throughholes 32a are arranged at substantially constant intervals and are spaced apart from the edge of the mesa M.

[41] Each of the second through-holes 32b is partially surrounded by the active layer 27 and the second conductivity type semiconductor layer 29. The second through-holes 32b are disposed along the edge of the mesa M and the first conductivity type semiconductor layer25 exposed through the second through-holes 32b is connected to the first conductivity type semiconductor layer27 exposed around the mesa M.

[42] The second through-holes 32b are indented from the edge of the mesa M into the mesa M. With this structure, a light emitting région can be secured between adjacent second through-holes 32b, thereby preventing réduction in light emitting area.

[43] As shown in FIG. 4A, the second through-holes 32b may be disposed along each of four edges of the mesa M, thereby enabling even spreading of electric current in edge régions of the mesa M.

[44] The second through-holes 32bmay be disposed at constant intervals, but are not limited thereto. For example, a distance between adjacent second through-holes 32bmay be changed depending upon arrangement of the upper electrode pads 55. In one embodiment, a distance between the second through-holes 32bin a région between the upper electrode pads 55may be smaller than a distance between the first through-holes 32a.

[45] In addition, a distance between the first through-hole 32a and the second through-hole32b may be greater than or equal to the distance between the first through-holes 32a.

[46] The first insulation layer 31 is disposed between the semiconductor stack structure 30 and the support substrate 51 and covers the first conductivity type semiconductor layer 25 exposed around the mesa M and the first conductivity type semiconductor layer 25 exposed through the first and second through-holes32a, 32b.

The first insulation layer 31 may also cover a side surface of the mesa M and a portion of a lower surface of the mesa M. In addition, the first insulation layer 31 may extend outward from the semiconductor stack structure 30. Here, the first insulation layer 31 has openings formed in the first and second through-holes 32a, 32b to expose the first conductivity type semiconductor layer 25 such that the first electrode 39 is connected to the first conductivity type semiconductor layer 25 therethrough, and openings which expose the lower surface of the mesa M such that the second electrode 34 is connected to the second conductivity type semiconductor layer 29 therethrough.

[47] The first insulation layer 31 may be composed of a single layer or multiple layers of Silicon oxide or Silicon nitride, or may include a distributed Bragg reflector in which insulation layers having different refractive indices, such as SiCh/TiCh or SiO2/Nb2O5, are repeatedly stacked one above another.

[48] The ohmic reflection layer 33 forms ohmic contact with the second conductivity type semiconductor layer 29 exposed through trenches of the first insulation layer 31. The ohmic reflection layer 33 may be formed to adjoin the first insulation layer 31 or may hâve an edge spaced apart from the first insulation layer 31, as shown in the drawings. The ohmic reflection layer 33 may include a reflection layer formed of, for example, Ag, and may include a métal layer for ohmic contact, such as a Ni layer. The ohmic reflection layer 33 is confined in a région under the mesa Μ.

[49] The protective métal layer 35 is disposed between the ohmic reflection layer 33 and the support substrate 51 and covers the ohmic reflection layer 33. The protective métal layer 35 may contact the second conductivity type semiconductor layer 29 exposed between the ohmic reflection layer 33 and the first insulation layer 31. The protective métal layer 35 also covers the first insulation layer 31 and extends outside a région under the semiconductor stack structure 30. The protective métal layer 35 exposes the first insulation layer 31 under the first and second throughholes 32a, 32b of the mesa M.

[50] The protective métal layer 35 prevents migration of métal éléments, for example, Ag, from the ohmic reflection layer 33 and also prevents the side surface of the ohmic reflection layer 33 from being exposed to the outside. The protective métal layer 35 may include, for example, Pt, Ni, Ti, W, Au, or alloys thereof.

[51] The second insulation layer 37 is disposed under the protective métal layer 35 to cover the protective métal layer 35. The second insulation layer 37 may cover the entire lower surface of the protective métal layer 35. In addition, the second insulation layer 37 may also cover a side surface of the protective métal layer 35 to prevent the side surface of the protective métal layer 35 from being exposed to the outside.

[52] The second insulation layer 37 may be composed of a single layer or multiple layers of Silicon oxide or Silicon nitride, or may be a distributed Bragg reflector in which insulation layers having different indices of refraction, such as SiO₂/TiO₂ or SiO₂/Nb₂O5, are repeatedly stacked one above another.

[53] The first electrode 39 is disposed between the second insulation layer 37 and the support substrate 51 and is electrically connected to the first conductivity type semiconductor layer 25 through the first insulation layer 31 and the second insulation layer 37. The first electrode 39 is disposed between the second electrode 34 and the support substrate 51.

[54] The first electrode 39 includes first contact portions 39a connected to the first conductivity type semiconductor layer 25 in the first through-holes 32a and second contact portions 39b connected to the first conductivity type semiconductor layer 25 in the second through-holes 32b. The first contact portions 39a and the second contact portions 39b are insulated from the mesa M by the first insulation layer 31 and the second insulation layer 37.

[55] The first electrode 39 may include an ohmic contact layer for ohmic contact with the first conductivity type semiconductor layer 25 and may also include a reflective métal layer. For example, the first electrode 39 may include Cr/Al, and may further include Ti/Ni.

[56] The first electrode-protecting métal layer 41 may cover a lower surface of the first electrode 39. The first electrode-protecting métal layer 41 protects the first electrode 39 by preventing diffusion of métal éléments such as Sn from the bonding métal layer 45. The first electrode-protection métal layer 41 may include, for example, Au, and may further include Ti and Ni. The first electrode-protection métal layer 41 may be formed by, for example, repeatedly stacking Ti/Ni plural times, followed by stacking Au thereon.

[57] The support substrate 51 may be bonded to the first electrode-protecting métal layer 41 via the bonding métal layer 45. The bonding métal layer 45 may be formed of, for example, AuSn or NiSn. Alternatively, the support substrate 51 may be formed on the first electrode-protecting métal layer 41 by, for example, plating. If the support substrate 51 is a conductive substrate, the support substrate 51 can act as a lower electrode pad. Alternatively, if the support substrate 51 is an insulating substrate, a lower electrode pad may be formed on the first electrode 39 or the first electrode-protecting métal layer 41 disposed on the support substrate 51.

[58] The upper insulation layer 53 may cover upper and side surfaces of the semiconductor stack structure 30, particularly, upper and side surfaces of the first conductivity type semiconductor layer 25. The upper insulation layer 53 covers the roughened surface R and may be formed along protrusions and dépréssions of the roughened surface R.

[59] The upper insulation layer 53 may hâve a structure in which multiple material layers are stacked one above another. Referring to an enlarged portion of a cross-sectional view of FIG. 2, the upper insulation layer 53 may include a first layer53a covering the roughened surface R of the first conductivity type semiconductor layer25, a second layer53b covering the first layer53a, and a third layer53c covering the second layer53b.

[60] In one embodiment, the first layer 53a covering the roughened surface R of the first conductivity type semiconductor layer 25 may include SiCh. The second layer 53b may include AI2O3 and the third layer 53c may include S1O2. The first layer 53a may hâve a larger thickness than the second layer 53b and the third layer 53c. The thickness of the second layer53b may be larger than or equal to the thickness of the third layer53c. For example, the first layer53a may hâve a thickness of 400nm, and the second layer53b and the third layer53c may hâve a thickness of about 60nm.

[61] The upper insulation layer 53 may be composed of multiple material layers to prevent external moisture from entering the light emitting diode. In particular, use of AhOafor the upper insulation layer can prevent damage to the nitride semiconductor layer due to moisture. In particular, for a UV light emitting diode, the first conductivity type semiconductor layer25 may include an Al-containing nitride semiconductor layer, which is vulnérable to moisture infiltration. Accordingly, with the upper insulation layer 53 comprising AI2O3, the light emitting diode can hâve improved reliability.

[62] Further, uniformity of light emitted from the light emitting diode can be improved through control of the refractive indices of the first conductivity type semiconductor layer25, the first layer53a, the second layer53b, and the third layer53c.

[63] By way of example, the first conductivity type semiconductor layer 25has a refractive index of about 2.4, SiCh has a refractive index of about 1.54, and AI2O3 has a refractive index of about 1.77. As such, the first conductivity type semiconductor layer 25 has a higher refractive index than the first layer 54a, whereby total internai reflection of light can occur at an interface between the first conductivity type semiconductor layer 25 and the first layer 54a.In addition, the second layer 53bhas a higher refractive index than the third layer 53c, whereby total internai reflection of light can occur at an interface between the second layer 53b and the third layer 53c.

[64] On the other hand, light reflected by total internai reflection at the interface between the second layer 53b and the third layer 53c travels to an interface between the second layer 53b and the first layer 53a and at least partially reflected again by total internai reflection at the interface therebetween. As such, since part of light traveling from the second layer 53b to the third layer 53c undergoes total internai reflection at the interface between the second layer 53b and the third layer 53c and part of the light having undergone the total internai reflection further undergoes total internai reflection at the interface between the second layer 53b and the first layer 53a, horizontal light diffusion occurs in the second layer 53b.

[65] Total internai reflection of light at the interface between the second layer 53b and the third layer 53c and total internai reflection of the light at the interface between the second layer and the first layer can improve light uniformity of the light emitting diode. Further, total internai reflection of light at the interface between the first conductivity type semiconductor layer 25 and the first layer 53a can also improve light uniformity of the light emitting diode according to the embodiment.

[66] Although the upper insulation layer 53 is illustrated as including the first to third layers 53a, 53b, 53c in this embodiment, it should be understood that other implémentations are possible. For example, the upper insulation layer 53 may be composed of two layers or a greater number of material layers. Here, the upper insulation layer 53 may include an AbOslayer and a SiCh layer covering the AI2O3 layer. The AbOslayermay adjoin the surface of the first conductivity type semiconductor layer 25. For the upper insulation layer 53 composed of two layers of AI2O3 and S1O2, the AI2O3 layer may hâve a smaller thickness than the SiChlayer. For example, the AI2O3 layer may hâve a thickness of about 100 nm to about 200nm and the S1O2 layer may hâve a thickness of about 300 nm to about 500nm.

[67] The AI2O3 layer may be formed by, for example, atomic layer déposition, which forms a thin layer having a high density. The AI2O3 layer formed by atomic layer déposition has high density and exhibits good layer covering properties, thereby securing excellent moisture blocking performance.

[68] The upper insulation layer 53 may hâve holes 53h that expose the protective métal layer 35. The holes 53h may be formed through the first insulation layer 31 to expose the protective métal layer 35.

[69] The upper electrode pads 55 are connected to the second electrode 34, for example, the protective métal layer 35, adjacent to the first conductivity type semiconductor layer 25. The upper electrode pads 55 may be disposed near opposite corners of one edge of the support substrate 51 and may be separated from the semiconductor stack structure 30 in the horizontal direction. The upper electrode pads 55 may be connected to the protective métal layer 35 through the holes 53h that are formed through the first insulation layer 31 and the upper insulation layer 53.

[70] The upper electrode pads 55 are insulated from the first conductivity type semiconductor layer 25. The upper electrode pads 55 are also separated from the first electrode 39.

[71] An élévation of a plane in which the upper electrode pads 55 adjoin the protective métal layer 35 may be placed in a région between the first conductivity type semiconductor layer 25 and the ohmic reflection layer 33, that is, in a région between a lower surface of the first conductivity type semiconductor layer 25 and a lower surface of the second conductivity type semiconductor layer 29. Accordingly, bottom surfaces of the upper electrode pads 55 are placed under the lower surface of the first conductivity type semiconductor layer 29 while being placed above the lower surface of the second conductivity type semiconductor layer 29. The first insulation layer 31 is placed between the lower surface of the first conductivity type semiconductor layer 25 and the protective métal layer 35. With the structure wherein the élévation of the upper electrode pads 55 is placed above the lower surface of the second conductivity type semiconductor layer 29, various processes for forming the upper electrode pads 55 can be easily performed, thereby enabling a process of manufacturing a light emitting diode to be efficiently performed.

[72] According to this embodiment, the light emitting diode 100 may hâve a mirror symmetry structure as shown in FIG. 1, thereby enabling even spreading of electric current over the entire région of the light emitting diode 100.

[73] FIG. 3A, FIG. 3B, FIG. 4A, FIG. 4B, FIG. 5A, FIG. 5B, FIG. 6A, FIG. 6B, FIG. 7A and FIG. 7B are plan views and sectional views illustrating a method of manufacturing the light emitting diode according to the embodiment of the présent disclosure. The structure of the light emitting diode according to the embodiment will become more apparent through the method of manufacturing the light emitting diode described below.

[74] Referring to FIG. 3A and FIG. 3B, a semiconductor stack structure 30 including a first conductivity type semiconductor layer 25, an active layer 27 and a second conductivity type semiconductor layer 29 is formed on a growth substrate 21. The growth substrate 21 may be a sapphire substrate, without being limited thereto. Altematively, the growth substrate 21 may be a different substrate, for example, a Silicon substrate. Each of the first and second conductivity type semiconductor layers 25, 29 may be composed of a single layer or multiple layers. The active layer 27 may hâve a single quantum well structure or a multiple quantum well structure.

[75] The compound semiconductor layers may be formed of III-N based compound semiconductors and may be grown on the growth substrate 21 by metalorganic Chemical vapor déposition (MOCVD), molecular beam epitaxy (MBE), or the like.

[76] Before forming the compound semiconductor layers, a nucléation layer may be formed. The nucléation layer serves to relieve lattice mismatch between the sacrificial substrate 21 and the compound semiconductor layers and may be a GaNbased material layer, such as gallium nitride or aluminum nitride.

[77] Then, the second conductivity type semiconductor layer 29 and the active layer 27 are subjected to patteming to expose the first conductivity type semiconductor layer 25. As a resuit, a mesa M is formed and first and second through-holes 32a, 32b are formed through the mesa M. As described above, the second through-holes 32b are arranged along edges of the mesa M and the first through-holes 32a are disposed in a région surrounded by the edges of the mesa M.

[78] Although FIG. 3A and FIG. 3B show a single light emitting diode région, it should be understood that a plurality of light emitting diode régions may be defined on a single growth substrate 21 and isolation régions may be disposed between these light emitting diode régions. In FIG. 3A, edges of the growth substrate 21 correspond to the isolation régions. In such isolation régions, the second conductivity type semiconductor layer 29 and the active layer 27 are removed to expose the first conductivity type semiconductor layer 25 during formation of the mesa M. Further, in régions P for upper electrode pads 55 described below, the second conductivity type semiconductor layer 29 and the active layer 27 are removed to expose the first conductivity type semiconductor layer 25. The second conductivity type semiconductor layer 29 and the active layer 27 are previously removed from the isolation régions and the upper electrode pad régions P, thereby facilitating a process of forming the upper electrode pads 55 described below and a process of isolating light emitting diodes.

[79] Referring to FIG. 4A and FIG. 4B, a first insulation layer 31 is formed to cover the mesa M. The first insulation layer 31 covers a side surface of the mesa M while covering the first conductivity type semiconductor layer 25 exposed around the mesa M and through the first and second through-holes 32a, 32b. The first insulation layer 31 may also partially cover an upper surface of the second conductivity type semiconductor layer 29. Here, the first insulation layer 31 exposes most of the upper surface of the second conductivity type semiconductor layer 29.

[80] The first insulation layer 31 may be deposited by plasma enhanced Chemical vapor déposition and may be patterned by photolithography and etching.

[81] Then, an ohmic reflection layer 33 is formed on the second conductivity type semiconductor layer 29. The ohmic reflection layer 33 may be deposited by électron beam évaporation and may be patterned by a lift-off process. A side surface of the ohmic reflection layer 33 may adjoin the first insulation layer 31 or may be separated therefrom, as shown in FIG. 4B.

[82] Thereafter, a protective métal layer 35 is formed on the ohmic reflection layer 33. The protective métal layer 35 covers an upper surface of the ohmic reflection layer 33 and surrounds an edge 33a of the ohmic reflection layer 33 to cover the edge 33a of the ohmic reflection layer 33. A portion of the protective métal layer 35 may contact the second conductivity type semiconductor layer 29 between the first insulation layer 31 and the ohmic reflection layer 33. Here, the protective métal layer 35 may form Schottky contact with the second conductivity type semiconductor layer 29. Thus, no current is injected directly into the second conductivity type semiconductor layer 29 through the protective métal layer 35, thereby preventing current from crowding near the side surface of the mesa M. Furthermore, the protective métal layer 35 including a reflection layer can reflect light incident around the ohmic reflection layer 33, thereby improving light extraction efficiency.

[83] The protective métal layer 35 exposes the first insulation layer 31 disposed in the first and second through-holes 32a, 32b. The protective métal layer 35 has through-holes having a similar shape to the first and second through-holes 32a, 32b and the first insulation layer 31 in the first and second through-holes 32a, 32b is exposed through the through-holes.

[84] A portion of the protective métal layer 35 covers the first insulation layer 31 around the mesa M and extends outside the mesa M. The protective métal layer 35 extending outside the mesa M is connected to the upper electrode pads 55 described below.

[85] A second insulation layer 37 is formed on the protective métal layer 35. The second insulation layer 37 covers upper and side surfaces of the protective métal layer 35. Accordingly, the second insulation layer 37 can prevent the protective métal layer 35 from being exposed to the outside. Alternatively, the second insulation layer 37 may be formed to cover the upper surface of the protective métal layer 35 without covering the side surface thereof such that the side surface of the protective métal layer 35 can be exposed to the outside in a completed light emitting diode.

[86] Referring to FIG. 5A and FIG. 5B, openings are formed to expose the first conductivity type semiconductor layer 25 in the first and second through-holes 32a,

32b through photolithography and etching processes on the second insulation layer 37 and the first insulation layer 31. Bottom surfaces of these openings correspond to first contact portions 39a and second contact portions 39b described below.

[87] A first electrode 39 is formed on the second insulation layer 37. The first electrode 39 covers the second insulation layer 37 and has the first contact portions 39a and the second contact portions 39 connected to the first conductivity type semiconductor layer 25 through the openings formed through the second insulation layer 37 and the first insulation layer 31. The first contact portions 39a are connected to the first conductivity type semiconductor layer 25 in a région surrounded by the edges of the mesa M and the second contact portions 39b are connected to the first conductivity type semiconductor layer 25 near the edges of the mesa M.

[88] A first electrode-protecting métal layer 41 is formed on the first electrode 39. The first electrode-protecting métal layer 41 is formed to prevent métal éléments, such as Sn and the like, from diffusing into the first electrode 39 and may include Ti, Ni and Au. The first electrode-protection métal layer 41 may be omitted.

[89] Referring to FIG. 6A and FIG. 6B, a support substrate 51 is attached to the semiconductor stack structure. The support substrate 51 may be manufactured separately from the semiconductor stack structure 30 and may be bonded to the first electrode 39 or the first electrode-protecting métal layer 41 via a bonding métal layer 45. Altematively, the support substrate 51 may be formed on the first electrode 39 or the first electrode-protecting métal layer 41 by plating.

[90] Next, the growth substrate 21 is removed to expose the surface of the first conductivity type semiconductor layer 25 of the semiconductor stack structure 30. The growth substrate 21 may be removed by, for example, a laser lift-off (LLO) process. After the growth substrate 21 is removed, the nitride semiconductor layer 25a may be partially removed by etching in order to remove a région damaged by laser processing.

[91] The first conductivity type semiconductor layer 25 is removed along régions for isolation of light emitting diodes. Here, the first conductivity type semiconductor layer 25 in régions P for formation of the upper electrode pads 55 is also removed. As the first conductivity type semiconductor layer 25 is removed, the first insulation layer 31 is exposed.

[92] As described above, since the second conductivity type semiconductor layer 29 and the active layer 27 are previously removed from the isolation régions and the upper electrode pad régions P upon formation of the mesa M, only the first conductivity type semiconductor layer 25 can be removed without removing the second conductivity type semiconductor layer 29 and the active layer 27, when the semiconductor layers are removed from the isolation régions. Accordingly, it is possible to reduce process time in removal of the first conductivity type semiconductor layer 25 from the isolation régions, thereby further simplifying the manufacturing process.

[93] In this embodiment, upon removal of the first conductivity type semiconductor layer 25, any other métal layers including the protective métal layer 35 are not exposed. Further, since the second conductivity type semiconductor layer 29 and the active layer 27 are sealed by the first insulation layer 31, short circuit due to etching by-products of the metallic materials does not occur, thereby securing high process reliability.

[94] On the other hand, a roughened surface R is formed on the surface of the first conductivity type semiconductor layer 25. The roughened surface R may be formed by a technique, such as photo-enhanced Chemical etching and the like.

[95] Although the roughened surface R is iilustrated as being formed after removal of the first conductivity type semiconductor layer 25 from the isolation régions in this embodiment, it should be understood that the roughened surface R may be formed before removal of the first conductivity type semiconductor layer 25 from the isolation régions.

[96] Referring to FIG. 7A and FIG. 7B, an upper insulation layer 53 is formed on the first conductivity type semiconductor layer 25 on which the roughened surface R is formed. The upper insulation layer 53 is formed along the roughened surface R to hâve a rough surface corresponding to the roughened surface R. The upper insulation layer 53 also covers the first insulation layer 31 exposed around the first conductivity type semiconductor layer 25.

[97] As described above, the upper insulation layer 53 may include first to third layers 53a, 53b, 53c, but is not limited thereto. Alternatively, the upper insulation layer 53 may include two layers of AhChand SiOaor a greater number of layers.

[98] Next, holes 53a are formed to expose the protective métal layer 35 by partially removing the upper insulation layer 53 and the first insulation layer 31. The holes 53a are formed in the upper electrode pad régions P such that the protective métal layer 35 extending to the upper electrode pad régions P is exposed. Then, the upper electrode pads 55 (see FIG. 1) are formed in the holes 53a and the semiconductor structure is divided into individual light emitting diodes along the isolation régions, thereby providing final light emitting diodes (see FIG. 1). Here, the first insulation layer 31, the second insulation layer 37, the first electrode 39, the first electrode-protecting métal layer 41, the bonding métal layer 45 and the support substrate 51 may also be divided together, whereby the side surfaces thereof may be parallel to each other. On the other hand, the ohmic reflection layer 33 and the protective métal layer 35 are disposed in a région surrounded by the edge of the divided support substrate and thus may be embedded in the light emitting diode without being exposed to the outside.

[99] In this embodiment, since the second conductivity type semiconductor layer 29 and the active layer 27 are previously removed from the upper electrode pad régions P upon formation of the mesa M, the first insulation layer 31 and the upper insulation layer 53 hâve an élévation closer to the surface of the first conductivity type semiconductor layer 25 in the upper electrode pad régions P than the case where the second conductivity type semiconductor layer 29 and the active layer 27 are not previously removed. Accordingly, the process of forming the holes 53a is facilitated, and even when the upper surfaces of the upper electrode pads 55 hâve a constant élévation, the overall thickness of the upper electrode pads 55 can be reduced, thereby providing convenience in formation of the upper electrode pads 55. [100] FIG. 8is a schematic plan view of a light emitting diode according to another embodiment of the présent disclosure.

[101] Referring to FIG. 8, alight emitting diode200 according to this embodiment is generally similar to the light emitting diode described with reference to FIG. 1 and FIG. 2 except that an upper electrode pad55alongitudinally extends along one edge of the support substrate51.

[102] Specifically, in the above embodiment, two upper electrode pads 55 are disposed near opposite corners of the support substrate51 to be separated from each other. In this embodiment, one upper electrode pad55a extends to the opposite corners of the support substrate51 along one edge thereof.

[103] The upper electrode pad55a may be connected to the protective métal layer 35 through a through-hole 53h formed through the upper insulation layer 53 and the first insulation layer 31. In this embodiment, the through-hole 53h has a similar shape to the upper electrode pad55a and longitudinally extends along the edge of the support substrate51. The protective métal layer 35 may be exposed over the entire lower région of the through-hole 53h.

[104] The second through-holes 32bare disposed along the edge of the mesa M. In particular, the second through-holes32 may be disposed near the edge of the mesa M adjacent to the upper electrode pad55a.

[105] FIG. 9shows images of luminous patterns of typical light emitting diodes and a light emitting diode according to one embodiment of the présent disclosure. FIG. 9(a) shows a luminous pattern of a light emitting diode having a vertical structure in which an anode pad is formed at a support substrate side, a cathode pad is formed on épitaxial layers and electrode extensions are formed. FIG. 9(b) shows a luminous pattern of a light emitting diode that is similar to the light emitting diode according to the one embodiment except that first contact portions are formed in the first through-holes without the second through-holes. FIG. 9(c) shows luminous patterns of the light emitting diode according to the one embodiment of the présent disclosure, in which the contact portions are formed in the first and second throughholes.

[106] Referring to FIG. 9(a), it can be seen that the cathode pad and the electrode extensions block light and uniform émission of light does not occur in a light emitting région.

[107] On the contrary, FIG. 9(b) shows that light is not blocked in a région outside the régions in which the upper electrode pads are formed. Here, it can be seen that light having relatively low intensity is emitted from the edge of the semiconductor stack structure.

[108] On the other hand, FIG. 9(c) shows that light is emitted through the overall région of the semiconductor stack structure. In particular, it can be seen that the light emitting diode emits a greater quantity of light through the edge of the semiconductor stack structure than the light emitting diode of FIG. 9(b).

[109] As can be seen from FIG. 9(b), in the structure wherein the second throughholes are omitted and only the first through-holes are présent, the light emitting area is reduced by the first through-holes and a smaller quantity of light is emitted from edge régions of the light emitting diode. On the contrary, as shown in FIG. 9(c), in the structure wherein the second through-holes are disposed in the edge régions of the light emitting diode, an effective light emitting area can be increased through réduction in the number of first through-holes. Furthermore, since the second through-holes are arranged in the edge régions of the light emitting diode, from which a smaller quantity of light is emitted, arrangement of the second throughholes does not reduce the effective light emitting area.

[110] As a resuit of measurement of intensity of light according to drive current, it could be confirmed that the light emitting diodes according to the embodiments of the présent disclosure had a higher intensity of light than conventional light emitting diodes and différence in intensity of light therebetween further increased with increasing electric current.

[111] FIG. 10 is an exploded perspective view of a lighting apparatus to which a light emitting diode according to one embodiment is applied.

[112] Referring to FIG. 10, the lighting apparatus according to this embodiment includes a diffusive cover 1010, a light emitting device module 1020, and a body 1030. The body 1030 may receive the light emitting device module 1020 and the diffusive cover 1010 may be disposed on the body 1030 to cover an upper side of the light emitting device module 1020.

[113] The body 1030 may hâve any shape so long as the body can supply electric power to the light emitting device module 1020 while receiving and supporting the light emitting device module 1020. For example, as shown in the drawing, the body 1030 may include a body case 1031, a power supply 1033, a power supply case 1035, and a power source connector 1037.

[114] The power supply 1033 is received in the power supply case 1035 to be electrically connected to the light emitting device module 1020, and may include at least one IC chip. The IC chip may regulate, change or control electric power supplied to the light emitting device module 1020. The power supply case 1035 may receive and support the power supply 1033 and the power supply case 1035 having the power supply 1033 secured therein may be disposed within the body case 1031. The power source connectorl037 is disposed at a lower end of the power supply case 1035 and is coupled thereto. Accordingly, the power source connector 1037 is electrically connected to the power supply 1033 within the power supply case 1035 and may serve as a passage through which power can be supplied from an external power source to the power supply 1033.

[115] The light emitting device module 1020 includes a substrate 1023 and a light emitting device 1021 disposed on the substrate 1023. The light emitting device module 1020 may be disposed at an upper portion of the body case 1031 and electrically connected to the power supply 1033.

[116] As the substrate 1023, any substrate capable of supporting the light emitting device 1021 may be used without limitation. For example, the substrate 1023 may include a printed circuit board having interconnects formed thereon. The substrate 1023 may hâve a shape corresponding to a securing portion formed at the upper portion of the body case 1031 so as to be stably secured to the body case 1031. The light emitting device 1021 may include at least one of the light emitting diodes according to the embodiments described above.

[117] The diffusive cover 1010 is disposed on the light emitting device 1021 and may be secured to the body case 1031 to cover the light emitting device 1021. The diffusive cover 1010 may be formed of a light transmitting material and light orientation of the lighting apparatus may be adjusted through régulation of the shape and optical transmissivity of the diffusive cover 1010. Thus, the diffusive cover 1010 may be modified to hâve various shapes depending on usage and applications of the lighting apparatus.

[118] FIG. 1 lis a cross-sectional view of one embodiment of a display apparatus to which a light emitting diode according to embodiments of the présent disclosure is applied.

[119] The display apparatus according to this embodiment includes a display panel 2110, a backlight unit supplying light to the display panel 2110, and a panel guide supporting a lower edge of the display panel 2110.

[120] The display panel 2110 is not particularly limited and may be, for example, a liquid crystal panel including a liquid crystal layer. Gâte driving PCBs may be further disposed at the periphery of the display panel 2110 to supply driving signais to a gâte line. Here, the gâte driving PCBs may be formed on a thin film transistor substrate instead of being formed on separate PCBs.

[121] The backlight unit includes a light source module which includes at least one substrate and a plurality of light emitting devices 2160. The backlight unit may further include a bottom cover 2180, a reflective sheet 2170, a diffusive plate 2131, and optical sheets 2130.

[122] The bottom cover 2180 may be open at an upper side thereof to receive the substrate, the light emitting devices 2160, the reflective sheet 2170, the diffusive plate 2131, and the optical sheets 2130. In addition, the bottom cover 2180 may be coupled to the panel guide. The substrate may be disposed under the reflective sheet 2170 to be surrounded by the reflective sheet 2170. Alternatively, when a reflective material is coated on a surface thereof, the substrate may be disposed on the reflective sheet 2170. Further, a plurality of substrates may be arranged parallel to one another, without being limited thereto. However, it should be understood that the backlight unit includes a single substrate.

[123] The light emitting devices 2160 may include at least one of the light emitting diodes according to the embodiments described above. The light emitting devices 2160 may be regularly arranged in a predetermined pattern on the substrate. In addition, a lens 2210 may be disposed on each of the light emitting devices 2160 to improve uniformity of light emitted from the plurality of light emitting devices 2160.

[124] The diffusive plate 2131 and the optical sheets 2130 are disposed above the light emitting device 2160. Light emitted from the light emitting devices 2160 may be supplied in the form of sheet light to the display panel 2110 through the diffusive plate 2131 and the optical sheets 2130.

[125] As such, the light emitting diodes according to the embodiments may be applied to direct type displays like the display apparatus according to this embodiment.

[126] FIG. 12 is a cross-sectional view of another embodiment of the display apparatus to which a light emitting diode according to embodiments of the present disclosure is applied.

[127] The display apparatus according to this embodiment includes a display panel 3210 on which an image is displayed, and a backlight unit disposed at a rear side of the display panel 3210 and emitting light thereto. Further, the display apparatus includes a frame 3240 supporting the display panel 3210 and receiving the backlight unit, and covers 3270, 3280 surrounding the display panel 3210.

[128] The display panel 3210 is not particularly limited and may be, for example, a liquid crystal panel including a liquid crystal layer. A gâte driving PCB may be further disposed at the periphery of the display panel 3210 to supply driving signais to a gâte line. Here, the gâte driving PCB may be formed on a thin film transistor substrate instead of being formed on a separate PCB. The display panel 3210 is secured by the covers 3270, 3280 disposed at upper and lower sides thereof, and the cover 3280 disposed at the lower side of the display panel 3210 may be coupled to the backlight unit.

[129] The backlight unit supplying light to the display panel 3210 includes a lower cover 3270 partially open at an upper side thereof, a light source module disposed at one side inside the lower cover 3270, and a light guide plate 3250 disposed parallel to the light source module and converting spot light into sheet light. In addition, the backlight unit according to this embodiment may further include optical sheets 3230 disposed on the light guide plate 3250 to spread and collect light, and a reflective sheet 3260 disposed at a lower side of the light guide plate 3250 and reflecting light traveling in a downward direction of the light guide plate 3250 towards the display panel 3210.

[130] The light source module includes a substrate 3220 and a plurality of light emitting devices 3110 arranged at constant intervals on one surface of the substrate 3220. As the substrate 3220, any substrate capable of supporting the light emitting devices 3110 and being electrically connected thereto may be used without limitation. For example, the substrate 3220 may include a printed circuit board. The light emitting devices 3110 may include at least one of the light emitting diodes according to the embodiments described above. Light emitted from the light source module enters the light guide plate 3250 and is supplied to the display panel 3210 through the optical sheets 3230. The light guide plate 3250 and the optical sheets 3230 couvert spot light emitted from the light emitting devices 3110 into sheet light.

[131] As such, the light emitting diodes according to the embodiments may be applied to edge type displays like the display apparatus according to this embodiment.

[132] FIG. 13 is a cross-sectional view of a headlight to which a light emitting diode according to embodiments of the présent disclosure is applied.

[133] Referring to FIG. 13, the headlight according to this embodiment includes a lamp body 4070, a substrate 4020, a light emitting device 4010, and a cover lens 4050. The headlight may further include a heat dissipation unit 4030, a support rack 4060, and a connection member 4040.

[134] The substrate 4020 is secured by the support rack 4060 and is disposed above the lamp body 4070. As the substrate 4020, any member capable of supporting the light emitting device 4010 may be used without limitation. For example, the substrate 4020 may include a substrate having a conductive pattern, such as a printed circuit board. The light emitting device 4010 is disposed on the substrate 4020 and may be supported and secured by the substrate 4020. In addition, the light emitting device 4010 may be electrically connected to an external power source through the conductive pattern of the substrate 4020. Further, the light emitting device 4010 may include at least one of the light emitting diodes according to the embodiments described above.

[135] The cover lens 4050 is disposed on a path of light emitted from the light emitting device 4010. For example, as shown in the drawing, the cover lens 4050 may be separated from the light emitting device 4010 by the connection member 4040 and may be disposed in a direction of supplying light emitted from the light emitting device 4010. By the cover lens 4050, an orientation angle and/or a color of light emitted by the headlight can be adjusted. On the other hand, the connection member 4040 is disposed to secure the cover lens 4050 to the substrate 4020 while surrounding the light emitting device 4010, and thus may act as a light guide that provides a luminous path 4045. The connection member 4040 may be formed of a light reflective material or coated therewith. On the other hand, the heat dissipation unit 4030 may include heat dissipation fins 4031 and/or a heat dissipation fan 4033 to dissipate heat generated upon operation of the light emitting device 4010.

[136] As such, the light emitting diodes according to the embodiments may be applied to headlights, particularly, headlights for vehicles, like the headlight according to this embodiment.

[137] Although some embodiments hâve been described herein, it should be understood that these embodiments are provided for illustration only and are not to be construed in any way as limiting the présent disclosure. It should be understood that features or components of one embodiment can also be applied to other embodiments without departing from the spirit and scope of the présent disclosure.

Claims (10)

1. [Claim 1 ]

   A light emitting diode comprising:

   a support substrate;

   a first conductivity type semiconductor layer disposed on the support substrate;

   an upper insulation layer disposed on the first conductivity type semiconductor layer;

   a mesa comprising an active layer and a second conductivity type semiconductor layer and disposed under a partial région of the first conductivity type semiconductor layer to expose an edge of the first conductivity type semiconductor layer, the mesa having first tlirough-holes and second through-holes exposing the first conductivity type semiconductor layer through the second conductivity type semiconductor layer and the active layer;

   a first electrode disposed between the second conductivity type semiconductor layer and the support substrate, the first electrode comprising first contact portions electrically connected to the first conductivity type semiconductor layer through the first through-holes and second contact portions electrically connected to the first conductivity type semiconductor layer through the second

   44 through-holes;

   a second electrode disposed between the first electrode and the second conductivity type semiconductor layer and electrically connected to the second conductivity type semiconductor layer; and at least one upper electrode pad disposed adjacent to the first conductivity type semiconductor layer and connected to the second electrode, wherein each of the first through-holes is surrounded by the active layer and the second conductivity type semiconductor layer and is disposed within a région surrounded by edges of the mesa, each of the second through-holes is partially surrounded by the active layer and the second conductivity type semiconductor layer and is disposed along the edge of the mesa, and the upper insulation layer comprises a plurality of material layers.
2. [Claim 2]

   The light emitting diode according to claim 1, wherein:

   The first conductivity type semiconductor layer has a roughened surface; and the upper insulation layer comprises a first layer covering the roughened surface of the first conductivity type semiconductor layer, a second layer covering the first layer and having a higher refractive index than the first layer, and a third layer covering the second layer and having a lower refractive index than the second layer.
3. [Claim 3]

   The light emitting diode according to claim 2, wherein the first layer and the third layer comprise SiChand the second layer comprises AI2O3.
4. [Claim 4]

   The light emitting diode according to claim 3, wherein the first layer has a greater thickness than the second layer and the third layer.
5. [Claim 5]

   The light emitting diode according to claim 2, where in the first conductivity type semiconductor layer comprises an Al-containing nitride semiconductor layer.
6. [Claim 6]

   The light emitting diode according to claim 1, wherein:

   The first conductivity type semiconductor layer has a roughened surface; and the upper insulation layer comprises an AhOslayer covering the roughened surface of the first conductivity type semiconductor layer and a S1O2 layer covering the AI2O3 layer.
7. [Claim 7]

   The light emitting diode according to claim 1, where in the support substrate has a rectangular shape and the upper electrode pad extends along one edge of the support substrate to be longitudinally disposed between one edge of the mesa and one edge of the support substrate.
8. [Claim 8]

   The light emitting diode according to claim 7, where in some of the second through-holes are disposed between the upper electrode pad and the mesa.
9. [Claim 9]

   The light emitting diode according to claim 1, where in the support substrate has a rectangular shape and two upper electrode pads are disposed near opposite corners of the support substrate along one edge of the support substrate.
10. [Claim 10]

    The light emitting diode according to claim 9, where in a partial région of the mesa is disposed between the two upper electrode pads and some of the second through-holes are formed in the partial région of the mesa disposed between the two upper electrode pads.

    [Claim 11 ]

    The light emitting diode according to claim 10, wherein the second throughholes are arranged to be disposed adjacent four edges of the support substrate.

    [Claim 12]

    The light emitting diode according to claim 10, wherein the light emitting diode has a mirror symmetry structure.

    [Claim 13]

    The light emitting diode according to claim 1, further comprising:

    a first insulation layer insulating the first electrode from the first conductivity type semiconductor layer; and a second insulation layer interposed between the first electrode and the second electrode.

    [Claim 14]

    The light emitting diode according to claim 13, further comprising:

    a reflection layer disposed between the second insulation layer and the first

    48 electrode, the reflection layer comprising a distributed Bragg reflector.

    [Claim 15]

    The light emitting diode according to claim 13, further comprising:

    a bonding métal layer interposed between the first electrode and the support substrate; and a first electrode-protecting métal layer interposed between the bonding métal layer and the first electrode and covering the first electrode.

    [Claim 16]

    The light emitting diode according to claim 1, where in the second electrode comprises an ohmic reflection layer forming ohmic contact with the second conductivity type semiconductor layer and a protective métal layer protecting the ohmic reflection layer.

    [Claim 17]

    The light emitting diode according to claim 16, wherein the protective métal layer extends outside the first conductivity type semiconductor layer and the upper electrode pad is connected to the protective métal layer.

    [Claim 18]

    The light emitting diode according to claim 17, wherein the upper electrode pad is connected to the protective métal layer through the upper insulation layer and the first insulation layer.

    [Claim 19]

    The light emitting diode according to claim 16, further comprising:

    a second insulation layer interposed between the first electrode and the second electrode and covering a side surface of the protective métal layer.