OA17516A - Conditional signaling of picture order count timing information for video timing in video coding. - Google Patents

Conditional signaling of picture order count timing information for video timing in video coding. Download PDF

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Publication number
OA17516A
OA17516A OA1201500263 OA17516A OA 17516 A OA17516 A OA 17516A OA 1201500263 OA1201500263 OA 1201500263 OA 17516 A OA17516 A OA 17516A
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syntax structure
video
vps
coded
condition
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OA1201500263
Inventor
Ye-Kui Wang
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Qualcomm Incorporated
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Publication of OA17516A publication Critical patent/OA17516A/en

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Abstract

In an example, the disclosure provides for encoding pictures of a video sequence to generate a coded video sequence comprising the encoded pictures and signaling timing parameters for the coded video sequence by directly signaling a condition for signaling a number of clock ticks corresponding to a difference of picture order count (POC) values equal to 1 in at least one of a video parameter set (VPS) syntax structure referenced by the coded video sequence and a sequence parameter set (SPS) syntax structure referenced by the coded video sequence. Another example provides for receiving timing parameters for a coded video sequence that include a condition for signaling a number of clock ticks corresponding to a difference of POC values equal to 1 directly in at least one of a VPS syntax structure referenced by the coded video sequence and an SPS syntax structure referenced by the coded video sequence.

Description

[0002] This disclosure relates to video coding and video processing, and more particularly to techniques for signaling timing information in video information.
BACKGROUND 1θ [0003] Digital video capabilities can be incorporated into a wide range of devices, including digital télévisions, digital direct broadcast Systems, wireless broadcast Systems, personal digital assistants (PDAs), laptop or desktop computers, tablet computers, e-book readers, digital caméras, digital recording devices, digital media players, video gaming devices, video game consoles, cellular or satellite radio 15 téléphonés, so-called “smart phones,” video teleconferencing devices, video streaming devices, and the like. Digital video devices implement video compression techniques, such as those described in the standards defined by MPEG-2, MPEG-4, ITU-T H.263, ITU-T H.264/MPEG-4, Part 10, Advanced Video Coding (AVC), the High Efficiency
Video Coding (HEVC) standard, and extensions of such standards. The video devices 20 may transmit, receive, encode, décodé, and/or store digital video information more efficiently by implementing such video compression techniques.
[0004] Video compression techniques perform spatial (intra-picture) prédiction and/or temporal (inter-picture) prédiction to reduce or remove redundancy inhérent in video sequences. For block-based video coding, a video slice (i.e., a video frame or a portion 25 of a video frame) may be partitioned into video blocks, which may also be referred to as treeblocks, coding units (CUs) and/or coding nodes. Video blocks in an intra-coded (I) slice of a picture are encoded using spatial prédiction with respect to reference samples in neighboring blocks in the same picture. Video blocks in an inter-coded (P or B) slice of a picture may use spatial prédiction with respect to reference samples in neighboring 30 blocks in the same picture or temporal prédiction with respect to reference samples in
other reference pictures. Pictures may be referred to as frames, and reference pictures may be referred to a reference frames.
[0005] Spatial or temporal prédiction utilizes a prédictive block. Residual data represents pixel différences between the original block to be coded and the prédictive block. An inter-coded block is encoded according to a motion vector that points to a block of reference samples forming the prédictive block, and the residual data indicating the différence between the coded block and the prédictive block. An intra-coded block is encoded according to an intra-coding mode and the residual data. For further compression, the residual data may be transformed from the pixel domain to a transform domain, resulting in residual transform coefficients, which then may be quantized. The quantized transform coefficients, initially arranged in a two-dimensional array, may be scanned in order to produce a one-dimensional vector of transform coefficients, and entropy coding may be applied to achieve even more compression.
[0006] A given coded video sequence encoded to a bitstream includes an ordered sequence of coded pictures. In the H.264/AVC and HEVC standards, the decoding order of the coded pictures for a bitstream is équivalent to the ordered sequence. However, the standards also support an output order of decoded pictures that differs from the decoding order, and in such cases each of the coded pictures is associated with a picture order count (POC) value that spécifiés the output order for the picture in the video sequence.
[0007] Video timing information for a video sequence may be signaled in syntax éléments of one or more syntax structures (altematively referred to as “parameter set structures” or simply “parameter sets”). The syntax structures may include a sequence parameter set (SPS) that includes coding information that applied to ail slices of a coded video sequence. The SPS may itself include parameters referred to as video usability information (VUI), which include hypothetical reference décoder (HRD) information as well as information for enhancing the use of the corresponding video sequence for various purposes. The HRD information may itself be signaled using a HRD syntax structure includable within other syntax structures such as the VUI syntax structure. The syntax structures may also include a video parameter set (VPS) that describes characteristics of a corresponding video sequence, such as common syntax éléments shared by multiple layers or operation points as well as other operation point information that may be common to multiple sequence parameter sets, such as HRD information for various layers or sub-layers.
5 SUMMARY
[0008] In general, this disclosure describes techniques for video coding, and more particularly to techniques for signaling timing information, e.g., to specify picture output timing and/or to define a buffering model such as a hypothetical référencé décoder (HRD). In some examples, the techniques may include directly signaling, in
10 the video parameter set (VPS) syntax structure or in the video usability information (VUI) part of the sequence parameter set (SPS) syntax structure for a coded video sequence, one or more syntax éléments that define a condition for signaling a number of clock ticks corresponding to a différence of picture order count (POC) values equal to 1. [0009] In one example of the disclosure, a method for coding video data includes
15 encoding pictures of a video sequence to generate a coded video sequence comprising the encoded pictures and signaling timing parameters for the coded video sequence by directly signaling a condition for signaling a number of clock ticks corresponding to a différence of picture order count (POC) values equal to 1 in at least one of a video parameter set (VPS) syntax structure referenced by the coded video sequence and a
20 sequence parameter set (SPS) syntax structure referenced by the coded video sequence. [0010] In another example of the disclosure, a method for processing video data includes receiving a coded video sequence comprising encoded pictures of a video sequence and receiving timing parameters for the coded video sequence that include a condition for signaling a number of clock ticks corresponding to a différence of picture
25 order count (POC) values equal to 1 directly in at least one of a video parameter set (VPS) syntax structure referenced by the coded video sequence and a sequence parameter set (SPS) syntax structure referenced by the coded video sequence. [0011] In another example, the disclosure describes a device for coding video data, the device including a processor configured to encode pictures of a video sequence to
30 generate a coded video sequence comprising the encoded pictures and signal timing parameters for the coded video sequence by directly signaling a condition for signaling a number of clock ticks corresponding to a différence of picture order count (POC) values equal to 1 in at least one of a video parameter set (VPS) syntax structure referenced by the coded video sequence and a sequence parameter set (SPS) syntax
35 structure referenced by the coded video sequence.
[0012] In another example, the disclosure describes a device for processing video data, the device including a processor configured to receive a coded video sequence comprising encoded pictures of a video sequence and receive timing parameters for the coded video sequence that include a condition for signaling a number of clock ticks corresponding to a différence of picture order count (POC) values equal to 1 directly in at least one of a video parameter set (VPS) syntax structure referenced by the coded video sequence and a sequence parameter set (SPS) syntax structure referenced by the coded video sequence.
[0013] In another example, the disclosure describes a device for processing video data, the device including means for receiving a coded video sequence comprising encoded pictures of a video sequence and means for receiving timing parameters for the coded video sequence that include a condition for signaling a number of clock ticks corresponding to a différence of picture order count (POC) values equal to 1 directly in at least one of a video parameter set (VPS) syntax structure referenced by the coded video sequence and a sequence parameter set (SPS) syntax structure referenced by the coded video sequence.
[0014] In another example, the disclosure describes a computer-readable storage medium. The computer-readable storage medium having stored thereon instructions that upon execution cause one or more processors to receive a coded video sequence comprising encoded pictures of a video sequence and receive timing parameters for the coded video sequence that include a condition for signaling a number of clock ticks corresponding to a différence of picture order count (POC) values equal to 1 directly in at least one of a video parameter set (VPS) syntax structure referenced by the coded video sequence and a sequence parameter set (SPS) syntax structure referenced by the coded video sequence.
[0015] The details of one or more examples are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims.
BRIEF DESCRIPTION OF DRAWINGS [0016] FIG. 1 is a block diagram illustrating an example video encoding and decoding System that may utilize the techniques described in this disclosure.
[0017] FIG. 2 is a block diagram illustrating an example video encoder that may implement the techniques described in this disclosure.
[0018] FIG. 3 is a block diagram illustrating an example video décoder that may 5 implement the techniques described in this disclosure.
[0019] FIG. 4 is a block diagram illustrating timing information for an example coding structure for a reference picture set according to techniques described herein.
[0020] FIG. 5 is a flowchart illustrating an example method of operation according to techniques described in this disclosure.
1θ [0021] FIGS. 6A-6B are flowcharts illustrating example methods of operation according to techniques described in this disclosure.
[0022] FIG. 7 is a flowchart illustrating an example method of operation according to techniques described in this disclosure.
[0023] FIG. 8 is a flowchart illustrating an example method of operation according to 15 techniques described in this disclosure.
[0024] FIGS. 9A-9B are flowcharts illustrating example methods of operation according to techniques described in this disclosure.
[0025] FIG. 10 is a flowchart illustrating an example method of operation according to techniques described in this disclosure.
DETAILED DESCRIPTION [0026] This disclosure describes various techniques for video coding, and more particularly to techniques for signaling timing information, e.g., to specify picture output timing and/or to define a buffering or decoding model such as a hypothetical reference décoder (HRD). In general, the term “signaling” is used in this disclosure to refer to signaling that takes place within a coded bitstream. An encoder may generate syntax éléments to signal information in a bitstream as part of a video encoding process. A decoding device or other video processing device, may receive a coded bitstream, and interpret syntax éléments in the coded bitstream as part of a video decoding process or other video processing.
[0027] For example, to indicate the output timing for switching from a given picture to the next picture in a coded video sequence according to the output ordering, the timing information for the coded video sequence may in some cases signal a number of clock ticks that correspond to a différence of picture order count (POC) values equal to one. A
• différence of POC values equal to one may represent the différence between a POC value for a given picture and the POC value for the next picture according to the output ordering, e.g. the POC value for the 2nd picture and the POC value for the 3rd picture according to the output ordering. The video timing information may also include a condition that spécifiés whether the video timing information signais the number of clock ticks that correspond to a différence of picture order count values equal to one. In other words, only if the condition holds does the video timing information signal the number of clock ticks that correspond to a différence of picture order count values equal to one. In some cases, the condition does not hold and the video timing information does not signal the number of clock ticks that correspond to a différence of picture order count values equal to one. The number of clock ticks may dépend upon the time scale (corresponding, e.g., to an oscillator frequency - such as 27 MHz - that defines a time coordinate System for the signaled information) and the number of time units of a clock operating at the time scale that corresponds to one incrément of a clock tick counter, which is referred to as a “clock tick.” [0028] In some examples, the techniques of this disclosure may include directly 2θ signaling, in the VPS syntax structure or in the VUI part of the SPS syntax structure for a coded video sequence, ail syntax éléments that define the condition for signaling a number of clock ticks corresponding to a différence of POC values equal to 1. That is, in some cases, the condition may hâve one or more dependencies upon additional information (i.e., the syntax éléments) signaled in the VPS syntax structure or in the 25 VUI part of the SPS syntax structure. These syntax éléments may include a timing information présent flag, as described below.
[0029] Video coding standards include ITU-T H.261, ISO/IEC MPEG-1 Visual, ITU-T H.262 or ISO/IEC MPEG-2 Visual, ITU-T H.263, ISO/IEC MPEG-4 Visual and ITU-T H.264 (also known as ISO/IEC MPEG-4 AVC), including its Scalable Video Coding 30 (SVC) and Multiview Video Coding (MVC) extensions.
[0030] In addition, there is a new video coding standard, namely High Effïciency Video Coding (HEVC), being developed by the Joint Collaboration Team on Video Coding (JCT-VC) of ITU-T Video Coding Experts Group (VCEG) and ISO/IEC Motion Picture Experts Group (MPEG). The latest Working Drafit (WD) of HEVC, and referred to as 35 HEVC WD9 or simply WD9 hereinafter, is Bross et al., “Proposed éditorial improvements for High Effïciency Video Coding (HEVC) text spécification draft 9 (SoDIS),” Joint Collaborative Team on Video Coding (JCT-VC) of ITU-T SG 16 WP 3
and ISO/IEC JTC l/SC 29/WG 11, 12th Meeting: Geneva, CH, 14-23 Jan. 2013, available from http://phenix.int5 evry.fr/jct/doc_end_user/documents/12_Geneva/wgll/JCTVC-L0030-vl.zip, as of
January 7,2013.
[0031] A recent draft of the HEVC standard, referred to as “HEVC Working Draft 10” or “WD 10,” is described in document JCTVC-L1003v34, Bross et al., “High efficiency video coding (HEVC) text spécification draft 10 (for FDIS & Last Call),” Joint 10 Collaborative Team on Video Coding (JCT-VC) of ITU-T SG16 WP3 and ISO/IEC
JTC1/SC29/WG11, 12th Meeting: Geneva, CH, 14-23 January, 2013, which is downloadable from: http://phenix.intevry .fr/j ct/doc_end_user/documents/12_Geneva/wg 11/JCTV C-L1003-v34.zip.
[0032] Another draft of the HEVC standard, referred to herein as “WD10 révisions,” is described in Bross et al., “Editors’ proposed corrections to HEVC version 1,” Joint
Collaborative Team on Video Coding (JCT-VC) of ITU-T SG16 WP3 and ISO/IEC JTC1/SC29/WG11, 13ύ Meeting, Incheon, KR, April 2013, which as of June 7, 2013, is available from:
http ://phenix .int-evry. fr/j et/doc_end_user/documents/13_Incheon/wg 11 /J CT V C20 M0432-v3.zip [0033] HEVC standardization efforts are based on a model of a video coding device referred to as the HEVC Test Model (HM). The HM présumés improvements in the capabilities of current video coding devices with respect to video coding devices available during the development of other previous video coding standards, e.g., ITU-T H.264/AVC. For example, whereas H.264 provides nine intra-prediction encoding modes, HEVC provides as many as thirty-five intra-prediction encoding modes. The entire contents of HEVC WD9 and HEVC WD 10 are incorporated herein by reference.
[0034] Video coding standards typically include a spécification of a video buffering model. In AVC and HEVC, the buffering model is referred to as the hypothetical 3θ reference décoder (HRD), which includes a buffering model of both the coded picture buffer (CPB) and the decoded picture buffer (DPB). As defmed in HEVC WD9, an HRD is a hypothetical décoder model that spécifiés constrains on the variability of Network Abstraction Layer (NAL) unit streams or conforming byte streams that an encoding process may produce.
[0035] The CPB and DPB behaviors are mathematically specifîed. The HRD directly imposes constraints on different timing, buffer sizes and bit rates, and indirectly
imposes constraints on bitstream characteristics and statistics. A complété set of HRD parameters include five basic parameters: initial CPB removal delay, CPB size, bit rate, initial DPB output delay, and DPB size.
[0036] In AVC and HEVC, bitstream conformance and décoder conformance are specified as parts of the HRD spécification. Although “Hypothetical Reference Décoder” includes the term “décoder,” HRD is typically needed at the encoder side to guarantee bitstream conformance and is typically not needed at the décoder side. Two types of bitstream or HRD conformance, namely Type I and Type II, are specified. 0 Also, two types of décoder conformance, output timing décoder conformance and output order décoder conformance are specified.
[0037] In HEVC WD9, HRD operations require parameters signaled in the hrd_parameters( ) syntax structures, buffering period supplémentai enhancement information (SEI) messages, picture timing SEI messages and sometimes also in 15 decoding unit information SEI messages. The hrd_parameters( ) syntax structures may be signaled in the video parameter set (VPS), the sequence parameter set (SPS), or any combination thereof.
[0038] In HEVC WD9, the hrd_parameters( ) syntax structure includes syntax éléments for signaling of video timing information, including time scale and the number of units ° in a clock tick. The video usability information (VUI) part of the SPS includes a flag indicating whether the picture order count (POC) value for each picture in the coded video sequence that is not the first picture in the coded video sequence, in decoding order, is proportional to the output time of the picture relative to the output time of the first picture in the coded video sequence; if yes, then the number of clock ticks 5 corresponding to a différence of picture order count values equal to 1.
[0039] The related syntax and semantics in HEVC WD9 are as follows. Table 1 shows an example video parameter set raw byte sequence payload (RBSP) syntax structure according to WD9.
video parameter set rbsp( ) { Descriptor
...
vpsnumhrdparameters ue(v)
for( i = 0; i < vps num hrd parameters; i++ ) {
hrd op set idx[ i ] ue(v)
if( i > 0 )
cprms present flag[ i ] u(l)
hrd_parameters( cprms_present_flag[ i ], vps max sub layers minus 1 )
}
...
}
Table 1: Example video parameter set RBSP syntax structure [0040] In Table 1 above, the syntax element vps_num_hrd_parameters spécifiés the number of hrd_parameters( ) syntax structures présent in the video parameter set Raw Byte Sequence Payload (RBSP). In bitstreams conforming to this version of this Spécification, the value of vps_num_hrd_parameters shall be less than or equal to 1.
1 θ Although the value of vps_num_hrd_parameters is required to be less than or equal to 1 in HEVC WD9, decoders shall allow other values of vps_num_hrd_parameters in the range of 0 to 1024, inclusive to appear in the syntax.
[0041] The syntax element hrd_op_set_idx[ i ] spécifiés the index, in the list of operation point sets specifïed by the video parameter set, of the operation point set to 15 which the i-th hrd_parameters( ) syntax structure in the video parameter set (VPS) applies. In bitstreams conforming to this version of this Spécification, the value of hrd_op_set_idx[ i ] shall be equal to 0. Although the value of hrd_op_set_idx[ i ] is required to be less than or equal to 1 in HEVC WD9, decoders shall allow other values of hrd_op_set_idx[ i ] in the range of 0 to 1023 to appear in the syntax.
[0042] The syntax element cprms_present_flag[ i ] equal to 1 spécifiés that the HRD parameters that are common for ail sub-layers are présent in the i-th hrd_parameters( ) syntax structure in the video parameter set. cprms_present_flag[ i ] equal to 0 spécifiés that the HRD parameters that are common for ail sub-layers are not présent in the i-th hrd_parameters( ) syntax structure in the video parameter set and are derived to be the 25 same as the ( i - 1 )-th hrd_parameters( ) syntax structure in the video parameter set.
cprms_present_flag[ 0 ] is inferred to be equal to 1.
[0043] Table 2 below shows a VUI parameters syntax structure according to WD9.
vui parameters( ) { Descriptor
...
hrd parameters present flag u(l)
if( hrd parameters present flag )
hrd parameters( 1, sps max sub layers minusl )
poc proportional to timing flag u(l)
if(poc_proportional_to_timing_flag && timing info présent flag)
num ticksjpoc diff one minusl ue(v)
...
}
Table 2: VUIparameters syntax structure [0044] In Table 2 above, the syntax element hrd_parameters_present_flag equal to 1 spécifiés that the syntax structure hrd_parameters( ) is présent in the vui_parameters( ) syntax structure. The hrd_parameters_present_flag equal to 0 spécifiés that the syntax structure hrd_parameters( ) is not présent in the vui_parameters( ) syntax structure.
[0045] The syntax element poc_proportional_to_timing flag equal to 1 indicates that 1Π the picture order count value for each picture in the coded video sequence that is not the first picture in the coded video sequence, in decoding order, is proportional to the output time of the picture relative to the output time of the first picture in the coded video sequence. The poc_proportional_to_timing_flag equal to 0 indicates that the picture order count value for each picture in the coded video sequence that is not the first 15 picture in the coded video sequence, in decoding order, may or may not be proportional to the output time of the picture relative to the output time of the first picture in the coded video sequence.
[0046] The syntax element num_ticks_poc_diff_one_minusl plus 1 spécifiés the number of clock ticks corresponding to a différence of picture order count values equal 20 toi.
[0047] Table 3 below shows an example HRD parameters syntax stmcture according to WD9.
hrd_parameters( commonlnfPresentFlag, maxNumSubLayersMinusl ) { Descriptor
if( commonlnfPresentFlag ) {
timing info present flag u(l)
if( timing info present flag ) {
num units in tick u(32)
time scale u(32)
}
···
}
Table 3: Example HRD parameters syntax structure [0048] In Table 3 above, the syntax element timing_info_present flag equal to 1 spécifiés that num_units_in_tick and timescale are présent in the hrd_parameters( ) syntax structure. If the tirning_info_present_flag is equal to 0, the num_units_in_tick and time_scale are not présent in the hrd_parameters( ) syntax structure. If not présent, the value of timing_info_present_flag is inferred to be 0.
[0049] The syntax element num_units_in_tick is the number of time units of a clock operating at the frequency time scale Hz that corresponds to one incrément (called a clock tick) of a clock tick counter. The value for syntax element num_units_in_tick shall be greater than 0. A clock tick is the minimum interval of time that can be represented in the coded data when sub_pic_cpb_params_present_flag is equal to 0. For example, when the picture rate of a video signal is 25 Hz, time scale may be equal to 27,000,000 and num units in tick may be equal to 1,080,000.
[0050] The syntax element time_scale is the number of time units that pass in one second. For example, a time coordinate System that measures time using a 27 MHz clock has a time scale of 27,000,000. The value for syntax element time scale shall be greater than 0.
[0051] The timing signaling as specified in HEVC WD9 and as described above may exhibit a number of problems. First, the condition for signaling of the syntax element num_ticks_poc_diff_one_minusl is “if( poc_proportional_to_timing_flag && timing_info_present_flag )”. This condition includes dependencies upon two signaled syntax éléments: poc_proportional_to_timing_flag and timing_info_present_flag. However, it is not clear from the HEVC WD9 spécification whether the timing_info_present_flag for the condition references the syntax element timing_info_present_flag of an hrd_parameters( ) syntax structure (if présent) in the
VUI part of the SPS or référencés référencés the syntax element 5 timing_info_present_flag of an hrd_parameters( ) syntax structure in the VPS.
[0052] In addition, multiple layers or multiple possible bitstream subsets of a scalable video bitstream may share the common values of time scale and the number of units in a clock tick, which are specified in HEVC WD9 in the syntax éléments time_scale and num_units_in_tick of an hrd_parameters( ) syntax structure, which may be repeatedly 10 signaled in the VUI part of the SPS and in the VPS, for instance. Such réplication, if présent in the bitstream, may resuit in bit wastage.
[0053] Further, picture order count (POC) values are typically proportionaî to output times for ail layers of a scalable video bitstream if the POC values are proportionaî to output times for any of the layers of a scalable video bitstream. However, The HEVC 15 WD9 spécification does not provide for signaling, in the scalable video bitstream, an indication that POC values are proportionaî to output times for ail layers or ail possible bitstream subsets of the scalable video bitstream. Reference to a “layer” of a scalable video bitstream may refer to a scalable layer, a texture view, and/or a depth view, for instance. In addition, although HEVC WD9 spécifiés that the flag 20 poc_proportional_to_timing flag is always signaled in the VUI syntax is always signaled in the VUI syntax structure of the SPS, the flag pocjproportional to timing flag has no utility if the syntax éléments time scale and num_units_in_tick are not also signaled in the bitstream.
[0054] The techniques of this disclosure may solve one or more of the above problems, 25 as well as provide other improvements, to enable efficient signaling of parameters for
HRD operations. Various examples of the techniques are described herein with reference to HEVC WD9 and potential improvements thereto. The solutions apply to any video coding standards, including AVC and HEVC, for example, that include a spécification for a video buffering model, though for purposes of illustration the 30 description is spécifie to the HRD parameters signaling defined in HEVC WD9 and modified in accordance with the techniques of this disclosure.
[0055] FIG. 1 is a block diagram illustrating an example video encoding and decoding System 10 that may utilize the techniques described in this disclosure. As shown in FIG. 1, System 10 includes a source device 12 that generates encoded video data to be 35 decoded at a later time by a destination device 14. Source device 12 and destination device 14 may comprise any of a wide range of devices, including desktop computers, notebook (i.e., laptop) computers, tablet computers, set-top boxes, téléphoné handsets
such as so-called “smart” phones, so-called “smart” pads, télévisions, caméras, display devices, digital media players, video gaming consoles, video streaming device, or the 5 like. In some cases, source device 12 and destination device 14 may be equipped for wireless communication.
[0056] Destination device 14 may receive the encoded video data to be decoded via a link 16. Link 16 may comprise any type of medium or device capable of moving the encoded video data from source device 12 to destination device 14. In one example, 10 link 16 may comprise a communication medium to enable source device 12 to transmit encoded video data directly to destination device 14 in real-time. The encoded video data may be modulated according to a communication standard, such as a wireless communication protocol, and transmitted to destination device 14. The communication medium may comprise any wireless or wired communication medium, such as a radio 15 frequency (RF) spectrum or one or more physical transmission lines. The communication medium may form part of a packet-based network, such as a local area network, a wide-area network, or a global network such as the Internet. The communication medium may include routers, switches, base stations, or any other equipment that may be useful to facilitate communication from source device 12 to 20 destination device 14.
[0057] Altematively, encoded data may be output from output interface 22 to a storage device 34. Similarly, encoded data may be accessed from storage device 34 by input interface. Storage device 34 may include any of a variety of distributed or locally accessed data storage media such as a hard drive, Blu-ray dises, DVDs, CD-ROMs, 25 flash memory, volatile or non-volatile memory, or any other suitable digital storage media for storing encoded video data. In a further example, storage device 34 may correspond to a file server or another intermediate storage device that may hold the encoded video generated by source device 12. Destination device 14 may access stored video data from storage device 34 via streaming or download. The file server may be 30 any type of server capable of storing encoded video data and transmitting that encoded video data to the destination device 14. Example file servers include a web server (e.g., for a website), an FTP server, network attached storage (NAS) devices, or a local disk drive. Destination device 14 may access the encoded video data through any standard data connection, including an Internet connection. This may include a wireless channel 35 (e.g., a Wi-Fi connection), a wired connection (e.g., DSL, cable modem, etc.), or a combination of both that is suitable for accessing encoded video data stored on a file
* server. The transmission of encoded video data from storage device 34 may be a streaming transmission, a download transmission, or a combination of both.
[0058] The techniques of this disclosure are not necessarily limited to wireless applications or settings. The techniques may be applied to video coding in support of any of a variety of multimedia applications, such as over-the-air télévision broadcasts, cable télévision transmissions, satellite télévision transmissions, streaming video transmissions, e.g., via the Internet, encoding of digital video for storage on a data storage medium, decoding of digital video stored on a data storage medium, or other applications. In some examples, System 10 may be confîgured to support one-way or two-way video transmission to support applications such as video streaming, video playback, video broadcasting, and/or video telephony.
[0059] In the example of FIG. 1, source device 12 includes a video source 18, video encoder 20 and an output interface 22. In some cases, output interface 22 may include a 15 modulator/demodulator (modem) and/or a transmitter. In source device 12, video source 18 may include a source such as a video capture device, e.g., a video caméra, a video archive containing previously captured video, a video feed interface to receive video from a video content provider, and/or a computer graphies System for generating computer graphies data as the source video, or a combination of such sources. As one 20 example, if video source 18 is a video caméra, source device 12 and destination device may form so-called caméra phones or video phones. However, the techniques described in this disclosure may be applicable to video coding in general, and may be applied to wireless and/or wired applications.
[0060] The captured, pre-captured, or computer-generated video may be encoded by video encoder 20. The encoded video data may be transmitted directly to destination device 14 via output interface 22 of source device 12. The encoded video data may also (or altematively) be stored onto storage device 34 for later access by destination device 14 or other devices, for decoding and/or playback.
[0061] Destination device 14 includes an input interface 28, a video décoder 30, and a display device 32. In some cases, input interface 28 may include a receiver and/or a modem. Input interface 28 of destination device 14 receives the encoded video data over link 16. The encoded video data communicated over link 16, or provided on storage device 34, may include a variety of syntax éléments generated by video encoder 20 for use by a video décoder, such as video décoder 30, in decoding the video data.
Such syntax éléments may be included with the encoded video data transmitted on a communication medium, stored on a storage medium, or stored a file server.
[0062] Display device 32 may be integrated with, or extemal to, destination device 14. In some examples, destination device 14 may include an integrated display device and also be configured to interface with an extemal display device. In other examples, destination device 14 may be a display device. In general, display device 32 displays the decoded video data to a user, and may comprise any of a variety of display devices such as a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, or another type of display device.
[0063] Video encoder 20 and video décoder 30 may operate according to a video compression standard, such as the High Efficiency Video Coding (HEVC) standard presently under development, and may conform to the HEVC Test Model (HM). Altematively, video encoder 20 and video décoder 30 may operate according to other proprietary or industry standards, such as the ITU-T H.264 standard, altematively referred to as MPEG-4, Part 10, Advanced Video Coding (AVC), or extensions of such standards. The techniques of this disclosure, however, are not limited to any particular coding standard. Other examples of video compression standards include MPEG-2 and ITU-T H.263.
[0064] Although not shown in FIG. 1, in some aspects, video encoder 20 and video décoder 30 may each be integrated with an audio encoder and décoder, and may include appropriate MUX-DEMUX units, or other hardware and software, to handle encoding of both audio and video in a common data stream or separate data streams. If applicable, in some examples, MUX-DEMUX units may conform to the ITU H.223 multiplexer protocol, or other protocols such as the user datagram protocol (UDP).
[0065] Video encoder 20 and video décoder 30 each may be implemented as any of a variety of suitable encoder circuitry, such as one or more microprocessors, digital signal processors (DSPs), application spécifie integrated circuits (ASICs), fîeld programmable gâte arrays (FPGAs), discrète logic, software, hardware, firmware or any combinations thereof. When the techniques are implemented partially in software, a device may store instructions for the software in a suitable, non-transitory computer-readable medium and execute the instructions in hardware using one or more processors to perform the techniques of this disclosure. Each of video encoder 20 and video décoder 30 may be included in one or more encoders or decoders, either of which may be integrated as part of a combined encoder/decoder (CODEC) in a respective device.
[0066] The JCT-VC is working on development of the HEVC standard. The HEVC standardization efforts are based on an evolving model of a video coding device referred to as the HEVC Test Model (HM). The HM présumés several additional capabilities of video coding devices relative to existing devices according to, e.g., ITU-T H.264/AVC. For example, whereas H.264 provides nine intra-prediction encoding modes, the HM may provide as many as thirty-three intra-prediction encoding modes.
[0067] In general, the working model of the HM describes that a video frame or picture may be divided into a sequence of treeblocks or largest coding units (LCU) that include both luma and chroma samples. A treeblock has a similar purpose as a macroblock of the H.264 standard. A slice includes a number of consecutive treeblocks in coding order. A video frame or picture may be partitioned into one or more slices. Each treeblock may be split into coding units (CUs) according to a quadtree. For example, a treeblock, as a root node of the quadtree, may be split into four child nodes, and each child node may in tum be a parent node and be split into another four child nodes. A final, unsplit child node, as a leaf node of the quadtree, comprises a coding node, i.e., a coded video block. Syntax data associated with a coded bitstream may define a maximum number of times a treeblock may be split, and may also define a minimum size of the coding nodes.
[0068] A CU includes a coding node and prédiction units (PUs) and transform units (TUs) associated with the coding node. A size of the CU generally corresponds to a size of the coding node and must typically be square in shape. The size of the CU may range from 8x8 pixels up to the size of the treeblock with a maximum of 64x64 pixels or greater. Each CU may contain one or more PUs and one or more TUs. Syntax data associated with a CU may describe, for example, partitioning of the CU into one or more PUs. Partitioning modes may differ between whether the CU is skip or direct mode encoded, intra-prediction mode encoded, or inter-prediction mode encoded. PUs may be partitioned to be non-square in shape. Syntax data associated with a CU may also describe, for example, partitioning of the CU into one or more TUs according to a quadtree. A TU can be square or non-square in shape.
[0069] The HEVC standard allows for transformations according to TUs, which may be different for different CUs. The TUs are typically sized based on the size of PUs within a given CU defined for a partitioned LCU, although this may not always be the case. The TUs are typically the same size or smaller than the PUs. In some examples, residual samples corresponding to a CU may be subdivided into smaller units using a
quadtree structure known as residual quad tree (RQT). The leaf nodes of the RQT may be referred to as transform units (TUs). Pixel différence values associated with the TUs may be transformed to produce transform coefficients, which may be quantized.
[0070] In general, a PU includes data related to the prédiction process. For example, when the PU is intra-mode encoded, the PU may include data describing an intraprediction mode for the PU. As another example, when the PU is inter-mode encoded, the PU may include data defining a motion vector for the PU. The data defining the motion vector for a PU may describe, for example, a horizontal component of the motion vector, a vertical component of the motion vector, a resolution for the motion vector (e.g., one-quarter pixel précision or one-eighth pixel précision), a reference picture to which the motion vector points, and/or a reference picture list (e.g., List 0, List 1, or List C) for the motion vector.
[0071] In general, a TU is used for the transform and quantization processes. A given CU having one or more PUs may also include one or more transform units (TUs). Following prédiction, video encoder 20 may calculate residual values from the video block identified by the coding node in accordance with the PU. The coding node is then updated to reference the residual values rather than the original video block. The residual values comprise pixel différence values that may be transformed into transform coefficients, quantized, and scanned using the transforme and other transform information specified in the TUs to produce serialized transform coefficients for entropy coding. The coding node may once again be updated to refer to these serialized transform coefficients. This disclosure typically uses the term “video block” to refer to a coding node of a CU. In some spécifie cases, this disclosure may also use the term “video block” to refer to a treeblock, i.e., LCU, or a CU, which includes a coding node and PUs and TUs.
[0072] A video sequence typically includes a sériés of video trames or pictures. A group of pictures (GOP) generally comprises a sériés of one or more of the video pictures. A GOP may include syntax data in a header of the GOP, a header of one or more of the pictures, or elsewhere, that describes a number of pictures included in the GOP. Each slice of a picture may include slice syntax data that describes an encoding mode for the respective slice. Video encoder 20 typically opérâtes on video blocks within individual video slices in order to encode the video data. A video block may correspond to a coding node within a CU. The video blocks may hâve fixed or varying sizes, and may differ in size according to a specified coding standard.
[0073] As an example, the HM supports prédiction in vanous PU sizes. Assuming that the size of a particular CU is 2Nx2N, the HM supports intra-prediction in PU sizes of 2Nx2N or NxN, and inter-prediction in symmetric PU sizes of 2Nx2N, 2NxN, Nx2N, or NxN. The HM also supports asymmetric partitioning for inter-prediction in PU sizes of 2NxnU, 2NxnD, nLx2N, and nRx2N. In asymmetric partitioning, one direction of a CU is not partitioned, while the other direction is partitioned into 25% and 75%. The portion of the CU corresponding to the 25% partition is indicated by an “n” followed by an indication of “Up”, “Down,” “Left,” or “Right.” Thus, for example, “2NxnU” refers to a 2Nx2N CU that is partitioned horizontally with a 2NxO.5N PU on top and a 2Nxl.5N PU on bottom.
[0074] In this disclosure, “NxN” and ‘TM by N” may be used interchangeably to refer to the pixel dimensions of a video block in terms of vertical and horizontal dimensions,
e.g., 16x16 pixels or 16 by 16 pixels. In general, a 16x16 block will hâve 16 pixels in a vertical direction (y = 16) and 16 pixels in a horizontal direction (x = 16). Likewise, an NxN block generally has N pixels in a vertical direction and N pixels in a horizontal direction, where N represents a nonnegative integer value. The pixels in a block may be arranged in rows and columns. Moreover, blocks need not necessarily hâve the same number of pixels in the horizontal direction as in the vertical direction. For example, blocks may comprise NxM pixels, where M is not necessarily equal to N.
[0075] Following intra-predictive or inter-predictive coding using the PUs of a CU, video encoder 20 may calculate residual data to which the transforms specified by TUs of the CU are applied. The residual data may correspond to pixel différences between pixels of the unencoded picture and prédiction values corresponding to the CUs. Video encoder 20 may form the residual data for the CU, and then transform the residual data to produce transform coefficients.
[0076] Following any transforms to produce transform coefficients, video encoder 20 may perform quantization of the transform coefficients. Quantization generally refers to a process in which transform coefficients are quantized to possibly reduce the amount of data used to represent the coefficients, providing further compression. The quantization process may reduce the bit depth associated with some or ail of the coefficients. For example, an «-bit value may be rounded down to an m-bit value during quantization, where n is greater than m.
[0077] In some examples, video encoder 20 may utilize a predefined scan order to scan the quantized transform coefficients to produce a serialized vector that can be entropy
encoded. In other examples, video encoder 20 may perform an adaptive scan. After scanning the quantized transform coefficients to form a one-dimensional vector, video encoder 20 may entropy encode the one-dimensional vector, e.g., according to context adaptive variable length coding (CAVLC), context adaptive binary arithmetic coding (CABAC), syntax-based context-adaptive binary arithmetic coding (SBAC), Probability Interval Partitioning Entropy (PIPE) coding or another entropy encoding methodology. Video encoder 20 may also entropy encode syntax éléments associated with the encoded video data for use by video décoder 30 in decoding the video data.
[0078] To perform CABAC, video encoder 20 may assign a context within a context model to a symbol to be transmitted. The context may relate to, for example, whether neighboring values of the symbol are non-zero or not. To perform CAVLC, video encoder 20 may select a variable length code for a symbol to be transmitted. Codewords in VLC may be constructed such that relatively shorter codes correspond to more probable symbols, while longer codes correspond to less probable symbols. In this way, the use of VLC may achieve a bit savings over, for example, using equallength codewords for each symbol to be transmitted. The probability détermination may be based on a context assigned to the symbol.
[0079] Source device 12 may generate an encoded bitstream to include syntax éléments that conform to a syntax structure in accordance with techniques described in this disclosure. In some examples, video encoder 20 may generate the encoded bitstream to directly signal, in the video parameter set (VPS) syntax structure or in the video usability information (VUI) part of the sequence parameter set (SPS) syntax structure for a coded video sequence, ail variables that define the condition for signaling a number of clock ticks corresponding to a différence of picture order count (POC) values equal to 1. In other words, rather than signaling the syntax éléments for the condition for signaling a number of clock ticks corresponding to a différence of picture order count (POC) values equal to 1 in another syntax structure (such as the HRD parameters syntax structure) that is incorporated into a VPS syntax structure or VUI part of the SPS syntax structure, the video encoder 20 generates the encoded bitstream to signal the syntax éléments that define the condition in the VPS and/or VUI syntax structure without reference to another syntax structure potentially incorporated within either/both of the VPS and VUI syntax structure. The syntax éléments may include the timing_info_present flag syntax element that is specified in HEVC WD9 as a syntax element of the HRD parameters syntax structure. As a resuit, the techniques may
reduce and potentially eliminate ambiguity within the HEVC WD9 spécification by clearly specifying in the syntax the source of syntax éléments that define the condition. [0080] The video encoder 20 may test the encoded bitstream for conformance to requirements specified as one or more bitstream conformance tests defined in a video coding spécification, such as HEVC WD9 or a successor spécification such as HEVC WD 10. The video encoder 20 may include or otherwise use a hypothetical reference décoder to test the encoded bitstream for conformance. According to techniques described herein, the video encoder 20 may test the encoded bitstream for conformance by decoding the encoded bitstream to détermine, from the VPS syntax structure or in the VUI part of the SPS syntax structure for a coded video sequence, the syntax éléments that define the condition for signaling the number of clock ticks corresponding to a différence of POC values equal to 1. If the condition holds according to the syntax element values, video encoder 20 may détermine the number of clock ticks corresponding to a différence of POC values equal to 1 and use the determined number of clock ticks as input for, e.g., determining CPB underflow or overflow during decoding of encoded pictures included in the encoded bitstream.
[0081] In some instances, at the destination device 14, a video décoder 30 under test (or VUT) may in some cases receive a représentation of the encoded bitstream generated by video encoder 20 to directly signal, in the VPS syntax structure or in the VUI part of the SPS syntax structure for a coded video sequence, ail syntax éléments that define the condition for signaling a number of clock ticks corresponding to a différence of picture order count (POC) values equal to 1. Video décoder 30 may décodé the encoded bitstream to détermine, from the VPS syntax structure or in the VUI part of the SPS syntax structure for a coded video sequence, the syntax éléments that define the condition for signaling the number of clock ticks corresponding to a différence of POC values equal to 1. If the condition holds according to the syntax element values, video décoder 30 may détermine the number of clock ticks corresponding to a différence of POC values equal to 1 and use the determined number of clock ticks as input for, e.g., determining CPB underflow or overflow during decoding of encoded pictures included in the encoded bitstream.
[0082] In some examples, the video encoder 20 may generate the encoded bitstream to signal the time scale and the number of units in a clock tick at most once in each of the VPS and VUI syntax structures for a given coded video sequence. That is, in a given VPS syntax structure for the encoded bitstream, video encoder 20 may signal the time
• scale and number of units in a clock tick syntax éléments at most once. Likewise, in a given VUI syntax structure (e.g., the VUI part of an SPS syntax structure) for the encoded bitstream, video encoder 20 may signal the time scale and number of units in a clock tick syntax éléments at most once. As a resuit, the video encoder 20 operating according to techniques described herein may reduce a number of instances of the time scale syntax element (time scale per WD9) and the number of units in a clock tick (num_units_in_tick per WD9) syntax element in the encoded bitstream. In addition, the video encoder 20 may in some instances generate the encoded bitstream to directly signal the time scale and the number of units in a clock tick in each of the VPS and VUI syntax structures for a given coded video sequence, rather than in an HRD parameters syntax structure incorporated within a VPS and/or VUI syntax structure.
[0083] According to techniques described herein, the video encoder 20 may test an encoded bitstream, generated by video encoder 20 to signal the time scale and the number of units in a clock tick at most once in each of the VPS and VUI syntax structures for a given coded video sequence, for conformance by decoding the encoded bitstream to détermine the time scale and the number of units in a clock tick from a VPS syntax structure of the encoded bitstream that encodes the time scale and the number of units in a clock tick syntax éléments at most once in the VPS syntax structure. In some instances, the video encoder 20 may test the encoded bitstream for conformance by decoding the encoded bitstream to détermine the time scale and the number of units in a clock tick from a VUI syntax structure of the encoded bitstream that encodes the time scale and the number of units in a clock tick syntax éléments at most once in the VUI syntax structure. The time scale and number of units in a clock tick may be signaled other than in an HRD parameters syntax structure incorporated within the VPS and/or
VUI syntax structure. Video encoder 20 may use the determined time scale and the determined number of units in a clock tick as input for, e.g., determining CPB underflow or overflow during decoding of encoded pictures included in the encoded bitstream.
[0084] In some instances, at the destination device 14, a video décoder 30 under test may in some cases receive a représentation of the encoded bitstream generated by video encoder 20 to signal the time scale and the number of units in a clock tick at most once in each of the VPS and VUI syntax structures for a given coded video sequence. The video décoder 30 may décodé the encoded bitstream to détermine the time scale and the number of units in a clock tick from a VPS syntax structure of the encoded bitstream
that encodes the time scale and the number of units in a clock tick syntax éléments at most once in the VPS syntax structure. In some instances, the video décoder 30 may test the encoded bitstream for conformance by decoding the encoded bitstream to détermine the time scale and the number of units in a clock tick from a VUI syntax structure of the encoded bitstream that encodes the time scale and the number of units in a clock tick syntax éléments at most once in the VUI syntax structure. The time scale and number of units in a clock tick may be signaled other than in an HRD parameters syntax structure incorporated within the VPS and/or VUI syntax structure. Video décoder 30 may use the determined time scale and the determined number of units in a clock tick as input for, e.g., determining CPB underflow or overflow during decoding of encoded pictures included in the encoded bitstream.
15 [0085] In some examples, the video encoder 20 may generate the encoded bitstream to signal, in a VPS syntax structure for one or more coded video sequences, a flag indicating whether the POC value for each picture in a coded video sequence that is not the first picture in the coded video sequence, in decoding order, is proportional to the output time of the picture relative to the output time of the first picture in the coded 2θ video sequence. This indication flag may altematively be referred to as the POC proportional to timing indication flag. As a resuit, the video encoder 20 may reduce a number of instances of the indication in the timing information signaled for multiple layers of a coded video sequence and/or for a scalable video bitstream having multiple layers. In some instances, the video encoder 20 may include this flag in the VPS syntax 25 structure only if the time scale and number of units in a clock tick syntax éléments are also included. The video encoder 20 may in this way avoid signaling this particular timing information (i.e., whether the POC value for each picture in a coded video sequence that is not the first picture in the coded video sequence, in decoding order, is proportional to the output time of the picture relative to the output time of the first 30 picture in the coded video sequence) if the clock tick information needed for using the
POC proportional to timing indication is not also présent.
[0086] According to techniques described herein, the video encoder 20 may test for conformance an encoded bitstream, generated by video encoder 20 to signal, in a VPS syntax structure for one or more coded video sequences, the POC proportional to timing 35 indication flag. The video encoder 20 may test the encoded bitstream for conformance by decoding the encoded bitstream to détermine a value for the flag. The video encoder 20 may additionally, or altematively, test an encoded bitstream, generated by video
encoder 20 to signal the flag in the VPS syntax structure only if the time scale and number of units in a clock tick syntax éléments are also included. The video encoder 20 may use the determined value of the POC proportional to timing indication flag and the time scale and number of units in a clock tick syntax éléments as input for, e.g., determining CPB underflow or overflow during decoding of encoded pictures included in the encoded bitstream.
[0087] In some instances, at the destination device 14, a video décoder 30 under test 10 may in some cases receive a représentation of the encoded bitstream generated by video encoder 20 to signal, in a VPS syntax structure for one or more coded video sequences, a POC proportional to timing indication flag. The video décoder 30 may test the encoded bitstream for conformance by decoding the encoded bitstream to détermine a value for the flag. The video décoder 30 may additionally, or altematively, test an 15 encoded bitstream, generated by video décoder 30 to signal the flag in the VPS syntax structure only if the time scale and number of units in a clock tick syntax éléments are also included. The video décoder 30 may use the determined value of the POC proportional to timing indication flag and the time scale and number of units in a clock tick syntax éléments as input for, e.g., determining CPB underflow or overflow during 20 decoding of encoded pictures included in the encoded bitstream.
[0088] FIG. 2 is a block diagram illustrating an example video encoder 20 that may implement the techniques described in this disclosure. Video encoder 20 may perform intra- and inter-coding of video blocks within video slices. Intra-coding relies on spatial prédiction to reduce or remove spatial redundancy in video within a given video frame 25 or picture. Inter-coding relies on temporal prédiction to reduce or remove temporal redundancy in video within adjacent frames or pictures of a video sequence. Intra-mode (I mode) may refer to any of several spatial based compression modes. Inter-modes, such as uni-directional prédiction (P mode) or bi-prediction (B mode), may refer to any of several temporal-based compression modes.
[0089] In the example of FIG. 2, video encoder 20 includes a partitioning unit 35, prédiction module 41, reference picture memory 64, summer 50, transform module 52, quantization unit 54, and entropy encoding unit 56. Prédiction module 41 includes motion estimation unit 42, motion compensation unit 44, and intra prédiction module 46. For video block reconstruction, video encoder 20 also includes inverse quantization 35 unit 58, inverse transform module 60, and summer 62. A deblocking filter (not shown in FIG. 2) may also be included to filter block boundaries to remove blockiness artifacts
from reconstructed video. If desired, the deblocking filter would typically filter the output of summer 62. Additional loop fïlters (in loop or post loop) may also be used in addition to the deblocking filter.
[0090] As shown in FIG. 2, video encoder 20 receives video data, and partitioning unit partitions the data into video blocks. This partitioning may also include partitioning into slices, tiles, or other larger units, as wells as video block partitioning, e.g., according to a quadtree structure of LCUs and CUs. Video encoder 20 generally illustrâtes the components that encode video blocks within a video slice to be encoded.
10 The slice may be divided into multiple video blocks (and possibly into sets of video blocks referred to as tiles). Prédiction module 41 may select one of a plurality of possible coding modes, such as one of a plurality of intra coding modes or one of a plurality of inter coding modes, for the current video block based on errer results (e.g., coding rate and the level of distortion). Prédiction module 41 may provide the resulting d R intra- or inter-coded block to summer 50 to generate residual block data and to summer 62 to reconstruct the encoded block for use as a reference picture.
[0091] Intra prédiction module 46 within prédiction module 41 may perform intrapredictive coding of the current video block relative to one or more neighboring blocks in the same frame or slice as the current block to be coded to provide spatial 20 compression. Motion estimation unit 42 and motion compensation unit 44 within prédiction module 41 perform inter-predictive coding of the current video block relative to one or more prédictive blocks in one or more reference pictures to provide temporal compression.
[0092] Motion estimation unit 42 may be configured to détermine the inter-prediction 25 mode for a video slice according to a predetermined pattern for a video sequence. The predetermined pattern may designate video slices in the sequence as P slices, B slices or GPB slices. Motion estimation unit 42 and motion compensation unit 44 may be highly integrated, but are illustrated separately for conceptual purposes. Motion estimation, performed by motion estimation unit 42, is the process of generating motion vectors, S0 which estimate motion for video blocks. A motion vector, for example, may indicate the displacement of a PU of a video block within a current video frame or picture relative to a prédictive block within a reference picture.
[0093] A prédictive block is a block that is found to closely match the PU of the video block to be coded in terms of pixel différence, which may be determined by sum of 5 absolute différence (SAD), sum of square différence (SSD), or other différence metrics.
In some examples, video encoder 20 may calculate values for sub-integer pixel positions of reference pictures stored in reference picture memory 64. For example, video encoder 20 may interpolate values of one-quarter pixel positions, one-eighth pixel positions, or other fractional pixel positions of the reference picture. Therefore, motion estimation unit 42 may perform a motion search relative to the full pixel positions and fractional pixel positions and output a motion vector with fractional pixel précision.
[0094] Motion estimation unit 42 calculâtes a motion vector for a PU of a video block in an inter-coded slice by comparing the position of the PU to the position of a prédictive block of a reference picture. The reference picture may be selected from a 10 first reference picture list (List 0) or a second reference picture list (List 1), each of which identify one or more reference pictures stored in reference picture memory 64.
Motion estimation unit 42 sends the calculated motion vector to entropy encoding unit and motion compensation unit 44.
[0095] Motion compensation, performed by motion compensation unit 44, may involve fetching or generating the prédictive block based on the motion vector determined by motion estimation, possibly performing interpolations to sub-pixel précision. Upon receiving the motion vector for the PU of the current video block, motion compensation unit 44 may locate the prédictive block to which the motion vector points in one of the reference picture lists. Video encoder 20 forms a residual video block by subtracting pixel values of the prédictive block from the pixel values of the current video block being coded, forming pixel différence values. The pixel différence values form residual data for the block, and may include both luma and chroma différence components.
Summer 50 represents the component or components that perform this subtraction operation. Motion compensation unit 44 may also generate syntax éléments 55 25 associated with the video blocks and the video slice for use by video décoder 30 in decoding the video blocks of the video slice.
[0096] Motion compensation unit 44 may generate syntax éléments 55 that conform to a syntax structure in accordance with techniques described in this disclosure. In some examples, video encoder 20 may generate syntax éléments 55 to directly signal, in the 30 video parameter set (VPS) syntax structure or in the video usability information (VUI) part of the sequence parameter set (SPS) syntax structure associated with the video blocks, ail syntax éléments that define the condition for signaling a number of clock ticks corresponding to a différence of picture order count (POC) values equal to 1. In other words, rather than signaling the syntax éléments for the condition for signaling a number of clock ticks corresponding to a différence of picture order count (POC) values equal to 1 in another syntax structure (such as the HRD parameters syntax structure) that is incorporated into a VPS syntax structure or VUI part of the SPS syntax structure, the motion compensation unit 44 generates the encoded bitstream to signal the syntax éléments for the syntax éléments that defïne the condition in the VPS and/or VUI syntax structure without reference to another syntax structure potentially incorporated within either/both of the VPS and VUI syntax structure.
[0097] In some examples, the motion compensation unit 44 may generate the syntax éléments 55 to signal the time scale and the number of units in a clock tick at most once in each of the VPS and VUI syntax structures for a given coded video sequence. That is, in a given VPS syntax structure for the encoded bitstream, the motion compensation unit 44 may generate the syntax éléments 55 to signal the time scale and number of units in a clock tick syntax éléments at most once. Likewise, in a given VUI syntax structure (e.g., the VUI part of an SPS syntax structure) for the encoded bitstream, the motion compensation unit 44 may generate the syntax éléments 55 signal the time scale and number of units in a clock tick syntax éléments at most once. In addition, the motion compensation unit 44 may in some instances generate the syntax éléments 55 to directly signal the time scale and the number of units in a clock tick in each of the VPS and VUI syntax structures for a given coded video sequence, rather than in an HRD parameters syntax structure incorporated within a VPS and/or VUI syntax structure.
[0098] In some examples, the motion compensation unit 44 may generate the syntax éléments 55 to signal, in a VPS syntax structure for one or more coded video sequences, a flag indicating whether the POC value for each picture in a coded video sequence that is not the first picture in the coded video sequence, in decoding order, is proportional to the output time of the picture relative to the output time of the first picture in the coded video sequence. This indication flag may altematively be referred to as the POC proportional to timing indication flag. As a resuit, the motion compensation unit 44 may reduce a number of instances of the indication in the timing information signaled for multiple layers of a coded video sequence and/or for a scalable video bitstream having multiple layers. In some instances, the motion compensation unit 44 may include this flag in the VPS syntax structure only if the time scale and number of units in a clock tick syntax éléments are also included. The motion compensation unit 44 may in this way avoid signaling this particular timing information (i.e., whether the POC value for each picture in a coded video sequence that is not the first picture in the
coded video sequence, in decoding order, is proportional to the output time of the 5 picture relative to the output time of the first picture in the coded video sequence) if the clock tick information needed for using the POC proportional to timing indication is not also présent.
[0099] Example changes to the HEVC WD9 text to effectuate the above techniques for generating syntax éléments 55 are as follows (other parts not mentioned may 0 unmodified vis-à-vis HEVC WD9):
[0100] The following is an example of a video parameter set RBSP syntax structure modified to solve one or more of the above problème (the underlined syntax is an addition to the video parameters set RBSP syntax structure of HEVC WD9; other syntax may be unchanged relative to HEVC WD9):
video parameter set rbsp( ) { Descriptor
...
vos timing info présent flag u(l)
iff vos timing info présent flag ) (
vps num units in tick u(32)
vps time scale u(32)
vps poc proportional to timing flag uiü
iff vos doc DroDortional to timing flag )
vps num ticks poc diff one minus 1 ue(v)
i
vpsnumhrdparameters ue(v)
for( i = 0; i < vps num hrd parameters; i++ ) {
cprmsjpresent flag[ i ] u(l)
hrd_parameters( cprms_present_flag[ i ], vps max sub layers minus 1 )
}
}
Table 4: Example video parameter set RBSP syntax structure [0101] Table 4 defines newly-added syntax éléments according to the following video parameter set (VPS) RBSP semantics:
[0102] vps timing info présent flag equal to 1 spécifiés that vps num units in tick, vps_time_scale, and vps_poc_proportional_to_timing_flag are présent in the video parameter set. vps_timing_info_present_flag equal to 0 spécifiés that
vps num units in tick, vps time scale, and vps_poc_proportional_to_timing_flag are not présent in the video parameter set.
[0103] vps_num_units_in_tick is the number of time units of a clock operating at the frequency vps_time_scale Hz that corresponds to one incrément (called a clock tick) of a clock tick counter. The value of vps_num_units_in_tick shall be greater than 0. A clock tick, in units of seconds, is equal to the quotient of vps_num_units_in_tick divided by vps_time_scale. For example, when the picture rate of a video signal is 25 Hz, vps_time_scale may be equal to 27,000,000 and vps_num_units_in_tick may be 10 equal to 1,080,000, and consequently a clock tick may be 0.04 seconds.
[0104] vps_time_scale is the number of time units that pass in one second. For example, a time coordinate System that measures time using a 27 MHz clock has a vps_time_scale of 27,000,000. The value of vps_time_scale shall be greater than 0.
[0105] vps poc proportional to timing flag equal to 1 indicates that the picture order count value for each picture in the coded video sequence that is not the first picture in the coded video sequence, in decoding order, is proportional to the output time of the picture relative to the output time of the first picture in the coded video sequence. vps_poc_proportional_to_timing_flag equal to 0 indicates that the picture order count value for each picture in the coded video sequence that is not the first picture in the coded video sequence, in decoding order, may or may not be proportional to the output time of the picture relative to the output time of the first picture in the coded video sequence.
[0106] vps_num_ticks_poc_diff_one_minusl plus 1 spécifiés the number of clock ticks corresponding to a différence of picture order count values equal to 1. The value of ne vps_num_ticks_poc_diff_one_minusl shall be in the range of 0 to 2Λ32 - 1, inclusive.
[0107] The following is an example of a VUl parameters syntax structure modified to solve one or more of the above problème (the underlined syntax is an addition to the VUl parameters syntax structure of HEVC WD9; the italicized syntax is removed from the VUl parameters syntax structure of HEVC WD9; other portions of the syntax table 3θ are unchanged relative to HEVC WD9):
vui parameters( ) { Descriptor
···
sds timing info présent flag uO)
ifï sds timing info présent flag 1 i
sds num units in tick u(32)
sds time scale u(32)
sds doc DroDortional to timing flag u(l)
ifi sds doc DroDortional to timing flag )
sds num ticks doc diff one minusl ue(v)
i
hrdjparametersjpresent flag u(l)
if( hrd parameters present flag )
hrd parameters( 1, sps max sub layers minusl )
poc proportional to timing flag u(l)
if( poc _proportional_totimingJlag && timing info présent flag)
num ticks poc dijf one minusl ue(v)
...
}
Table 5: Example modified VUIparameters syntax structure [0108] Table 5 defines newly-added syntax éléments according to the following VUI parameters semantics (semantics for the removed syntax éléments are likewise removed):
[0109] sps_timing_info_present_flag equal to 1 spécifiés that sps num units in tick, spstimescale, and sps_poc_proportional_to_timing_flag are présent in the vui_parameters( ) syntax structure. sps_timing_info_present_flag equal to 0 spécifiés that sps_num_units_in_tick, sps_time_scale, and sps_poc_proportional_to_timing_flag 10 are not présent in the vui_parameters( ) syntax structure.
[0110] sps_num_units_in_tick is the number of time units of a clock operating at the frequency sps time scale Hz that corresponds to one incrément (called a clock tick) of a clock tick counter. sps_num_units_in_tick shall be greater than 0. A clock tick, in units of seconds, is equal to the quotient of sps_num_units_in_tick divided by 15 sps time scale. For example, when the picture rate of a video signal is 25 Hz, sps time scale may be equal to 27,000,000 and sps_num_units_in_tick may be equal to 1,080,000, and consequently a clock tick may be equal to 0.04 seconds (see Equation (1)). When vps num units in tick is présent in the video parameter set referred to by
the sequence parameter set, sps_num_units_in_tick, when présent, shall be equal to 5 vps_num_units_in_tick.
[OUI] The formula for deriving the variable ClockTick (also referred to herein as a “clock tick”) is modified to be as follows:
, sps num units in tick ClockTick =--------=-----— --- Equation (I) sps _ time _ scale [0112] sps_time_scale is the number of time units that pass in one second. For example, a time coordinate system that measures time using a 27 MHz clock has a sps_time_scale of 27,000,000. The value of sps time scale shall be greater than 0.
When vps_time_scale is présent in the video parameter set referred to by the sequence parameter set, sps time scale, when présent, shall be equal to vps time scale.
[0113] sps_poc_proportional_to_timing_flag equal to 1 indicates that the picture order count value for each picture in the coded video sequence that is not the first picture in the coded video sequence, in decoding order, is proportional to the output time of the picture relative to the output time of the first picture in the coded video sequence. The sps_poc_proportional_to_timing_flag equal to 0 indicates that the 20 picture order count value for each picture in the coded video sequence that is not the first picture in the coded video sequence, in decoding order, may or may not be proportional to the output time of the picture relative to the output time of the first picture in the coded video sequence. When vps_poc_proportional_to_timing_flag is présent in the video parameter set referred to by the sequence parameter set, sps_poc_proportional_to_timing flag, when présent, shall be equal to vps_poc_proportional_to_timing_flag.
[0114] sps_num_ticks_poc_diff_one_minusl plus 1 spécifiés the number of clock ticks corresponding to a différence of picture order count values equal to 1. The value of sps_num_ticks_poc_diff_one_minusl shall be in the range of 0 to 2Λ32 - 1, inclusive. 3θ When vps_num_ticks_poc_diff_one_minusl is présent in the video parameter set referred to by the sequence parameter set, sps_num_ticks_poc_diff_one_minusl, when présent, shall be equal to sps_num_ticks_poc_diff_one_minusl.
[0115] The following is an example of an HRD parameters syntax structure modified to solve one or more of the above problems (the italicized syntax is removed from the HRD parameters syntax structure of HEVC WD9):
hrd_parameters( commonlnfPresentFlag, Descript
maxNumSubLayersMinusl ) { or
if( commonlnfPresentFlag ) {
timing info presentJlag u(V
if( timing info present Jlag ) {
num units in tick u(32)
time scale u(32)
}
...
}
Table 6: Example modified HRD parameters syntax structure [0116] Semantics for syntax éléments removed according to the example modified HRD parameters syntax structure of Table 6 are likewise removed.
[0117] The intra-prediction module 46 may intra-predict a current block, as an alternative to the inter-prediction performed by motion estimation unit 42 and motion compensation unit 44, as described above. In particular, intra-prediction module 46 may détermine an intra-prediction mode to use to encode a current block. In some examples, intra-prediction module 46 may encode a current block using various intraprediction modes, e.g., during separate encoding passes, and intra-prediction module 46 (or mode select unit 40, in some examples) may select an appropriate intra-prediction mode to use from the tested modes. For example, intra-prediction module 46 may calculate rate-distortion values using a rate-distortion analysis for the various tested intra-prediction modes, and select the intra-prediction mode having the best ratedistortion characteristics among the tested modes. Rate-distortion analysis generally détermines an amount of distortion (or error) between an encoded block and an original, unencoded block that was encoded to produce the encoded block, as well as a bit rate (that is, a number of bits) used to produce the encoded block. Intra-prediction module 46 may calculate ratios from the distortions and rates for the various encoded blocks to détermine which intra-prediction mode exhibits the best rate-distortion value for the block.
[0118] In any case, after selecting an intra-prediction mode for a block, intra-prediction module 46 may provide information indicative of the selected intra-prediction mode for the block to entropy encoding unit 56. Entropy encoding unit 56 may encode the information indicating the selected intra-prediction mode in accordance with the techniques of this disclosure. Video encoder 20 may include in the transmitted
bitstream configuration data, which may include a plurality of intra-prediction mode index tables and a plurality of modified intra-prediction mode index tables (also referred to as codeword mapping tables), définitions of encoding contexts for various blocks, 5 and indications of a most probable intra-prediction mode, an intra-prediction mode index table, and a modified intra-prediction mode index table to use for each of the contexts.
[0119] After prédiction module 41 generates the prédictive block for the current video block via either inter-prediction or intra-prediction, video encoder 20 forms a residual 10 video block by subtracting the prédictive block from the current video block. The residual video data in the residual block may be included in one or more TUs and applied to transform module 52. Transform module 52 transforms the residual video data into residual transform coefficients using a transform, such as a discrète cosine transform (DCT) or a conceptually similar transform. Transform module 52 may 15 convert the residual video data from a pixel domain to a transform domain, such as a frequency domain.
[0120] Transform module 52 may send the resulting transform coefficients to quantization unit 54. Quantization unit 54 quantizes the transform coefficients to further reduce bit rate. The quantization process may reduce the bit depth associated 20 with some or ail of the coefficients. The degree of quantization may be modified by adjusting a quantization parameter. In some examples, quantization unit 54 may then perform a scan of the matrix including the quantized transform coefficients. Altematively, entropy encoding unit 56 may perform the scan.
[0121] Following quantization, entropy encoding unit 56 entropy encodes the quantized 25 transform coefficients. For example, entropy encoding unit 56 may perform context adaptive variable length coding (CAVLC), context adaptive binary arithmetic coding (CABAC), syntax-based context-adaptive binary arithmetic coding (SBAC), probability interval partitioning entropy (PIPE) coding or another entropy encoding methodology or technique. Following the entropy encoding by entropy encoding unit 56, the encoded 30 bitstream may be transmitted to video décoder 30, or archived for later transmission or retrieval by video décoder 30. Entropy encoding unit 56 may also entropy encode the motion vectors and the other syntax éléments for the current video slice being coded.
[0122] Inverse quantization unit 58 and inverse transform module 60 apply inverse quantization and inverse transformation, respectively, to reconstruct the residual block 35 in the pixel domain for later use as a reference block of a reference picture. Motion
• compensation unit 44 may calculate a reference block by adding the residual block to a prédictive block of one of the reference pictures within one of the reference picture lists. Motion compensation unit 44 may also apply one or more interpolation filters to the reconstructed residual block to calculate sub-integer pixel values for use in motion 5 estimation. Summer 62 adds the reconstructed residual block to the motion compensated prédiction block produced by motion compensation unit 44 to produce a reference block for storage in reference picture memory 64 (sometimes called a decoded picture buffer (DPB)). The reference block may be used by motion estimation unit 42 and motion compensation unit 44 as a reference block to inter-predict a block in a 10 subséquent video frame or picture.
[0123] The video encoder 20 may optionally include a hypothetical reference décoder (HRD) 57 (illustrated as optional by use of dashed Unes) to check encoded bitstreams generated by éléments of video encoder 20 for conformance to the buffer model defined for the HRD 57. The HRD 57 may check Type I and/or Type II bitstreams or bitstream 15 subsets for HRD conformance. Parameters sets needed for operation of the HRD 57 are signaled by one of two types of HRD parameter sets, NAL HRD parameters and VCL HRD parameters. As described above, the HRD parameter sets may be incorporated within the SPS syntax structure and/or the VPS syntax structure.
[0124] The HRD 57 may test the video blocks and associated syntax éléments 55 for 20 conformance to requirements specifîed as one or more bitstream conformance tests defined in a video coding spécification, such as HEVC WD9 or a successor spécification such as HEVC WD10. For example, the HRD 57 may test the encoded bitstream for conformance by processing the syntax éléments 55 to détermine, from the VPS syntax structure or in the VUI part of the SPS syntax structure for a coded video 25 sequence, the syntax éléments that define the condition for signaling the number of clock ticks corresponding to a différence of POC values equal to 1. If the condition holds according to the syntax element values, HRD 57 may détermine the number of clock ticks corresponding to a différence of POC values equal to 1 and use the detennined number of clock ticks as input for, e.g., determining CPB underflow or 30 overflow during decoding of encoded pictures included in the encoded bitstream. Use herein of the term “processing” with regard to a syntax éléments may refer to extracting, decoding and extracting, reading, parsing, and any other serviceable operation or combination of operations to obtain syntax éléments in a form usable by a decoder/HRD 57.
o(
[0125] As another example, the HRD 57 may test the encoded bitstream for conformance by decoding the encoded bitstream to détermine the time scale and the number of units in a clock tick from a VPS syntax structure of syntax éléments 55 that encodes the time scale and the number of units in a clock tick syntax éléments at most once in the VPS syntax structure. In some instances, the HRD 57 may test the encoded bitstream for conformance by decoding the syntax éléments 55 to détermine the time scale and the number of units in a clock tick from a VUI syntax structure of the encoded bitstream that encodes the time scale and the number of units in a clock tick syntax éléments at most once in the VUI syntax structure. The time scale and number of units in a clock tick may be signaled other than in an HRD parameters syntax structure 15 incorporated within the VPS and/or VUI syntax structure. The HRD 57 may use the determined time scale and the determined number of units in a clock tick as input for, e.g., determining CPB underflow or overflow during decoding of encoded pictures included in the encoded bitstream.
[0126] According to techniques described herein, the HRD 57 may test the encoded 20 bitstream for conformance by decoding, from a VPS syntax structure of the syntax éléments 55 for one or more coded video sequences, the value for a POC proportional to timing indication flag. The HRD 57 may additionally, or altematively, test an encoded bitstream for conformance by decoding the value for a POC proportional to timing indication flag in the VPS syntax structure only if the time scale and number of units in 25 a clock tick syntax éléments are also included. The HRD 57 may use the determined value of the POC proportional to timing indication flag and the time scale and number of units in a clock tick syntax éléments as input for, e.g., determining CPB underflow or overflow during decoding of encoded pictures included in the encoded bitstream.
[0127] FIG. 3 is a block diagram illustrating an example video décoder 76 that may 30 implement the techniques described in this disclosure. In the example of FIG. 3, video décoder 76 includes coded picture buffer (CPB) 78, entropy decoding unit 80, prédiction module 81, inverse quantization unit 86, inverse transformation unit 88, summer 90, and decoded picture buffer (DPB) 92. Prédiction module 81 includes motion compensation unit 82 and intra prédiction module 84. Video décoder 76 may, in 35 some examples, perform a decoding pass generally reciprocal to the encoding pass described with respect to video encoder 20 from FIG. 2. Video décoder 76 may represent an example instance of video décoder 30 of destination device 14 or of hypothetical reference décoder 57 of FIG. 2.
[0128] CPB 78 stores coded pictures from the encoded picture bitstream. In one example, CBP 78 is a first-in first-out buffer containing access units (AU) in decoding order. An AU is set of network abstraction layer (NAL) units that are associated with each other according to a specified classification rule, are consecutive in decoding order, and each contain exactly one coded picture. Decoding order is the order in which pictures are decoded, and may differ from the order in which pictures are displayed (i.e., the display order). The operation of the CPB may be specified by a hypothetical reference décoder (HRD).
[0129] During the decoding process, video décoder 76 receives an encoded video bitstream that represents video blocks of an encoded video slice and associated syntax éléments from video encoder 20. Entropy decoding unit 80 of video décoder 76 décodés the bitstream to generate quantized coefficients, motion vectors, and other syntax éléments 55. Entropy decoding unit 80 forwards the motion vectors and other syntax éléments 55 to prédiction module 81. Video décoder 76 may receive the syntax éléments 55 at the video slice level and/or the video block level. The encoded video bitstream may include timing information signaled according to techniques described below. For example, the encoded video bitstream may include a video parameter set (VPS), a sequence parameter set (SPS), or any combination thereof having syntax structures according to techniques described herein to signal parameters for HRD operations.
[0130] When the video slice is coded as an intra-coded (I) slice, intra prédiction module 84 of prédiction module 81 may generate prédiction data for a video block of the current video slice based on a signaled intra prédiction mode and data from previously decoded blocks of the current frame or picture. When the video frame is coded as an inter-coded (i.e., B, P or GPB) slice, motion compensation unit 82 of prédiction module 81 produces prédictive blocks for a video block of the current video slice based on the motion vectors and other syntax éléments 55 received from entropy decoding unit 80. The prédictive blocks may be produced from one of the reference pictures within one of the reference picture lists. Video décoder 76 may construct the reference frame lists, List 0 and List 1, using default construction techniques based on reference pictures stored in DPB 92.
[0131] Motion compensation unit 82 détermines prédiction information for a video block of the current video slice by parsing the motion vectors and other syntax éléments 55, and uses the prédiction information to produce the prédictive blocks for the current
video block being decoded. For example, motion compensation unit 82 uses some of the received syntax éléments 55 to détermine a prédiction mode (e.g., intra- or inter5 prédiction) used to code the video blocks of the video slice, an inter-prediction slice type (e.g., B slice, P slice, or GPB slice), construction information for one or more of the reference picture lists for the slice, motion vectors for each inter-encoded video block of the slice, inter-prediction status for each inter-coded video block of the slice, and other information to décodé the video blocks in the current video slice.
1Ω [0132] Motion compensation unit 82 may also perform interpolation based on interpolation filters. Motion compensation unit 82 may use interpolation filters as used by video encoder 20 during encoding of the video blocks to calculate interpolated values for sub-integer pixels of reference blocks. In this case, motion compensation unit 82 may détermine the interpolation filters used by video encoder 20 from the received 15 syntax éléments 55 and use the interpolation filters to produce prédictive blocks.
[0133] Inverse quantization unit 86 inverse quantizes, i.e., de-quantizes, the quantized transform coefficients provided in the bitstream and decoded by entropy decoding unit 80. The inverse quantization process may include use of a quantization parameter calculated by video encoder 20 for each video block in the video slice to détermine a 20 degree of quantization and, likewise, a degree of inverse quantization that should be applied. Inverse transform unit 88 applies an inverse transform, e.g., an inverse DCT, an inverse integer transform, or a conceptually similar inverse transform process, to the transform coefficients in order to produce residual blocks in the pixel domain.
[0134] After motion compensation unit 82 generates the prédictive block for the current oc video block based on the motion vectors and other syntax éléments 55, video décoder forms a decoded video block by summing the residual blocks from inverse transform unit 88 with the corresponding prédictive blocks generated by motion compensation unit 82. Summer 90 represents the component or components that perform this summation operation. If desired, a deblocking filter may also be applied to filter the •0 decoded blocks in order to remove blockiness artifacts. Other loop filters (either in the coding loop or after the coding loop) may also be used to smooth pixel transitions, or otherwise improve the video quality. The decoded video blocks in a given frame or picture are then stored in DPB 92, which stores reference pictures used for subséquent motion compensation. DPB 92 also stores decoded video for later présentation on a 5 display device, such as display device 32 of FIG. 1. Like CPB 78, in one example, the operation of DPB 92 may be specifïed by the Hypothetical Reference Décoder (HRD).
[0135] Encoder 20 and décoder 76, as described m this disclosure, represent examples of devices configured to perform techniques for signaling timing in a video coding process as described in this disclosure. Accordingly, operations described in this disclosure for signaling time may be performed by encoder 20, décoder 76 or both. In some instances, encoder 20 may signal timing information and décoder 76 may receive such timing information, e.g., for using in defïning one or more HRD features, characteristics, parameters, or conditions.
[0136] Video décoder 76 may in some instances be a video décoder 76 under test (or VUT). The video décoder 76 may receive a représentation of the encoded bitstream generated by a video encoder 20 to directly signal, in the VPS syntax structure or in the VUI part of the SPS syntax structure of syntax éléments 55 for a coded video sequence, ail syntax éléments that define the condition for signaling a number of clock ticks corresponding to a différence of picture order count (POC) values equal to 1. Video décoder 76 may décodé the encoded bitstream to détermine, from the VPS syntax structure or in the VUI part of the SPS syntax structure for a coded video sequence, the syntax éléments that define the condition for signaling the number of clock ticks corresponding to a différence of POC values equal to 1. If the condition holds according to the syntax element values, video décoder 76 may détermine the number of clock ticks corresponding to a différence of POC values equal to 1 and use the determined number of clock ticks as input for, e.g., determining CPB 78 underflow or overflow during decoding of encoded pictures included in the encoded bitstream.
[0137] In another example, the video encoder 20 may receive a représentation of the encoded bitstream generated by video encoder 20 to signal the time scale and the number of units in a clock tick at most once in each of the VPS and VUI syntax structures of syntax éléments 55 for a given coded video sequence. The video décoder 76 may décodé the encoded bitstream to détermine the time scale and the number of units in a clock tick from a VPS syntax structure of the encoded bitstream that encodes the time scale and the number of units in a clock tick syntax éléments at most once in the VPS syntax structure. In some instances, the video décoder 76 may test the encoded bitstream for conformance by decoding the encoded bitstream to détermine the time scale and the number of units in a clock tick from a VUI syntax structure of the encoded bitstream that encodes the time scale and the number of units in a clock tick syntax éléments at most once in the VUI syntax structure. The time scale and number of units in a clock tick may be signaled other than in an HRD parameters syntax structure
incorporated within the VPS and/or VUI syntax structure. Video décoder 76 may use the determined time scale and the determined number of units in a clock tick as input for, e.g., determining CPB 78 underflow or overflow during decoding of encoded pictures included in the encoded bitstream.
[0138] In another example, the video décoder 76 may receive a représentation of the encoded bitstream generated by video encoder 20 to signal, in a VPS syntax structure of syntax éléments 55 for one or more coded video sequences, a POC proportional to timing indication flag. The video décoder 76 may test the encoded bitstream for conformance by decoding the encoded bitstream to détermine a value for the flag. The 1θ video décoder 76 may additionally, or altematively, test an encoded bitstream, generated by video décoder 76 to signal the flag in the VPS syntax structure only if the time scale and number of units in a clock tick syntax éléments are also included. The video décoder 76 may use the determined value of the POC proportional to timing indication flag and the time scale and number of units in a clock tick syntax éléments as 15 input for, e.g., determining CPB 78 underflow or overflow during decoding of encoded pictures included in the encoded bitstream.
[0139] FIG. 4 is a block diagram illustrating an example coding structure 100 for a reference picture set. The coding structure 100 includes slices 102A-102E (collectively, “slices 102”). Picture order count 108 associated with the coding structure 2θ 100 dénotés the output order of the corresponding slice in the reference picture set. For example, I-slice 102A is to be output first (POC value 0) while b-slice 102B is to be output second (POC value 1). Decoding order 110 associated with the coding structure 100 dénotés the decoding order for the corresponding slice in the reference picture set. For example, I-slice 102A is to be output first (decoding order 1) while b-slice 102B is 25 to be output second (decoding order 2).
[0140] Arrow 104 indicates an output time for the pictures along a time continuum t. Time interval 106 represents a time interval corresponding to a différence of picture order count (POC) values equal to 1. The time interval 106 may include a number of clock ticks, which may dépend upon the time scale (corresponding, e.g., to an oscillator 30 frequency - such as 27 MHz - that defînes a time coordinate System for the signaled information) and the number of time units of a clock operating at the time scale that corresponds to one incrément of a clock tick counter, which is referred to as a “clock tick.” In accordance with techniques described herein, a video encoder 20 may generate a bitstream to directly signal, in the video parameter set (VPS) syntax structure or in the
video usability information (VUI) part of the sequence parameter set (SPS) syntax structure for a coded video sequence, syntax éléments that define a condition for signaling a number of clock ticks corresponding to a différence of picture order count (POC) values equal to l.
[0141] FIG. 5 is a flowchart illustrating an example method of operation according to techniques described in this disclosure. A video encoder 20 encodes pictures of a video sequence to generate a coded video sequence (200). The video encoder 20 additionally generates parameter sets for the coded video sequence. The parameter sets may include parameters encoded according to a sequence parameter set (SPS) syntax structure and/or according to a video parameter set (VPS) syntax structure. According to techniques 15 described herein, the video encoder 20 encodes syntax éléments for the number of units in a clock tick and the time scale directly to the VPS syntax structure and/or directly to the SPS syntax structure for the coded video sequence (202). The term “directly” indicates that such encoding may be generated without incorporating, in the VPS syntax structure or SPS syntax structure (as applicable), the syntax éléments for the number of ’θ units in a clock tick and the time scale defined for a separate parameter set syntax structure, such as that corresponding to the hypothetical reference décoder (HRD) parameter set as defined in HEVC WD9.
[0142] In addition, the video encoder 20 encodes, directly to the VPS syntax structure and/or SPS syntax structure of the coded video sequence, a condition for signaling a 5 number of clock ticks corresponding to a différence of picture order count (POC) values equal to one (204). The condition may include one or more syntax éléments that represent variables for a Boolean formula, in which case video encoder 20 may encode each such syntax element directly to the VPS syntax structure and/or SPS syntax structure of the coded video sequence. The video encoder 20 outputs the coded video ,0 sequence and the VPS syntax structure and/or the SPS syntax structure for the coded video sequence (206). In some cases, the video encoder 20 outputs these structures to a HRD of the video encoder 20.
[0143] FIGS. 6A-6B are flowcharts illustrating example methods of operation according to techniques described in this disclosure. In FIG. 6A, a video encoder 20 5 encodes pictures of a video sequence to generate a coded video sequence (300). The video encoder 20 additionally generates parameter sets for the coded video sequence. The parameter sets may include parameters encoded according to a video parameter set (VPS) syntax structure. According to techniques described herein, the video encoder 20
encodes syntax éléments for the number of units in a clock tick and the time scale 5 directly, and at most once, to a VPS syntax structure for the coded video sequence (302). In some instances, even in cases in which the VPS syntax structure includes multiple instances of HRD parameters, by encoding the syntax éléments directly to the VPS syntax structure (at most once) and not to the HRD parameter sets (or any other incorporated parameter set syntax structure), the VPS syntax structure may include a 0 single syntax element for each of the number of units in a clock tick and the time scale.
The video encoder 20 outputs the coded video sequence and the VPS syntax structure for the coded video sequence (304). In some cases, the video encoder 20 outputs these structures to a HRD of the video encoder 20.
[0144] In FIG. 6B, a video encoder 20 encodes pictures of a video sequence to generate 5 a coded video sequence (310). The video encoder 20 additionally generates parameter sets for the coded video sequence. The parameter sets may include parameters encoded according to a video parameter set (SPS) syntax structure. According to techniques described herein, the video encoder 20 encodes syntax éléments for the number of units in a clock tick and the time scale directly, and at most once, to a SPS syntax structure for the coded video sequence (312). In some instances, even in cases in which the SPS syntax structure includes multiple instances of HRD parameters, by encoding the syntax éléments directly to the SPS syntax structure (at most once) and not to the HRD parameter sets (or any other incorporated parameter set syntax structure), the SPS syntax structure may include a single syntax element for each of the number of units in a clock tick and the time scale. The video encoder 20 outputs the coded video sequence and the SPS syntax structure for the coded video sequence (314). In some cases, the video encoder 20 outputs these structures to a HRD of the video encoder 20. In some instances, video encoder 20 may encode the syntax éléments for the number of units in a clock tick and the time scale to both a VPS syntax structure and an SPS syntax structure for the coded video sequence.
[0145] FIG. 7 is a flowchart illustrating an example method of operation according to techniques described in this disclosure. A video encoder 20 encodes pictures of a video sequence to generate a coded video sequence (400). The video encoder 20 additionally generates parameter sets for the coded video sequence. The parameter sets may include parameters encoded according to a video parameter set (VPS) syntax structure. If timing information is to be included, e.g., for defîning a HRD buffering model (YES branch of402), the video encoder 20 encodes, directly to A VPS syntax structure for the
coded video sequence, a syntax element having a value that spécifiés whether the picture order count (POC) value for each picture in the coded video sequence that is not the first picture in the coded video sequence, in decoding order, is proportional to the output time of the picture relative to the output time of the first picture in the coded video sequence (404). The syntax element may be semantically similar to the poc_proportional_to_timing flag defined by HEVC WD9. The timing information may represent the number of units in a clock tick and the time scale.
[0146] If the value of the syntax element is true (YES branch of 406), the video encoder 20 also encodes a syntax element for the number of clock ticks corresponding to a différence of picture order count values equal to one (408). Because the video encoder 20 encodes the syntax éléments to the VPS, the values of the syntax éléments may apply to ail layers or ail possible bitstream subsets of a scalable video bitstream, for the VPS représenta the highest layer parameter set and describes the overall characteristics of coded picture sequences.
[0147] If the timing information is not to be included in the VPS syntax structure (NO branch of 402), the video encoder 20 encodes neither the syntax element for indicating the POC is proportional to the timing information nor the syntax element for the number of clock ticks corresponding to a différence of picture order count values equal to one. If the POC is not proportional to the timing information (i.e., the value is false) (NO branch of 406), the video encoder 20 does not encode the syntax element for the number of clock ticks corresponding to a différence of picture order count values equal to one.
[0148] The video encoder 20 outputs the coded video sequence and the VPS syntax structure for the coded video sequence (410). In some cases, the video encoder 20 outputs these structures to a HRD of the video encoder 20.
[0149] FIG. 8 is a flowchart illustrating an example method of operation according to techniques described in this disclosure. A video décoder device 30 or hypothetical reference décoder 57 of a video encoder device 20 (hereinafter, “the décoder”) receives a coded video sequence and a video parameter set (VPS) syntax structure and/or a sequence parameter set (SPS) syntax structure for the coded video sequence (500). The coded video sequence and/or the syntax structure(s) may be encoded to a bitstream that includes one or more encoded pictures.
[0150] The décoder processes the VPS syntax structure and/or the SPS syntax structure to extract a syntax element that spécifiés, directly in the VPS syntax structure and/or the SPS syntax structure, a condition for signaling a number of clock ticks corresponding to
a différence of picture order count (POC) values equal to one (502). The condition may include one or more syntax éléments that represent variables for a Boolean formula, in which case the décoder may process each such syntax element directly from the VPS syntax structure and/or SPS syntax structure of the coded video sequence.
[0151] The décoder additionally processes the VPS syntax structure and/or the SPS syntax structure to extract syntax éléments for the number of units in a clock tick and the time scale directly from the VPS syntax structure and/or directly from the SPS syntax structure for the coded video sequence (504). The décoder may then verify conformance of the coded video sequence to a video buffering model that is defîned, at least in part, by the values for the condition, the number of units in a clock tick, and the time scale as extracted from the VPS syntax structure and/or the SPS syntax structure and as read from the corresponding syntax éléments (506).
[0152] FIGS. 9A-9B are flowcharts illustrating example methods of operation according to techniques described in this disclosure. In FIG. 9A, a video décoder device 30 or hypothetical reference décoder 57 of a video encoder device 20 (hereinafter, “the décoder”) receives a coded video sequence and a video parameter set (VPS) syntax structure for the coded video sequence (600). The coded video sequence and/or the VPS syntax structure may be encoded to a bitstream that includes one or more encoded pictures.
[0153] According to techniques described herein, the décoder processes the VPS syntax structure to extract syntax éléments for the number of units in a clock tick and the time scale that are occur directly, and at most once, in the VPS syntax structure for the coded video sequence (602). The décoder may then verify conformance of the coded video sequence to a video buffering model that is defîned, at least in part, by the values for the number of units in a clock tick and the time scale as extracted from the VPS syntax structure and as read from the corresponding syntax éléments (604).
[0154] In FIG. 9B, the décoder receives a coded video sequence and a video parameter set (SPS) syntax structure for the coded video sequence (610). The coded video sequence and/or the SPS syntax structures may be encoded to a bitstream that includes one or more encoded pictures.
[0155] According to techniques described herein, the décoder processes the SPS syntax structure to extract syntax éléments for the number of units in a clock tick and the time scale that are occur directly, and at most once, in the SPS syntax structure for the coded video sequence (612). The décoder may then verify conformance of the coded video
sequence to a video buffering model that is defined, at least in part, by the values for the number of units in a clock tick and the time scale as extracted from the SPS syntax structure and as read from the corresponding syntax éléments (614).
[0156] FIG. 10 is a flowchart illustrating an example method of operation according to techniques described in this disclosure. In FIG. 10, a video décoder device 30 or hypothetical reference décoder 57 of a video encoder device 20 (hereinafiter, “the décoder”) receives a coded video sequence and a video parameter set (VPS) syntax structure for the coded video sequence (700). The coded video sequence and/or the VPS syntax structure may be encoded to a bitstream that includes one or more encoded pictures.
[0157] The décoder processes the VPS syntax structure to extract a syntax element that spécifiés whether the picture order count value for each picture in the coded video sequence that is not the first picture in the coded video sequence, in decoding order, is proportional to the output time of the picture relative to the output time of the first picture in the coded video sequence (702). If the value for the syntax element is true, then the décoder further pro cesses the VPS syntax structure to extract a syntax element for the number of clock ticks corresponding to a différence of picture order count values equal to one (706). The décoder may then verify conformance of the coded video sequence to a video buffering model that is defined, at least in part, by the value for the number of clock ticks corresponding to a différence of picture order count values equal to one extracted from the VPS syntax structure and as read from the corresponding syntax element (708).
[0158] In one or more examples, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over, as one or more instructions or code, a computer-readable medium and executed by a hardware-based processing unit. Computer-readable media may include computer-readable storage media, which corresponds to a tangible medium such as data storage media, or communication media including any medium that facilitâtes transfer of a computer program from one place to another, e.g., according to a communication protocol. In this manner, computerreadable media generally may correspond to (1) tangible computer-readable storage media which is non-transitory or (2) a communication medium such as a signal or carrier wave. Data storage media may be any available media that can be accessed by one or more computers or one or more processors to retrieve instructions, code and/or data structures for implémentation of the techniques described in this disclosure. A computer program product may include a computer-readable medium.
[0159] By way of example, and not limitation, such computer-readable storage media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage, or other magnetic storage devices, Flash memory, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if instructions are transmitted from a website, server, or other remote source using a coaxial cable, fîber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fîber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the définition of medium. It should be understood, however, that computer-readable storage media and data storage media do not include connections, carrier waves, signais, or other transient media, but are instead directed to non-transient, tangible storage media. Disk and dise, as used herein, includes compact dise (CD), laser dise, optical dise, digital versatile dise (DVD), floppy disk and Blu-ray dise, where disks usually reproduce data magnetically, while dises reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
[0160] Instructions may be executed by one or more processors, such as one or more digital signal processors (DSPs), general purpose microprocessors, application spécifie integrated circuits (ASICs), field programmable logic arrays (FPGAs), or other équivalent integrated or discrète logic circuitry. Accordingly, the term “processor,” as used herein may refer to any of the foregoing structure or any other structure suitable for implémentation of the techniques described herein. In addition, in some aspects, the functionality described herein may be provided within dedicated hardware and/or software modules configured for encoding and decoding, or incorporated in a combined codée. Also, the techniques could be fully implemented in one or more circuits or logic éléments.
[0161] The techniques of this disclosure may be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC) or a set of ICs (e.g., a chip set). Various components, modules, or units are described in this disclosure to emphasize functional aspects of devices configured to perform the disclosed techniques, but do not necessarily require realization by different hardware
units. Rather, as described above, various units may be combined in a codée hardware 5 unit or provided by a collection of interoperative hardware units, including one or more processors as described above, in conjunction with suitable software and/or fïrmware.
[0162] Various examples hâve been described. These and other examples are within the scope of the following daims.

Claims (30)

1. A method for processing video data, the method comprising:
receiving a coded video sequence comprising encoded pictures of a video sequence; and
5 receiving timing parameters for the coded video sequence that include a condition for signaling a number of clock ticks corresponding to a différence of picture order count (POC) values equal to 1 directly in at least one of a video parameter set (VPS) syntax structure referenced by the coded video sequence and a sequence parameter set (SPS) syntax structure referenced by the coded video sequence.
2. The method of claim 1, wherein receiving the coded video sequence comprises receiving a coded bitstream comprising a sequence of bits that forms a représentation of the encoded pictures, the method further comprising:
verifying conformance of the coded bitstream to a video buffering model of a
15 coded picture buffer and a decoded picture buffer defined, at least in part, by the condition.
3. The method of claim 1, wherein receiving the timing parameters for the coded video sequence further comprises:
20 receiving a time scale and a number of units in a clock tick in at least one of the
VPS syntax structure and the SPS syntax structure.
4. The method of claim 1, wherein the timing parameters comprise timing parameters for hypothetical reference decoding operations.
5. The method of claim 1, wherein the condition does not include a dependency on a syntax element in a hypothetical reference décoder (HRD) parameters syntax structure of the VPS syntax structure or the SPS syntax structure.
30
6. The method of claim 1, wherein the VPS syntax structure includes the condition.
7. The method of claim 6, wherein the VPS syntax structure includes the condition as a vps_poc_proportional_to_timing_flag syntax element.
8. The method of claim 1, wherein the SPS syntax structure includes the condition.
9. The method of claim 8, wherein SPS syntax structure includes the condition as a sps_poc_proportional_to_timing_flag syntax element.
10. A method for encoding video data, the method comprising:
encoding pictures of a video sequence to generate a coded video sequence comprising the encoded pictures; and signaling timing parameters for the coded video sequence by directly signaling a 10 condition for signaling a number of clock ticks corresponding to a différence of picture order count (POC) values equal to 1 in at least one of a video parameter set (VPS) syntax structure referenced by the coded video sequence and a sequence parameter set (SPS) syntax structure referenced by the coded video sequence.
15
11. The method of claim 10, wherein the condition does not include a dependency on a syntax element signaled in a hypothetical reference décoder (HRD) parameters syntax structure.
12. The method of claim 10, wherein signaling the timing parameters further
20 comprises:
signaling a time scale and a number of units in a clock tick in at least one of the VPS syntax structure and the SPS syntax structure.
13. The method of claim 10, wherein directly signaling the condition comprises
25 signaling the condition in the VPS syntax structure.
14. The method of claim 13, wherein signaling the condition in the VPS syntax structure comprises signaling the condition as a vps_poc_proportional_to_timing_flag syntax element.
15. The method of claim 10, wherein directly signaling the condition comprises signaling the condition in the SPS syntax structure.
16. The method of claim 15, wherein signaling the condition in the SPS syntax structure comprises signaling the condition as a sps_poc_proportional_to_timing_flag syntax element.
5
17. The method of claim 10, further comprising:
generating a coded bitstream comprising a sequence of bits that forms a représentation of the encoded pictures, wherein the timing parameters at least in part define a video buffering model of a coded picture buffer and a decoded picture buffer for verifying conformance of the 10 coded bitstream.
18. The method of claim 10, wherein the timing parameters comprise timing parameters for hypothetical reference decoding operations.
15
19. A device for processing video data comprising:
a processor configured to:
receive a coded video sequence comprising encoded pictures of a video sequence; and receive timing parameters for the coded video sequence that include a condition
20 for signaling a number of clock ticks corresponding to a différence of picture order count (POC) values equal to 1 directly in at least one of a video parameter set (VPS) syntax structure referenced by the coded video sequence and a sequence parameter set (SPS) syntax structure referenced by the coded video sequence.
25 20. The device of claim 19, wherein to receive the coded video sequence the processor is further configured to receive a coded bitstream comprising a sequence of bits that forms a représentation of the encoded pictures, and wherein the processor is further configured to verify conformance of the coded
30 bitstream to a video buffering model of a coded picture buffer and a decoded picture buffer defined, at least in part, by the condition.
21. The device of claim 19, wherein to receive the timing parameters for the coded video sequence the processor is further configured to receive a time scale and a number of units in a clock tick in at least one of the VPS syntax structure and the SPS syntax structure.
22. The device of claim 19, wherein the timing parameters comprise timing parameters for hypothetical reference decoding operations.
23. The device of claim 19, wherein the condition does not include a dependency on a syntax element in a hypothetical reference décoder (HRD) parameters syntax structure of the VPS syntax structure or the SPS syntax structure.
24. The device of claim 19, wherein the VPS syntax structure includes the condition.
25. The device of claim 24, wherein the VPS syntax structure includes the condition as a vps_poc_proportional_to_timing_flag syntax element.
26. The device of claim 19, wherein the SPS syntax structure includes the condition.
27. The device of claim 26, wherein SPS syntax structure includes the condition as a sps_poc_proportional_to_timing_flag syntax element.
28. A device for encoding video data comprising:
a processor configured to:
encode pictures of a video sequence to generate a coded video sequence comprising the encoded pictures; and signal timing parameters for the coded video sequence by directly signaling a condition for signaling a number of clock ticks corresponding to a différence of picture order count (POC) values equal to 1 in at least one of a video parameter set (VPS) syntax structure referenced by the coded video sequence and a sequence parameter set (SPS) syntax structure referenced by the coded video sequence.
9 50
29. The device of claim 28, wherein the condition does not include a dependency on a syntax element signaled in a hypothetical reference décoder (HRD) parameters syntax structure.
5 30. The device of claim 28, wherein to signal the timing parameters the processor is configured to signal a time scale and a number of units in a clock tick in at least one of the VPS syntax structure and the SPS syntax structure.
31. The device of claim 28, wherein to directly signal the condition the processor is 10 configured to signal the condition in the VPS syntax structure.
32. The device of claim 31, wherein to signal the condition in the VPS syntax structure the processor is configured to signal the condition as a vps_poc_proportional_to_timing_flag syntax element.
33. The device of claim 28, wherein to directly signal the condition the processor is configured to signal the condition in the SPS syntax structure.
34. The device of claim 33, wherein to signal the condition in the SPS syntax
20 structure the processor is configured to signal the condition as a sps_poc_proportional_to_timing_flag syntax element.
35. The device of claim 28, wherein the processor is further configured to generate a coded bitstream comprising a sequence of bits that forms a
25 représentation of the encoded pictures, wherein the timing parameters at least in part define a video buffering model of a coded picture buffer and a decoded picture buffer for verifying conformance of the coded bitstream.
30 36. The device of claim 28, wherein the timing parameters comprise timing parameters for hypothetical reference decoding operations.
37. A device for processing video data comprising:
means for receiving a coded video sequence comprising encoded pictures of a video sequence; and means for receiving timing parameters for the coded video sequence that include
5 a condition for signaling a number of clock ticks corresponding to a différence of picture order count (POC) values equal to 1 directly in at least one of a video parameter set (VPS) syntax structure referenced by the coded video sequence and a sequence parameter set (SPS) syntax structure referenced by the coded video sequence.
10 38. The device of claim 37, wherein the means for receiving the coded video sequence comprise means for receiving a coded bitstream comprising a sequence of bits that forms a représentation of the encoded pictures, the device further comprising: means for verifying conformance of the coded bitstream to a video buffering model of a coded picture buffer and a decoded picture buffer defined, at least in part, by
15 the condition.
39. The device of claim 37, wherein the means for receiving the timing parameters for the coded video sequence further comprise:
means for receiving a time scale and a number of units in a clock tick in at least
20 one of the VPS syntax structure and the SPS syntax structure.
40. The device of claim 37, wherein the timing parameters comprise timing parameters for hypothetical reference decoding operations.
25 41. The device of claim 37, wherein the condition does not include a dependency on a syntax element in a hypothetical reference décoder (HRD) parameters syntax structure of the VPS syntax structure or the SPS syntax structure.
G 52
42. A non-transitory computer readable storage medium storing instructions for processing video data that upon execution by one or more processors cause the one or more processors to:
receive a coded video sequence comprising encoded pictures of a video
5 sequence; and receive timing parameters for the coded video sequence that include a condition for signaling a number of clock ticks corresponding to a différence of picture order count (POC) values equal to 1 directly in at least one of a video parameter set (VPS) syntax structure referenced by the coded video sequence and a sequence parameter set
10 (SPS) syntax structure referenced by the coded video sequence.
43. The non-transitory computer readable storage medium of claim 42, wherein to receive the coded video sequence the instructions further cause the one or more processors to receive a coded bitstream comprising a sequence of bits that
15 forms a représentation of the encoded pictures, and wherein the instructions further cause the one or more processors to verify conformance of the coded bitstream to a video buffering model of a coded picture buffer and a decoded picture buffer defined, at least in part, by the condition.
20 44. The non-transitory computer readable storage medium of claim 42, wherein to receive the timing parameters for the coded video sequence the instructions further cause the one or more processors to receive a time scale and a number of units in at least one of the VPS syntax structure and the SPS syntax structure.
25 45. The non-transitory computer readable storage medium of claim 42, wherein the timing parameters comprise timing parameters for hypothetical reference decoding operations.
46. The non-transitory computer readable storage medium of claim 42, wherein the
30 condition does not include a dependency on a syntax element in a hypothetical reference décoder (HRD) parameters syntax structure of the VPS syntax structure or the SPS syntax structure.
OA1201500263 2013-01-07 2013-12-20 Conditional signaling of picture order count timing information for video timing in video coding. OA17516A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US61/749,866 2013-01-07
US14/061,130 2013-10-23

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Publication Number Publication Date
OA17516A true OA17516A (en) 2017-02-10

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