NZ701750B2 - Improved control channel in a high-speed packet access system - Google Patents
Improved control channel in a high-speed packet access system Download PDFInfo
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- NZ701750B2 NZ701750B2 NZ701750A NZ70175012A NZ701750B2 NZ 701750 B2 NZ701750 B2 NZ 701750B2 NZ 701750 A NZ701750 A NZ 701750A NZ 70175012 A NZ70175012 A NZ 70175012A NZ 701750 B2 NZ701750 B2 NZ 701750B2
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- 230000000051 modifying Effects 0.000 claims abstract description 177
- 238000004891 communication Methods 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 13
- 238000005516 engineering process Methods 0.000 abstract description 11
- 238000010586 diagram Methods 0.000 description 38
- 230000005540 biological transmission Effects 0.000 description 20
- 230000000875 corresponding Effects 0.000 description 13
- 239000010410 layer Substances 0.000 description 9
- 238000010295 mobile communication Methods 0.000 description 6
- 230000011664 signaling Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 230000004301 light adaptation Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 230000003595 spectral Effects 0.000 description 2
- 230000003466 anti-cipated Effects 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000001413 cellular Effects 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000001419 dependent Effects 0.000 description 1
- 230000002708 enhancing Effects 0.000 description 1
- 230000002349 favourable Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006011 modification reaction Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/06—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
- H04B7/0613—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission
- H04B7/0615—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission of weighted versions of same signal
- H04B7/0619—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission of weighted versions of same signal using feedback from receiving side
- H04B7/0621—Feedback content
- H04B7/063—Parameters other than those covered in groups H04B7/0623 - H04B7/0634, e.g. channel matrix rank or transmit mode selection
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/06—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
- H04B7/0613—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission
- H04B7/0615—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission of weighted versions of same signal
- H04B7/0619—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission of weighted versions of same signal using feedback from receiving side
- H04B7/0658—Feedback reduction
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W24/00—Supervisory, monitoring or testing arrangements
- H04W24/10—Scheduling measurement reports ; Arrangements for measurement reports
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
- H04W52/04—TPC
- H04W52/06—TPC algorithms
- H04W52/14—Separate analysis of uplink or downlink
- H04W52/146—Uplink power control
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- H04W72/042—
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The proposed technology relates to a method for conveying information from a node to user equipment, UE, in a HSPA, system. The method comprises the step of obtaining (S1) rank information and modulation information related to a four-branch Multiple Input Multiple Output, MIMO, system. The method also comprises the step of combining (S2) the rank information and the modulation information related to the four-branch MIMO system into a bit pattern, and the step of transmitting (S3) the combined rank information and modulation information related to the four-branch MIMO system as said bit pattern in a control channel to the UE. In this way, a power-efficient solution for conveying information related to a four-branch MIMO system in a control channel from a node to a UE in a HSPA system is provided. so comprises the step of combining (S2) the rank information and the modulation information related to the four-branch MIMO system into a bit pattern, and the step of transmitting (S3) the combined rank information and modulation information related to the four-branch MIMO system as said bit pattern in a control channel to the UE. In this way, a power-efficient solution for conveying information related to a four-branch MIMO system in a control channel from a node to a UE in a HSPA system is provided.
Description
IMPROVED CONTROL CHANNEL
IN A HIGH-SPEED PACKET ACCESS SYSTEM
TECHNICAL FIELD
The field of the present disclosure is that of multiple input-multiple output,
MIMO, transmission in a high-speed packet access, HSPA, mobile
communication system. More particularly, the proposed technology relates
to a method and corresponding node for conveying information from a node
to user equipment, UE, and a method and corresponding UE for receiving
and processing information from a node, as well as a bit mapping method
and corresponding bit mapping device for information for a control channel
in a HSPA system, and a method and corresponding device for processing
information of such a control channel.
BACKGROUND
HSPA is generally based on High Speed Downlink Packet Access, HSDPA,
in the downlink and Enhanced Uplink, EUL, in the uplink. The Enhanced
Uplink is sometimes referred to as High Speed Uplink Packet Access,
HSUPA.
HSDPA is an enhancement to WCDMA that provides a smooth evolutionary
path to higher data rates. HSDPA includes additional transport and control
channels such as the High-Speed Downlink Shared Channel, HS-DSCH.
EUL includes additional transport and control channels such as the
Enhanced Dedicated Channel, E-DCH.
HSDPA enables improvements in capacity and end-user perception by
means of efficient sharing of common resources in the cell among many
users, rapid adaptation of the transmission parameters to the instantaneous
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radio channel conditions, increased peak bit rates and reduced delays. Fast
scheduling is a mechanism that selects which user(s) to transmit to in a
given Transmission Time Interval, TTI. The packet scheduler is a key
element in the design of a HSDPA system as it controls the allocation of the
shared resources among the users and to a great extent determines the
overall behavior of the system. In fact, the scheduler decides which users to
serve and, in close cooperation with the link adaptation mechanism, which
modulation, power and how many codes should be used for each user. This
produces the actual end-users bit rate and system capacity. The High-
Speed Downlink Shared Data Channel, HS-DSCH, is shared between users
using channel-dependent scheduling to take advantage of favorable channel
conditions in order to make best use of the available radio resources. The
downlink control information is carried on the High-Speed Shared Control
Channel, HS-SCCH.
Multiple Input Multiple Output, MIMO was introduced to increase peak data
rates through multi-stream transmission. MIMO generally denotes the use of
multiple antennas at both the transmitter and receiver. This can be used to
obtain a diversity gain and thereby increase the carrier-to-interference ratio
at the receiver. However, the term is also commonly used to denote
transmission of multiple layers or multiple streams to improve the end-user
throughput by acting as a ‘data-rate booster’ through spatial multiplexing.
Naturally, improved end-user throughput will to some extent also result in an
increased system throughput.
So-called dual-stream MIMO, also referred to as dual-branch MIMO,
supports transmission of up to two streams or layers. Each stream is
normally subject to the same physical-layer processing in terms of coding,
spreading and modulation as the corresponding single-layer HSDPA case.
Even if only a single stream is transmitted it can be beneficial to exploit both
transmit antennas by using transmit diversity. To support dual-stream
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transmission, the HS-DSCH is modified to support up to two transport blocks
per TTI. Each transport block represents one stream or layer. In effect, this
means that up to two transport blocks may be simultaneously transmitted on
the downlink shared data channel. The standardized HS-SCCH control
channel is extended to include so-called rank information about the number
of streams, i.e. the number of transport blocks to be simultaneously
transmitted to the UE, one or two, and their respective modulation scheme
as well as which pre-coding to be used. Reference can e.g. be made to the
third generation partnership project, 3GPP, technical specification TS 25.212
V10.2.0
Current work within the third generation partnership project, 3GPP,
regarding HSPA evolution include addition of several new features in order
to meet the requirements set by the International Mobile
Telecommunications Advanced, IMT-A. The main objective of these new
features is to increase the average spectral efficiency. One possible
technique for improving downlink spectral efficiency would be to introduce
support for four-branch MIMO, i.e. utilize up to four transmit and receive
antennas, to enhance the spatial multiplexing gains and to offer improved
beam forming capabilities. Four-branch MIMO, which is sometimes also
referred to as four-stream or four-layer MIMO, provides up to 84 Mbps per 5
MHz carrier for high signal to noise ratio, SNR, users and improves the
coverage for low SNR users. Four-branch MIMO supports simultaneous
transmission of up to four streams or layers on the downlink to a given UE.
The HS-DSCH is thus modified to support up to four transport blocks per
TTI, where each transport block represents one stream or layer. In effect,
this means that up to four transport blocks may be simultaneously
transmitted on the downlink shared data channel.
Introduction of four-branch MIMO will however require a new control channel
structure to send the downlink grant information to the UE. It would be
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desirable to provide a power-efficient solution for such a control channel in a
HSPA system.
6739296_4.doc
SUMMARY
It is a general object to provide a power-efficient solution for a control channel
in a HSPA system.
It is a specific object to provide a method and corresponding node for
conveying information from a node to user equipment in a HSPA system.
It is also an object to provide a method and corresponding UE for receiving
and processing information from a node in a HSPA system.
Yet another object is to provide a bit mapping method and corresponding bit
mapping device for information for a control channel in a HSPA system.
The present invention provides a method for conveying information from a
node to user equipment (UE) in a High Speed Packet Access (HSPA) system,
wherein said method comprises the steps of: obtaining rank information and
modulation information related to a four-branch Multiple Input Multiple Output
(MIMO) system, wherein the rank information indicates a number of transport
blocks, from one to four, to be simultaneously transmitted on the data channel
associated with a control channel; combining the rank information and the
modulation information related to said four-branch MIMO system into a bit
pattern of 5 bits; transmitting the combined rank information and modulation
information related to said four-branch MIMO system as said bit pattern of 5
bits in the control channel to the UE.
In one embodiment, the control channel is a High Speed Shared Control
Channel (HS-SCCH) in the HSPA system
The present invention further provides a method of receiving and processing
information from a node in a High Speed Packet Access (HSPA) system,
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wherein said method comprises the steps of: receiving, in a control channel
from the node, information including a bit pattern of 5 bits representing
combined rank information and modulation information related to a four-
branch Multiple Input Multiple Output (MIMO) system, wherein the rank
information indicates a number of transport blocks, from one to four, to be
simultaneously transmitted on the data channel associated with the control
channel; and processing the received information including decombining the
combined rank information and modulation information related to said four-
branch MIMO system.
The present invention further provides a bit mapping method for information
for a control channel in a High Speed Packet Access (HSPA) system, wherein
said method comprises the steps of: obtaining rank information and
modulation information related to a four-branch Multiple Input Multiple Output
(MIMO) system, wherein the rank information indicates a number of transport
blocks, from one to four, to be simultaneously transmitted on the data channel
associated with the control channel; and combining the rank information and
the modulation information related to said four-branch MIMO system into a bit
pattern of 5 bits for said control channel.
The present invention further provides a node configured for conveying
information to user equipment (UE) in a High Speed Packet Access (HSPA)
system, wherein said node comprises: processing circuitry configured to
obtain rank information and modulation information related to a four-branch
Multiple Input Multiple Output (MIMO) system, wherein the rank information
indicates a number of transport blocks, from one to four, to be simultaneously
transmitted on the data channel associated with a control channel; wherein
said processing circuitry is also configured to combine the rank information
and the modulation information related to said four-branch MIMO system into
a bit pattern of 5 bits; and communication circuitry configured to transmit the
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combined rank and modulation information related to said four-branch MIMO
system as said bit pattern of 5 bits in the control channel to the UE.
The present invention further provides user equipment (UE) configured for
receiving and processing information from a node in a High Speed Packet
Access (HSPA) system, wherein said UE comprises: communication circuitry
configured to receive, in a control channel from the node, information
including a bit pattern of 5 bits representing combined rank information and
modulation information related to a four-branch Multiple Input Multiple Output
(MIMO) system, wherein the rank information indicates a number of transport
blocks, from one to four, to be simultaneously transmitted on the data channel
associated with the control channel; and processing circuitry configured to
process the received information including decombining the combined rank
information and modulation information related to said four-branch MIMO
system.
The present invention further provides a bit mapping device for information for
a control channel in a High Speed Packet Access (HSPA) system, wherein
said device comprises: processing circuitry configured to obtain rank
information and modulation information related to a four-branch Multiple Input
Multiple Output (MIMO) system, wherein the rank information indicates a
number of transport blocks, from one to four, to be simultaneously transmitted
on the data channel associated with the control channel; and wherein said
processing circuitry is also configured to combine the rank information and the
modulation information related to said four-branch MIMO system into a bit
pattern of 5 bits for said control channel.
The present invention further provides a method of processing information of
a control channel in a High Speed Packet Access (HSPA) system, wherein
said method comprises the steps of: obtaining information from said control
channel including a bit pattern of 5 bits representing combined rank
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information and modulation information related to a four-branch Multiple Input
Multiple Output (MIMO) system, wherein the rank information indicates a
number of transport blocks, from one to four, to be simultaneously transmitted
on the data channel associated with the control channel; decombining the
combined rank information and modulation information related to said four-
branch MIMO system by mapping the bit pattern of 5 bits into rank information
and modulation information.
The present invention still further provides a device for processing information
of a control channel in a High Speed Packet Access (HSPA) system,
wherein said device comprises: processing circuitry configured to obtain
information from said control channel including a bit pattern of 5 bits
representing combined rank information and modulation information related
to a four-branch Multiple Input Multiple Output (MIMO) system, wherein the
rank information indicates a number of transport blocks, from one to four, to
be simultaneously transmitted on the data channel associated with the
control channel, wherein said processing circuitry is also configured to
decombine the combined rank information and modulation information
related to said four-branch MIMO system by mapping the bit pattern of 5 bits
into rank information and modulation information.
The inventor has recognized that four-branch MIMO requires more bits for
reporting information such as rank information. This means more power is
required for the control channel. However, more power to the control
channel degrades the performance of the associated data channel, and
hence degrades the system throughput.
According to a first aspect of the present disclosure, there is provided a
method for conveying information from a node to user equipment, UE, in a
HSPA, system. The method comprises the step of obtaining rank information
and modulation information related to a four-branch MIMO system. The
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method also comprises the step of combining the rank information and the
modulation information related to the four-branch MIMO system into a bit
pattern, and the step of transmitting the combined rank information and
modulation information related to the four-branch MIMO system as said bit
pattern in a control channel to the UE.
The inventor has realized that the rank information and the modulation
information related to a four-branch MIMO system can be combined into a
common bit pattern to reduce the number of bits that have to be transmitted
in the control channel to the UE, thus saving valuable power resources that
can be used for the data channel to maintain high user and system
throughput in a HSPA system.
According to a second aspect of the present disclosure, there is provided a
method of receiving and processing information from a node in a HSPA
system. The method comprises the step of receiving, in a control channel
from the node, information including a bit pattern representing combined
rank information and modulation information related to a four-branch MIMO
system. The method also comprises the step of processing the received
information including decombining the combined rank information and
modulation information related to the four-branch MIMO system.
In this way, there is provided a solution for receiving and processing the
combined rank information and modulation information related to a four-
branch MIMO system, to enable proper decoding of data to be received on a
data channel associated with the control channel.
According to a third aspect of the present disclosure, there is provided a bit
mapping method for information for a control channel in a HSPA system.
The method comprises the step of obtaining rank information and
modulation information related to a four-branch MIMO system. The method
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also comprises the step of combining the rank information and the
modulation information related to the four-branch MIMO system into a bit
pattern for the control channel.
This novel HSPA bit-mapping method enables a power-efficient solution for a
control channel in a HSPA system.
According to a fourth aspect of the present disclosure, there is provided a
node configured for conveying information to user equipment, UE, in a
HSPA system. The node comprises processing circuitry configured to obtain
rank information and modulation information related to a four-branch MIMO
system. The processing circuitry is also configured to combine the rank
information and the modulation information related to the four-branch MIMO
system into a bit pattern. The node further comprises communication
circuitry configured to transmit the combined rank and modulation
information related to the four-branch MIMO system as said bit pattern in a
control channel to the UE.
According to a fifth aspect of the present disclosure, there is provided user
equipment, UE, configured for receiving and processing information from a
node in a HSPA system. The UE comprises communication circuitry
configured to receive, in a control channel from the node, information
including a bit pattern representing combined rank information and
modulation information related to a four-branch MIMO system. The UE also
comprises processing circuitry configured to process the received
information including decombining the combined rank information and
modulation information related to the four-branch MIMO system.
According to a sixth aspect of the present disclosure, there is provided a bit
mapping device for information for a control channel in a HSPA system. The
device comprises processing circuitry configured to obtain rank information
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and modulation information related to a four-branch Multiple Input Multiple
Output, MIMO, system. The processing circuitry is also configured to
combine the rank information and the modulation information related to the
four-branch MIMO system into a bit pattern for the control channel.
According to a seventh aspect of the present disclosure, there is provided a
method of processing information of a control channel in a High Speed
Packet Access, HSPA, system. The method comprises the step of obtaining
information from the control channel including a bit pattern representing
combined rank information and modulation information related to a four-
branch Multiple Input Multiple Output, MIMO, system. The method also
comprises the step of decombining the combined rank information and
modulation information related to the four-branch MIMO system by mapping
the bit pattern into rank information and modulation information.
According to an eighth aspect of the present disclosure, there is provided a
device for processing information of a control channel in a High Speed
Packet Access, HSPA, system. The device comprises processing circuitry
configured to obtain information from the control channel including a bit
pattern representing combined rank information and modulation information
related to a four-branch Multiple Input Multiple Output, MIMO, system. The
processing circuitry is also configured to decombine the combined rank
information and modulation information related to the four-branch MIMO
system by mapping the bit pattern into rank information and modulation
information.
Other advantages will be appreciated when reading the detailed description.
6739296_4.doc
BRIEF DESCRIPTION OF THE DRAWINGS
The proposed technology, together with further objects and advantages
thereof, may best be understood by making reference to the following
description taken together with the accompanying drawings, in which:
Figure 1 is a schematic diagram that illustrates schematically an example of
a mobile communication system.
Figure 2 is a schematic flow diagram illustrating an example of a method for
conveying information from a node to user equipment, UE, in a HSPA,
system according to an embodiment.
Figure 3 is a schematic diagram illustrating an example of the combining
step according to a particular embodiment.
Figure 4 is a schematic flow diagram illustrating an example of a method of
receiving and processing information from a node in a HSPA system
according to an embodiment.
Figure 5 is a schematic flow diagram illustrating an example of a method of
receiving and processing information from a node in a HSPA system,
including also preparing decoding of data based on the processed
information according to an embodiment.
Figure 6 is a schematic diagram illustrating an example of the processing
step according to a particular embodiment.
Figure 7A is a schematic flow diagram illustrating an example of a bit
mapping method for information for a control channel in a HSPA system
according to an embodiment.
6739296_4.doc
Figure 7B is a schematic flow diagram illustrating an example of the
combining step according to a particular embodiment.
Figure 8 is a schematic block diagram illustrating an example of a node for
conveying information to user equipment, UE, in a HSPA system according
to an embodiment.
Figure 9 is a schematic block diagram illustrating an example of a node for
conveying information to user equipment, UE, in a HSPA system according
to a particular embodiment.
Figure 10 is a schematic block diagram illustrating an example of user
equipment, UE, for receiving and processing information from a node in a
HSPA system according to an embodiment.
Figure 11 is a schematic block diagram illustrating an example of user
equipment, UE, for receiving and processing information from a node in a
HSPA system according to a particular embodiment.
Figure 12 is a schematic block diagram illustrating an example of a bit
mapping device for information for a control channel in a HSPA system
according to an embodiment.
Figure 13 is a schematic block diagram illustrating an example of a bit
mapping device for information for a control channel in a HSPA system
according to a particular embodiment.
Figure 14 is a schematic block diagram illustrating an example of a node in
which a HSPA bit mapping device of figure 12 or figure 13 is implemented.
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Figure 15A is a schematic signaling diagram illustrating an example of
signaling between a Node-B and a UE in a HSPA system.
Figure 15B is a schematic diagram that illustrates schematically an example
of the timing for channel transmission.
Figure 16 is a schematic block diagram that illustrates schematically an
example of a node in a mobile communication system.
Figure 17 is a schematic block diagram that illustrates schematically an
example of a UE.
Figure 18 is a schematic diagram that illustrates schematically an example
of the contents of a signaling channel divided into two parts.
Figure 19 is a schematic flowchart illustrating an example of a method in a
node.
Figure 20 is a schematic flowchart illustrating an example of a method in a
UE.
Figure 21 is a schematic flow diagram illustrating an example of a method of
processing information of a control channel in a High Speed Packet Access,
HSPA, system according to an embodiment.
Figure 22 is a schematic block diagram illustrating an example of a device
for processing information of a control channel in a High Speed Packet
Access, HSPA, system according to an embodiment.
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DETAILED DESCRIPTION
Throughout the drawings, the same reference numbers are used for similar
or corresponding elements.
Figure 1 illustrates schematically a universal mobile telecommunications
system, UMTS, network 100 in which the present methods and apparatuses
can be implemented. It should be noted, however, that the skilled person will
readily be able to perform implementations in other similar communication
systems involving transmission of data between nodes.
In figure 1 the UMTS network 100 comprises a core network 102 and a
UMTS terrestrial radio access network, UTRAN, 103. The UTRAN 103
comprises a number of nodes in the form of radio network controllers, RNC,
105a, 105b, each of which is coupled to a set of neighbouring nodes in the
form of one or more NodeB 104a, 104b. Each NodeB 104 is responsible for
a given geographical radio cell and the controlling RNC 105 is responsible
for routing user and signalling data between that NodeB 104 and the core
network 102. All of the RNC’s 105 are coupled to one another. A general
outline of the UTRAN 103 is given in 3GPP technical specification TS
.401 V3.2.0.
Figure 1 also illustrates communicating entities in the form of mobile devices
or user equipment, UE, 106a, 106b connected to a respective NodeB 104a,
104b in the UTRAN 103 via a respective air interface 111a, 111b. Mobile
devices served by one NodeB, such as UE 106a served by NodeB 104a, are
located in a so-called radio cell. The core network 102 comprises a number
of nodes represented by node 107 and provides communication services to
the UE 106 via the UTRAN 103, for example when communicating with the
Internet 109 where, schematically, a server 110 illustrates an entity with
which the mobile devices 106 may communicate. As the skilled person
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realizes, the network 100 in figure 1 may comprise a large number of similar
functional units in the core network 102 and the UTRAN 103, and in typical
realizations of networks, the number of mobile devices may be very large.
Furthermore, as will be discussed in detail later on, communication between
the nodes in the UTRAN 103 and the mobile devices 106 may follow the
protocols as specified by 3GPP technical specification TS 25.214 V10.6.0.
Figure 2 is a schematic flow diagram illustrating an example of a method for
conveying information from a node to user equipment, UE, in a HSPA,
system according to an embodiment. The method comprises the step of
obtaining (S1) rank information and modulation information related to a four-
branch Multiple Input Multiple Output, MIMO, system. The method also
comprises the step of combining (S2) the rank information and the
modulation information related to the four-branch MIMO system into a bit
pattern, and the step of transmitting (S3) the combined rank information and
modulation information related to the four-branch MIMO system as said bit
pattern in a control channel to the UE.
In this way, a power-efficient solution for conveying information related to a
four-branch MIMO system in a control channel from a node to a UE in a HSPA
system is provided.
As previously mentioned, the inventor has recognized that the rank
information and the modulation information related to a four-branch MIMO
system can be combined into a common bit pattern to reduce the number of
bits that have to be transmitted in the control channel to the UE. This saves
valuable power resources that can be used for the data channel to maintain
high user and system throughput in a HSPA system.
6739296_4.doc
By way of example, the control channel is a High Speed Shared Control
Channel, HS-SCCH in the HSPA system. The corresponding downlink data
channel may then be the High-Speed Downlink Shared Data Channel,
HS-DSCH, also referred to as the High-Speed Physical Downlink Shared
Data Channel, HS-PDSCH.
As mentioned, MIMO technology improves transmission and reception
efficiency by using multiple transmit antennas and multiple receive
antennas. The MIMO technology generally includes spatial multiplexing,
transmit diversity and/or beamforming. A MIMO channel matrix is defined by
the number of transmit antennas and the number of receive antennas, and
can be divided into multiple independent channels. Each such channel is
often referred to as a stream or layer, and the rank of the MIMO channel
matrix typically corresponds to the number of streams or layers. The
downlink data channel such as the HS-DSCH is modified to support multiple
transport blocks per TTI, where each transport block represents one stream
or layer. According to well-accepted terminology, the rank information is
representative of the number of transport blocks to be simultaneously
transmitted on the data channel associated with the control channel; e.g.
see US Patent Applications 2008/0043867 and 2011/0064159.
The rank information and modulation information can be obtained for
example by i) determining this information in the node more or less
independently, or with the use of input from the UE and/or other node(s), or
ii) receiving this information from the UE or other node(s), or iii) any feasible
combination thereof. In this sense, the step of ‘obtaining’ rank information
and modulation information can also be referred to as a step of ‘providing’
rank information and modulation information.
By way of example, a possible scenario may be for the UE to send
information representative of rank and modulation scheme to the NodeB,
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and the NodeB then finally decides which rank and modulation to be used at
least partly based on the received information.
The inventor has discovered that the rank information and the modulation
information related to a four-branch MIMO system for a HSPA system can
be efficiently mapped into a bit pattern of 5 bits.
As illustrated in figure 3, the step (S2) of combining the rank information and
the modulation information related to the four-branch MIMO system into a bit
pattern may comprise the step (S2-1) of mapping the rank information and
the modulation information into a bit pattern according to a bit mapping
table. Table 1 below illustrates an example of a bit mapping table:
Bit Pattern RI Modulation-I Modulation-II
00000 1 QPSK NA
00001 1 16QAM NA
00010 1 64 QAM NA
00011 2 QPSK QPSK
00100 2 QPSK 16QAM
00101 2 QPSK 64QAM
00110 2 16QAM QPSK
00111 2 16QAM 16QAM
01000 2 16QAM 64QAM
01001 2 64QAM QPSK
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Bit Pattern RI Modulation-I Modulation-II
01010 2 64QAM 16QAM
01011 2 64QAM 64QAM
01100 3 QPSK QPSK
01101 3 QPSK 16QAM
01110 3 QPSK 64QAM
01111 3 16QAM QPSK
10000 3 16QAM 16QAM
10001 3 16QAM 64QAM
10010 3 64QAM QPSK
10011 3 64QAM 16QAM
10100 3 64QAM 64QAM
10101 4 QPSK QPSK
10110 4 QPSK 16QAM
10111 4 QPSK 64QAM
11000 4 16QAM QPSK
11001 4 16QAM 16QAM
11010 4 16QAM 64QAM
11011 4 64QAM QPSK
11100 4 64QAM 16QAM
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Bit Pattern RI Modulation-I Modulation-II
11101 4 64QAM 64QAM
11110 NA NA NA
11111 NA NA NA
where RI denotes ‘Rank Information’, QPSK denotes ‘Quadrature Phase
Shift Keying’, QAM denotes ‘Quadrature Amplitude Modulation’, NA denotes
‘Not Applicable’, and Modulation-I and Modulation-II denotes modulation for
different transport blocks.
In other words, the rank information and the modulation information are
jointly coded according to the bit mapping table.
For example, the rank information and the modulation information can be
determined by the node based on suitable input, determined or
recommended by another node and signaled to the node, determined or
recommended by the UE and signaled to the node or a combination thereof.
In practice, suitable representations of the rank information and modulation
information, e.g. maintained as two information variables or stored in two
information fields, are combined into a common bit pattern. Any suitable
original representations of the rank information and modulation information
are feasible, as long as the rank information and modulation information are
combined into a bit pattern that is finally reported to the UE. In other words,
the rank information and modulation information are jointly represented by
this bit pattern. In a preferred example, the rank information and modulation
information related to the four-branch MIMO system are combined and
reported to the UE in one information field in the control channel.
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In a particular example, especially when more than two transport blocks are
to be simultaneously transmitted for parallel streams, the modulation may be
assigned to pairs of transport blocks. By way of example, with four parallel
streams it is possible to use Modulation-I for transport blocks 1 and 4, and
use Modulation-II for transport blocks 2 and 3. With three parallel streams,
this would mean using Modulation-I for transport block 1, and Modulation-II
for transport blocks 2 and 3. It is possible to use a different ‘pairing’ of the
transport blocks of parallel streams.
Preferably, the rank information and the modulation information are coupled
for each Hybrid Automatic Repeat reQuest, HARQ, process.
Figure 4 is a schematic flow diagram illustrating an example of a method of
receiving and processing information from a node in a HSPA system
according to an embodiment. The method comprises the step of receiving
(S11), in a control channel from the node, information including a bit pattern
representing combined rank information and modulation information related
to a four-branch Multiple Input Multiple Output, MIMO, system. The method
also comprises the step of processing (S12) the received information
including decombining the combined rank information and modulation
information related to said four-branch MIMO system.
In this way, there is provided a solution for receiving and processing the
combined rank information and modulation information related to a four-
branch MIMO system, to enable proper decoding of data to be received on a
data channel associated with the control channel.
Preferably, the control channel is a High Speed Shared Control Channel,
HS-SCCH, in the HSPA system, as previously exemplified.
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The rank information is representative of the number of transport blocks to
be simultaneously transmitted on the data channel associated with the
control channel.
As illustrated in figure 5, the method may also involve preparing decoding of
data based on the processed information. More specifically, in this particular
example, the method also includes the step (S13) of preparing decoding of
data to be received on the data channel associated with the control channel
based on the processed information.
In a preferred example, the bit pattern representing combined rank
information and modulation information related to the four-branch MIMO
system is a bit pattern of 5 bits.
Figure 6 is a schematic diagram illustrating an example of the processing
step according to a particular embodiment. In this example, the step (S12) of
processing the received information comprises the step (S12-1) of mapping
the bit pattern into rank information and modulation information according to
a bit mapping table. Preferably, the bit mapping table illustrated in Table 1
above is used.
On the network side, the bit mapping table is used to map rank information
and modulation information into a bit pattern. On the UE side, the bit
mapping table is used to map the bit pattern into rank information and
modulation information. In other words, the network node combines the rank
information and modulation information into the bit pattern for transmission
to the UE. The UE then decombines the received bit pattern back into rank
information and modulation information to enable decoding of data to be
transmitted on the shared downlink data channel associated with the control
channel.
6739296_4.doc
Figure 7A is a schematic flow diagram illustrating an example of a bit
mapping method for information for a control channel in a HSPA system
according to an embodiment. The method comprises the step of obtaining
(S21) rank information and modulation information related to a four-branch
Multiple Input Multiple Output, MIMO, system. The method also comprises
the step of combining (S22) the rank information and the modulation
information related to the four-branch MIMO system into a bit pattern for the
control channel.
Preferably, the control channel is a High Speed Shared Control Channel,
HS-SCCH in the HSPA system. In a preferred example, the rank information
and the modulation information related to the four-branch MIMO system are
mapped into a bit pattern of 5 bits.
Figure 7B is a schematic flow diagram illustrating an example of the
combining step according to a particular embodiment. For example, the step
(S22) of combining of the rank information and the modulation information
related to the four-branch MIMO system into a bit pattern may comprise the
step (S22-1) of mapping the rank information and the modulation information
into the bit pattern according to a bit mapping table such as the one shown
in Table 1 above.
The resulting bit pattern may then be inserted into the control channel
structure in one information field.
Figure 21 is a schematic flow diagram illustrating an example of a method of
processing information of a control channel in a High Speed Packet Access,
HSPA, system according to an embodiment. The method comprises the step
(S31) of obtaining information from the control channel including a bit pattern
representing combined rank information and modulation information related
to a four-branch Multiple Input Multiple Output, MIMO, system. The method
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also comprises the step (S32) of decombining the combined rank
information and modulation information related to the four-branch MIMO
system by mapping the bit pattern into rank information and modulation
information.
By way of example, the bit mapping table illustrated in Table 1 above may
be used to map the bit pattern into rank information and modulation
information.
Expressed somewhat differently, in order to mitigate at least some of the
drawbacks as discussed in the background section, there is provided in a
first aspect a method for improving performance of downlink data
transmission in a mobile communication system. The method comprises
obtaining information for a control channel, arranging this information and
transmitting the information in the control channel to a UE.
In a second aspect there is provided a method for improving performance of
downlink data transmission in a mobile communication system. The method
comprises receiving information in a control channel, processing this
information and, at least partly depending on outcome of the processing,
preparing for decoding (also including demodulation) of data to be received
in a corresponding downlink data channel.
The control channel can be, e.g. a HS-SCCH in a HSPA system, the
information can comprise rank information and modulation information. The
arranging and processing of the information can comprise combining and
de-combining, respectively, the rank information and the modulation
information. The information can relate to a four-branch MIMO system.
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In further aspects there are provided a node and a UE comprising
processing and communication circuitry configured to perform such
methods.
In other words, examples of a method are proposed that can report control
channel information in a 4-way transmit antenna wireless communication
system. It is to be noted that the four-branch MIMO can be applied to a
single downlink carrier.
This is advantageous, for example, in that it provides an efficient design of
HS-SCCH that minimizes the capacity (throughput) loss. That is, the fact
that such a design requires less number of bits implies less amount of power
for control channel and hence more throughput.
It will be appreciated that the methods described above can be combined
and re-arranged in a variety of ways, and that the methods can be
performed by processing circuitry such as specially configured electronic
circuits, e.g. discrete logic gates interconnected to perform a specialized
function, or application-specific integrated circuits and/or one or more
suitably programmed processors.
Many aspects of the proposed technology are described in terms of
sequences of actions that can be performed by, for example, elements of a
programmable computer system.
The steps, functions, procedures and/or blocks described above may be
implemented in hardware using any conventional technology, such as
discrete circuit or integrated circuit technology, including both general-
purpose electronic circuitry and application-specific circuitry.
Alternatively, at least some of the steps, functions, procedures and/or blocks
described above may be implemented in software for execution by a suitable
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computer or processing device such as a microprocessor, Digital Signal
Processor (DSP) and/or any suitable programmable logic device such as a
Field Programmable Gate Array (FPGA) device and a Programmable Logic
Controller (PLC) device.
It should also be understood that it may be possible to re-use the general
processing capabilities of any device or unit in which the present technology
is implemented, such as a base station, network controller or scheduling
node. It may also be possible to re-use existing software, e.g. by
reprogramming of the existing software or by adding new software
components.
Figure 8 is a schematic block diagram illustrating an example of a node
configured for conveying information to user equipment, UE, in a HSPA
system according to an embodiment. The node 200 basically comprises
communication circuitry 206, processing circuitry 209 and multiple antennas
212 connected to the communication circuitry 206 via a conventional data
path 210. The communication circuitry 206 and the processing circuitry 209
are interconnected by conventional means. The antennas 212 may be
regarded as part of an overall communication circuitry 206, 212.
The processing circuitry 209 is configured to obtain rank information and
modulation information related to a four-branch Multiple Input Multiple
Output, MIMO, system. The rank information and modulation information
may be determined by the node based on suitable input and/or at least
partly signaled from another node or UE to the node 200. The processing
circuitry 209 is also configured to combine the rank information and the
modulation information related to the four-branch MIMO system into a bit
pattern. The communication circuitry 206, 212 is configured to transmit the
combined rank and modulation information related to the four-branch MIMO
system as said bit pattern in a control channel to the UE.
6739296_4.doc
By way of example, the communication circuitry 206, 212 is configured to
transmit the combined rank and modulation information related to the four-
branch MIMO system in a High Speed Shared Control Channel, HS-SCCH.
Preferably, as previously defined, the processing circuitry 209 is configured
to obtain rank information representative of the number of transport blocks to
be simultaneously transmitted on the data channel associated with the
control channel.
The node 200 is preferably configured to combine and report the rank
information and modulation information related to the four-branch MIMO
system to the UE in one information field in the control channel.
In a preferred example, the processing circuitry 209 is configured to map the
rank information and the modulation information related to the four-branch
MIMO system into a bit pattern of 5 bits.
By way of example, the processing circuitry 209 may be configured to map
the rank information and the modulation information related to the four-
branch MIMO system into a bit pattern according to the bit mapping shown
in Table 1.
Figure 9 is a schematic block diagram illustrating an example of a node for
conveying information to user equipment, UE, in a HSPA system according
to a particular embodiment. In this particular example, the processing
circuitry 209 comprises a processor 202 and an associated memory 204
connected to the processor 202. The memory 204 includes software 205 for
performing, when executed by the processor 202, the processing steps
described above for the node side.
6739296_4.doc
Figure 10 is a schematic block diagram illustrating an example of user
equipment, UE, configured for receiving and processing information from a
node in a HSPA system according to an embodiment. The UE 250 basically
comprises communication circuitry 256, processing circuitry 259 and
multiple antennas 262 connected to the communication circuitry 256 via a
conventional data path 260. The communication circuitry 256 and the
processing circuitry 259 are interconnected by conventional means. The
antennas 262 may be regarded as part of an overall communication circuitry
256, 262.
The communication circuitry 256, 262 is configured to receive, in a control
channel from the node, information including a bit pattern representing
combined rank information and modulation information related to a four-
branch Multiple Input Multiple Output, MIMO, system. The processing
circuitry 259 is configured to process the received information including
decombining the combined rank information and modulation information
related to the four-branch MIMO system.
By way of example, the communication circuitry 256, 262 is configured to
receive the information including a bit pattern representing combined rank
information and modulation information in a High Speed Shared Control
Channel, HS-SCCH.
The rank information is representative of the number of transport blocks to
be simultaneously transmitted on the data channel associated with the
control channel.
The processing circuitry 259 is preferably configured to decombine the
combined rank information and modulation information in order to be
prepared for decoding of data to be received on the data channel associated
with the control channel.
6739296_4.doc
In a preferred example, the received bit pattern representing combined rank
information and modulation information related to the four-branch MIMO
system is a bit pattern of 5 bits.
By way of example, the processing circuitry 259 may be configured to map
the bit pattern into rank information and modulation information according to
the bit mapping shown in Table 1.
Figure 11 is a schematic block diagram illustrating an example of user
equipment, UE, for receiving and processing information from a node in a
HSPA system according to a particular embodiment. In this particular
example, the processing circuitry 259 comprises a processor 252 and an
associated memory 254 connected to the processor 252. The memory 254
includes software 255 for performing, when executed by the processor 252,
the processing steps described above for the UE side.
Figure 12 is a schematic block diagram illustrating an example of a bit
mapping device for information for a control channel in a HSPA system
according to an embodiment. The HSPA bit mapping device 300 basically
comprises processing circuitry 309 configured to obtain rank information and
modulation information related to a four-branch Multiple Input Multiple
Output, MIMO, system. The processing circuitry 309 is also configured to
combine the rank information and the modulation information related to the
four-branch MIMO system into a bit pattern for the control channel.
By way of example, the processing circuitry 309 is configured to combine the
rank information and the modulation information related to the four-branch
MIMO system into the bit pattern for a High Speed Shared Control Channel,
HS-SCCH.
6739296_4.doc
Preferably, the processing circuitry 309 is configured to obtain rank
information representative of the number of transport blocks to be
simultaneously transmitted on the data channel associated with the control
channel.
In a preferred example, the processing circuitry 309 is configured to map the
rank information and the modulation information related to the four-branch
MIMO system into a bit pattern of 5 bits.
By way of example, the processing circuitry 309 is configured to map the
rank information and the modulation information related to the four-branch
MIMO system into a bit pattern according to the bit mapping shown in Table
The processing circuitry 309 may comprise one or more Input/Output (I/O)
interfaces for obtaining the rank information and modulation information, and
for outputting the bit pattern.
Figure 13 is a schematic block diagram illustrating an example of a bit
mapping device for information for a control channel in a HSPA system
according to a particular embodiment. In this particular example, the
processing circuitry 309 comprises a processor 302 and an associated
memory 304 connected to the processor 302. The memory 304 includes
software 305 for performing, when executed by the processor 302, the
processing steps for effectuating the bit mapping.
Figure 14 is a schematic block diagram illustrating an example of a node in
which a HSPA bit mapping device of figure 12 or figure 13 is implemented.
Basically, the node 200 comprises communication circuitry 206, 212 for
incoming and outgoing communication and a HSPA bit mapping device 300
connected to the communication circuitry 206.
6739296_4.doc
Figure 22 is a schematic block diagram illustrating an example of a device
for processing information of a control channel in a High Speed Packet
Access, HSPA, system according to an embodiment. The device 400
comprises processing circuitry 409 configured to obtain information from the
control channel including a bit pattern representing combined rank
information and modulation information related to a four-branch Multiple
Input Multiple Output, MIMO, system. The processing circuitry 409 is also
configured to decombine the combined rank information and modulation
information related to the four-branch MIMO system by mapping the bit
pattern into rank information and modulation information.
By way of example, the processing circuitry 409 may be configured to map
the bit pattern into rank information and modulation information according to
the bit mapping shown in Table 1.
The processing circuitry 409 may comprise one or more I/O-interfaces for
obtaining information from the control channel such as the bit pattern and for
outputting the rank information and modulation information.
It may be useful to describe the proposed technology with respect to
particular examples in the overall context of messages exchanged between
NodeB and a user equipment, UE, during typical data call set up in a high
speed downlink packet access, HSDPA, system.
Figure 15A shows an example of the messages exchanged between NodeB
and a user equipment, UE, during typical data call set up in a high speed
downlink packet access, HSDPA, system. From the common pilot channel,
CPICH, UE estimates the channel and computes the channel quality
information and pre-coding channel indicator. This information along with
hybrid automatic repeat request, HARQ, acknowledgement/negative
6739296_4.doc
acknowledgement, ACK/NAK, is reported to NodeB using high speed
dedicated physical control channel, HS-DPCCH. The minimum periodicity of
HS-DPCCH is one subframe (2msec). A NodeB scheduler decides the
parameters including modulation and code rate (transport block size), pre-
coding index and rank information for the data transmission on the high
speed physical downlink shared channel, HS-PDSCH. This information is
sent through the high speed shared control channel, HS-SCCH. After HS-
SCCH, the high speed physical downlink shared channel, HS-PDSCH, is
transmitted.
Due to the scheduled nature of the HS-PDSCH, the control signaling is not
needed all the time for a particular user. For downlink, where the number of
channelization codes is limited, it becomes beneficial to designate only a few
control channels to be shared among the users. A HS-SCCH is assigned to
a user only when the user is scheduled. In order to provide the user with all
the necessary information such as rank, modulation, channelization codes,
the HS-SCCH is staggered with HS-PDSCH as shown in figure 15B, where
the HS-SCCH is sent 2 slots ahead of HS-PDSCH. Through successful
decoding of the UE identification field, the intended user is informed of the
upcoming HS-PDSCH. This user then decodes the rest of the HS-SCCH to
obtain the necessary information and be prepared for the decoding of HS-
PDSCH.
Figure 16 is a functional block diagram that schematically illustrates a node
200 that is configured to operate in a radio access network, such as the
UTRAN 103 in figure 1. In the embodiment of figure 16, the node 200
represents a NodeB, such as any of the NodeBs 104 in figure 1.
The node 200 comprises processing means, memory means and
communication means in the form of a processor 202, a memory 204 and
communication circuitry 206. The node 200 communicates with other nodes
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via a first data path 208 and via a second data path 210. For example, the
first data path 208 can be connected to a RNC and the second data path
210 can be connected to one or more antennas 212. The data paths 208,
210 can be any of uplink and downlink data paths, as the skilled person will
realize.
Figure 17 is a functional block diagram that schematically illustrates a UE
250 that is configured to operate in a radio access network, such as the
UTRAN 103 in figure 1. In the embodiment of figure 17, the UE 250 can be
any of the UEs 106 in figure 1.
The UE 250 comprises processing means, memory means and
communication means in the form of a processor 252, a memory 254 and
radio circuitry 256. The UE 250 communicates with other nodes via a radio
air interface with the use of one or more antennas 262. The UE 250 also
comprises input/output circuitry 258 in the form of, e.g., a display, a keypad,
a microphone, a camera etc.
The methods to be described below can be implemented in the node 200
and the UE 250. In such embodiments, the method actions are realized by
means of software instructions 205, 255 that are stored in the memory 204,
254 and are executable by the processor 202, 252. Such software
instructions 205, 255 can be realized and provided in any suitable way, e.g.
provided via the networks 102, 103 or being installed during manufacturing,
as the skilled person will realize. Moreover, the memory 204, 254, the
processor 202, 252, as well as the communication circuitry 206 and radio
circuitry 256 comprise software and/or firmware that, in addition to being
configured such that it is capable of implementing the methods to be
described, is configured to control the general operation of the node 200 and
the UE 250, respectively, when operating in a cellular mobile communication
system such as the system 100 in figure 1. However, for the purpose of
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avoiding unnecessary detail, no further description will be made in the
present disclosure regarding this general operation.
Turning now to a discussion of HSPA communication between a NodeB and
a UE, such as any of the NodeBs 104, 200 and UEs 106, 250 in figure 1,
including transmission in a HS-SCCH and a HS-PDSCH.
For a two-branch MIMO system, also commonly referred to as dual-stream
MIMO, the HS-SCCH carries information about channelization code set,
CCS, modulation and transport block information etc. Since the UE needs
information about the channelization code set and modulation, pre-coding
for setting up the weights for HS-PDSCH, the HS-SCCH is divided to two
parts (part I and part II).
Part I consists of 12 bits, which conveys information about channelization
code set (7 bits), modulation (3 bits), and PCI (2 bits). Rank information, RI,
is implicitly informed through modulation bits. That is, in summary:
Part I (Total of 12 bits):
channelization code set (7 bits),
modulation and Rank (3 bits),
pre-coding information (2 bits)
Part II consists of 36 bits. Out of which 6 bits for each transport block 4 bits
for HARQ process, 4 bits for redundancy version for the two streams and 16
bits for the identity, ID, of the UE. For single stream transmission, only 28
bits are needed for part II. That is, in summary:
Part II (Total of 28 or 36 bits):
For single stream transmission NodeB conveys 28 bits:
Transport block size (6 bits)
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HARQ process (4 bits),
redundancy version (2 bits),
UE ID (16 bits)
For dual stream transmission NodeB conveys 36 bits:
Transport block size -1 (6 bits)
Transport block size -2 (6 bits)
HARQ process (4 bits),
Redundancy version -1 (2 bits),
Redundancy version -2 (2 bits),
UE ID (16 bits)
Similar to a two-branch MIMO, a four-branch MIMO system HS-SCCH
structure consist of two parts. Since it has been decided to use two code
words, it is not anticipated any change in the part II structure.
For part I structure the following has to be informed:
• CCS (7 bits)
• Rank information – requires 2 bits
• Modulation per each code word (2+2 = 4 bits)
• PCI (4 bits)
Hence in general there is a need for 7+2+2*2+4 = 17 bits in such a direct
approach. It is to be noted that in the direct approach, rank information and
modulation information are reported independently. In the NodeB, the rank
information and modulation information are initially maintained as two
independent information entities, as previously explained.
In a proposed approach, rank information and information about modulation
are coupled for each HARQ process so that the number of reported bits is
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reduced; keeping in mind that the proposed approach is also applicable
when there is no HARQ. An example of this approach is illustrated in a flow
chart in figure 19. An obtaining step 502 comprises obtaining rank
information and information about modulation, a combining step 504
comprises combining the rank information and information about modulation
into a bit pattern and a transmission step 506 comprises transmitting the
combined rank and modulation information in a control channel such as HS-
SCCH.
A corresponding method in a UE is illustrated in the flow chart of figure 20.
The method comprises, in a reception step 602, receiving rank and
modulation information in a control channel such as HS-SCCH. Processing
of this information takes place in a processing step 604 where the received
information is de-combined. Finally, data is then received in a reception step
606 in a corresponding data channel such as HS-PDSCH downlink channel.
In other words, in the proposed approach, a NodeB reports the combined
rank and modulation information to the UE, and instead of reporting rank
information and modulation separately, the rank information and the
modulation reporting are combined into one field so that total number of bits
is reduced. That is, with reference to figure 18:
• CCS (7 bits)
• Rank information +modulation per 2 code words (5 bits)
• PCI (4 bits)
The previously presented Table 1 shows one bit mapping example for such
an approach. In total, 16 bits are needed and the power can be reduced by
up to as much as 0.35 dB in comparison with the direct approach where 17
bits are reported. This will have a considerable effect on user throughput as
well as system throughput in the HSPA system.
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The embodiments described above are merely given as examples, and it
should be understood that the proposed technology is not limited thereto. It
will be understood by those skilled in the art that various modifications,
combinations and changes may be made to the embodiments without
departing from the scope of the present invention. In particular, different part
solutions in the different embodiments can be combined in other
configurations, where technically possible. The scope of the present
invention is, however, defined by the appended claims.
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Claims (25)
1. A method for conveying information from a node to user equipment (UE) in a High Speed Packet Access (HSPA) system, wherein said method 5 comprises the steps of: obtaining rank information and modulation information related to a four-branch Multiple Input Multiple Output (MIMO) system, wherein the rank information indicates a number of transport blocks, from one to four, to be simultaneously transmitted on the data channel associated with a control 10 channel; combining the rank information and the modulation information related to said four-branch MIMO system into a bit pattern of 5 bits; transmitting the combined rank information and modulation information related to said four-branch MIMO system as said bit pattern of 5 15 bits in the control channel to the UE.
2. The method of claim 1, wherein the control channel is a High Speed Shared Control Channel (HS-SCCH) in the HSPA system. 20
3. The method of claim 1 or 2, wherein said rank information and modulation information related to said four-branch MIMO system are combined and reported to the UE in one information field in the control channel. 25
4. The method of any one of the claims 1 to 3, wherein said step of combining the rank information and the modulation information related to said four-branch MIMO system into a bit pattern comprises the step of mapping the rank information and the modulation information into the bit pattern according to the following bit mapping table: 6739296_4.doc Bit Pattern RI Modulation-I Modulation-II 00000 1 QPSK NA 00001 1 16QAM NA 00010 1 64 QAM NA 00011 2 QPSK QPSK 00100 2 QPSK 16QAM 00101 2 QPSK 64QAM 00110 2 16QAM QPSK 00111 2 16QAM 16QAM 01000 2 16QAM 64QAM 01001 2 64QAM QPSK 01010 2 64QAM 16QAM 01011 2 64QAM 64QAM 01100 3 QPSK QPSK 01101 3 QPSK 16QAM 01110 3 QPSK 64QAM 01111 3 16QAM QPSK 10000 3 16QAM 16QAM 10001 3 16QAM 64QAM 10010 3 64QAM QPSK 6739296_4.doc Bit Pattern RI Modulation-I Modulation-II 10011 3 64QAM 16QAM 10100 3 64QAM 64QAM 10101 4 QPSK QPSK 10110 4 QPSK 16QAM 10111 4 QPSK 64QAM 11000 4 16QAM QPSK 11001 4 16QAM 16QAM 11010 4 16QAM 64QAM 11011 4 64QAM QPSK 11100 4 64QAM 16QAM 11101 4 64 QAM 64QAM 11110 NA NA NA 11111 NA NA NA where RI denotes ‘Rank Information’, QPSK denotes ‘Quadrature Phase Shift Keying’, QAM denotes ‘Quadrature Amplitude Modulation’, NA denotes ‘Not Applicable’, and Modulation-I and Modulation-II denotes modulation for 5 different transport blocks.
5. The method of any one of the claims 1 to 4, wherein the rank information and the modulation information are coupled for each Hybrid Automatic Repeat reQuest (HARQ) process. 6739296_4.doc
6. A method of receiving and processing information from a node in a High Speed Packet Access (HSPA) system, wherein said method comprises the steps of: receiving, in a control channel from the node, information including a 5 bit pattern of 5 bits representing combined rank information and modulation information related to a four-branch Multiple Input Multiple Output (MIMO) system, wherein the rank information indicates a number of transport blocks, from one to four, to be simultaneously transmitted on the data channel associated with the control channel; and 10 processing the received information including decombining the combined rank information and modulation information related to said four- branch MIMO system.
7. The method of claim 6, wherein the control channel is a High Speed 15 Shared Control Channel (HS-SCCH) in the HSPA system.
8. The method of claim 6 or 7, further comprising the step of preparing decoding of data to be received on the data channel associated with the control channel based on the processed information.
9. The method of any one of the claims 6 to 8, wherein said step of processing the received information comprises the step of mapping the bit pattern into rank information and modulation information according to the following bit mapping table: Bit Pattern RI Modulation-I Modulation-II 00000 1 QPSK NA 00001 1 16QAM NA 00010 1 64 QAM NA 6739296_4.doc Bit Pattern RI Modulation-I Modulation-II 00011 2 QPSK QPSK 00100 2 QPSK 16QAM 00101 2 QPSK 64QAM 00110 2 16QAM QPSK 00111 2 16QAM 16QAM 01000 2 16QAM 64QAM 01001 2 64QAM QPSK 01010 2 64QAM 16QAM 01011 2 64QAM 64QAM 01100 3 QPSK QPSK 01101 3 QPSK 16QAM 01110 3 QPSK 64QAM 01111 3 16QAM QPSK 10000 3 16QAM 16QAM 10001 3 16QAM 64QAM 10010 3 64QAM QPSK 10011 3 64QAM 16QAM 10100 3 64QAM 64QAM 10101 4 QPSK QPSK 6739296_4.doc Bit Pattern RI Modulation-I Modulation-II 10110 4 QPSK 16QAM 10111 4 QPSK 64QAM 11000 4 16QAM QPSK 11001 4 16QAM 16QAM 11010 4 16QAM 64QAM 11011 4 64QAM QPSK 11100 4 64QAM 16QAM 11101 4 64 QAM 64QAM 11110 NA NA NA 11111 NA NA NA where RI denotes ‘Rank Information’, QPSK denotes ‘Quadrature Phase Shift Keying’, QAM denotes ‘Quadrature Amplitude Modulation’, NA denotes ‘Not Applicable’, and Modulation-I and Modulation-II denotes modulation for 5 different transport blocks.
10. A bit mapping method for information for a control channel in a High Speed Packet Access (HSPA) system, wherein said method comprises the steps of: 10 obtaining rank information and modulation information related to a four-branch Multiple Input Multiple Output (MIMO) system, wherein the rank information indicates a number of transport blocks, from one to four, to be simultaneously transmitted on the data channel associated with the control channel; and 6739296_4.doc combining the rank information and the modulation information related to said four-branch MIMO system into a bit pattern of 5 bits for said control channel. 5
11. The method of claim 10, wherein the control channel is a High Speed Shared Control Channel (HS-SCCH) in the HSPA system.
12. The method of claim 10 or 11, wherein said step of combining the rank information and the modulation information related to said four-branch 10 MIMO system into a bit pattern comprises the step of mapping the rank information and the modulation information into the bit pattern according to the following bit mapping table: Bit Pattern RI Modulation-I Modulation-II 00000 1 QPSK NA 00001 1 16QAM NA 00010 1 64 QAM NA 00011 2 QPSK QPSK 00100 2 QPSK 16QAM 00101 2 QPSK 64QAM 00110 2 16QAM QPSK 00111 2 16QAM 16QAM 01000 2 16QAM 64QAM 01001 2 64QAM QPSK 6739296_4.doc Bit Pattern RI Modulation-I Modulation-II 01010 2 64QAM 16QAM 01011 2 64QAM 64QAM 01100 3 QPSK QPSK 01101 3 QPSK 16QAM 01110 3 QPSK 64QAM 01111 3 16QAM QPSK 10000 3 16QAM 16QAM 10001 3 16QAM 64QAM 10010 3 64QAM QPSK 10011 3 64QAM 16QAM 10100 3 64QAM 64QAM 10101 4 QPSK QPSK 10110 4 QPSK 16QAM 10111 4 QPSK 64QAM 11000 4 16QAM QPSK 11001 4 16QAM 16QAM 11010 4 16QAM 64QAM 11011 4 64QAM QPSK 11100 4 64QAM 16QAM 6739296_4.doc Bit Pattern RI Modulation-I Modulation-II 11101 4 64 QAM 64QAM 11110 NA NA NA 11111 NA NA NA where RI denotes ‘Rank Information’, QPSK denotes ‘Quadrature Phase Shift Keying’, QAM denotes ‘Quadrature Amplitude Modulation’, NA denotes ‘Not Applicable’, and Modulation-I and Modulation-II denotes modulation for 5 different transport blocks.
13. A node configured for conveying information to user equipment (UE) in a High Speed Packet Access (HSPA) system, wherein said node comprises: 10 processing circuitry configured to obtain rank information and modulation information related to a four-branch Multiple Input Multiple Output (MIMO) system, wherein the rank information indicates a number of transport blocks, from one to four, to be simultaneously transmitted on the data channel associated with a control channel; 15 wherein said processing circuitry is also configured to combine the rank information and the modulation information related to said four-branch MIMO system into a bit pattern of 5 bits; and communication circuitry configured to transmit the combined rank and modulation information related to said four-branch MIMO system as said 20 bit pattern of 5 bits in the control channel to the UE.
14. The node of claim 13, wherein the control channel is a High Speed Shared Control Channel (HS-SCCH) in the HSPA system. 6739296_4.doc
15. The node of claim 13 or 14, wherein said node is configured to combine and report said rank information and modulation information related to said four-branch MIMO system to the UE in one information field in the control channel.
16. The node of any one of the claims 13 to 15, wherein said processing circuitry is configured to map the rank information and the modulation information related to said four-branch MIMO system into a bit pattern according to the following bit mapping table: Bit Pattern RI Modulation-I Modulation-II 00000 1 QPSK NA 00001 1 16QAM NA 00010 1 64 QAM NA 00011 2 QPSK QPSK 00100 2 QPSK 16QAM 00101 2 QPSK 64QAM 00110 2 16QAM QPSK 00111 2 16QAM 16QAM 01000 2 16QAM 64QAM 01001 2 64QAM QPSK 01010 2 64QAM 16QAM 01011 2 64QAM 64QAM 6739296_4.doc Bit Pattern RI Modulation-I Modulation-II 01100 3 QPSK QPSK 01101 3 QPSK 16QAM 01110 3 QPSK 64QAM 01111 3 16QAM QPSK 10000 3 16QAM 16QAM 10001 3 16QAM 64QAM 10010 3 64QAM QPSK 10011 3 64QAM 16QAM 10100 3 64QAM 64QAM 10101 4 QPSK QPSK 10110 4 QPSK 16QAM 10111 4 QPSK 64QAM 11000 4 16QAM QPSK 11001 4 16QAM 16QAM 11010 4 16QAM 64QAM 11011 4 64QAM QPSK 11100 4 64QAM 16QAM 11101 4 64 QAM 64QAM 11110 NA NA NA 6739296_4.doc Bit Pattern RI Modulation-I Modulation-II 11111 NA NA NA where RI denotes ‘Rank Information’, QPSK denotes ‘Quadrature Phase Shift Keying’, QAM denotes ‘Quadrature Amplitude Modulation’, NA denotes ‘Not Applicable’, and Modulation-I and Modulation-II denotes modulation for 5 different transport blocks.
17. The node of any one of the claims 13 to 16, wherein said node is a NodeB. 10
18. User equipment (UE) configured for receiving and processing information from a node in a High Speed Packet Access (HSPA) system, wherein said UE comprises: communication circuitry configured to receive, in a control channel from the node, information including a bit pattern of 5 bits representing 15 combined rank information and modulation information related to a four- branch Multiple Input Multiple Output (MIMO) system, wherein the rank information indicates a number of transport blocks, from one to four, to be simultaneously transmitted on the data channel associated with the control channel; and 20 processing circuitry configured to process the received information including decombining the combined rank information and modulation information related to said four-branch MIMO system.
19. The UE of claim 18, wherein said communication circuitry is 25 configured to receive said information in a High Speed Shared Control Channel (HS-SCCH). 6739296_4.doc
20. The UE of claim 18 or 19, wherein said processing circuitry is configured to decombine said combined rank information and modulation information to be prepared for decoding of data to be received on the data channel associated with the control channel.
21. The UE of any one of the claims 18 to 20, wherein said processing circuitry is configured to map the bit pattern into rank information and modulation information according to the following bit mapping table: Bit Pattern RI Modulation-I Modulation-II 00000 1 QPSK NA 00001 1 16QAM NA 00010 1 64 QAM NA 00011 2 QPSK QPSK 00100 2 QPSK 16QAM 00101 2 QPSK 64QAM 00110 2 16QAM QPSK 00111 2 16QAM 16QAM 01000 2 16QAM 64QAM 01001 2 64QAM QPSK 01010 2 64QAM 16QAM 01011 2 64QAM 64QAM 01100 3 QPSK QPSK 6739296_4.doc Bit Pattern RI Modulation-I Modulation-II 01101 3 QPSK 16QAM 01110 3 QPSK 64QAM 01111 3 16QAM QPSK 10000 3 16QAM 16QAM 10001 3 16QAM 64QAM 10010 3 64QAM QPSK 10011 3 64QAM 16QAM 10100 3 64QAM 64QAM 10101 4 QPSK QPSK 10110 4 QPSK 16QAM 10111 4 QPSK 64QAM 11000 4 16QAM QPSK 11001 4 16QAM 16QAM 11010 4 16QAM 64QAM 11011 4 64QAM QPSK 11100 4 64QAM 16QAM 11101 4 64 QAM 64QAM 11110 NA NA NA 11111 NA NA NA 6739296_4.doc where RI denotes ‘Rank Information’, QPSK denotes ‘Quadrature Phase Shift Keying’, QAM denotes ‘Quadrature Amplitude Modulation’, NA denotes ‘Not Applicable’, and Modulation-I and Modulation-II denotes modulation for 5 different transport blocks.
22. A bit mapping device for information for a control channel in a High Speed Packet Access (HSPA) system, wherein said device comprises: processing circuitry configured to obtain rank information and 10 modulation information related to a four-branch Multiple Input Multiple Output (MIMO) system, wherein the rank information indicates a number of transport blocks, from one to four, to be simultaneously transmitted on the data channel associated with the control channel; and wherein said processing circuitry is also configured to combine the 15 rank information and the modulation information related to said four-branch MIMO system into a bit pattern of 5 bits for said control channel.
23. The device of claim 22, wherein said processing circuitry is configured to combine the rank information and the modulation information 20 related to said four-branch MIMO system into said bit pattern for a High Speed Shared Control Channel (HS-SCCH).
24. The device of claim 22 or 23, wherein said processing circuitry is configured to map the rank information and the modulation information 25 related to said four-branch MIMO system into a bit pattern according to the following bit mapping table: Bit Pattern RI Modulation-I Modulation-II 00000 1 QPSK NA 6739296_4.doc Bit Pattern RI Modulation-I Modulation-II 00001 1 16QAM NA 00010 1 64 QAM NA 00011 2 QPSK QPSK 00100 2 QPSK 16QAM 00101 2 QPSK 64QAM 00110 2 16QAM QPSK 00111 2 16QAM 16QAM 01000 2 16QAM 64QAM 01001 2 64QAM QPSK 01010 2 64QAM 16QAM 01011 2 64QAM 64QAM 01100 3 QPSK QPSK 01101 3 QPSK 16QAM 01110 3 QPSK 64QAM 01111 3 16QAM QPSK 10000 3 16QAM 16QAM 10001 3 16QAM 64QAM 10010 3 64QAM QPSK 10011 3 64QAM 16QAM 6739296_4.doc Bit Pattern RI Modulation-I Modulation-II 10100 3 64QAM 64QAM 10101 4 QPSK QPSK 10110 4 QPSK 16QAM 10111 4 QPSK 64QAM 11000 4 16QAM QPSK 11001 4 16QAM 16QAM 11010 4 16QAM 64QAM 11011 4 64QAM QPSK 11100 4 64QAM 16QAM 11101 4 64 QAM 64QAM 11110 NA NA NA 11111 NA NA NA where RI denotes ‘Rank Information’, QPSK denotes ‘Quadrature Phase Shift Keying’, QAM denotes ‘Quadrature Amplitude Modulation’, NA denotes ‘Not Applicable’, and Modulation-I and Modulation-II denotes modulation for 5 different transport blocks.
25. A method of processing information of a control channel in a High Speed Packet Access (HSPA) system, wherein said method comprises the steps of: 10 obtaining information from said control channel including a bit pattern of 5 bits representing combined rank information and modulation information 6739296_4.doc
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US201261644515P | 2012-05-09 | 2012-05-09 | |
US61/644,515 | 2012-05-09 | ||
PCT/SE2012/051328 WO2013169163A1 (en) | 2012-05-09 | 2012-11-29 | Improved control channel in a high-speed packet access system |
Publications (2)
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NZ701750A NZ701750A (en) | 2016-07-29 |
NZ701750B2 true NZ701750B2 (en) | 2016-11-01 |
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