NZ245344A - Bus control logic overrides memory arbitration control logic for dual bus architecture computer - Google Patents

Bus control logic overrides memory arbitration control logic for dual bus architecture computer

Info

Publication number
NZ245344A
NZ245344A NZ245344A NZ24534492A NZ245344A NZ 245344 A NZ245344 A NZ 245344A NZ 245344 A NZ245344 A NZ 245344A NZ 24534492 A NZ24534492 A NZ 24534492A NZ 245344 A NZ245344 A NZ 245344A
Authority
NZ
New Zealand
Prior art keywords
bus
memory
input
system memory
data
Prior art date
Application number
NZ245344A
Other languages
English (en)
Inventor
Nader Amini
Bechara Fouad Boury
Sherwood Brannon
Richard Louis Horne
Terrence Joseph Lohman
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of NZ245344A publication Critical patent/NZ245344A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
NZ245344A 1992-01-02 1992-12-02 Bus control logic overrides memory arbitration control logic for dual bus architecture computer NZ245344A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US81599292A 1992-01-02 1992-01-02

Publications (1)

Publication Number Publication Date
NZ245344A true NZ245344A (en) 1995-09-26

Family

ID=25219387

Family Applications (1)

Application Number Title Priority Date Filing Date
NZ245344A NZ245344A (en) 1992-01-02 1992-12-02 Bus control logic overrides memory arbitration control logic for dual bus architecture computer

Country Status (10)

Country Link
US (1) US5544346A (zh)
EP (1) EP0550224A1 (zh)
JP (1) JPH05242014A (zh)
KR (1) KR950014183B1 (zh)
CN (1) CN1029168C (zh)
AU (1) AU663536B2 (zh)
CA (1) CA2080608A1 (zh)
NZ (1) NZ245344A (zh)
SG (1) SG44430A1 (zh)
TW (1) TW318224B (zh)

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US5815675A (en) * 1996-06-13 1998-09-29 Vlsi Technology, Inc. Method and apparatus for direct access to main memory by an I/O bus
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US7526691B1 (en) 2003-10-15 2009-04-28 Marvell International Ltd. System and method for using TAP controllers
US7139150B2 (en) 2004-02-10 2006-11-21 Marvell International Ltd. Method and system for head position control in embedded disk drive controllers
US7120084B2 (en) 2004-06-14 2006-10-10 Marvell International Ltd. Integrated memory controller
US8166217B2 (en) 2004-06-28 2012-04-24 Marvell International Ltd. System and method for reading and writing data using storage controllers
US9201599B2 (en) 2004-07-19 2015-12-01 Marvell International Ltd. System and method for transmitting data in storage controllers
US8032674B2 (en) 2004-07-19 2011-10-04 Marvell International Ltd. System and method for controlling buffer memory overflow and underflow conditions in storage controllers
US7757009B2 (en) 2004-07-19 2010-07-13 Marvell International Ltd. Storage controllers with dynamic WWN storage modules and methods for managing data and connections between a host and a storage device
US7386661B2 (en) 2004-10-13 2008-06-10 Marvell International Ltd. Power save module for storage controllers
US7240267B2 (en) 2004-11-08 2007-07-03 Marvell International Ltd. System and method for conducting BIST operations
US7802026B2 (en) 2004-11-15 2010-09-21 Marvell International Ltd. Method and system for processing frames in storage controllers
US7609468B2 (en) 2005-04-06 2009-10-27 Marvell International Ltd. Method and system for read gate timing control for storage controllers
US9838784B2 (en) 2009-12-02 2017-12-05 Knowles Electronics, Llc Directional audio capture
US8798290B1 (en) 2010-04-21 2014-08-05 Audience, Inc. Systems and methods for adaptive signal equalization
US20140082307A1 (en) * 2012-09-17 2014-03-20 Mobileye Technologies Limited System and method to arbitrate access to memory
US9536540B2 (en) 2013-07-19 2017-01-03 Knowles Electronics, Llc Speech signal separation and synthesis based on auditory scene analysis and speech modeling
US9170942B1 (en) * 2013-12-31 2015-10-27 Emc Corporation System, apparatus, and method of automatic data padding
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Also Published As

Publication number Publication date
EP0550224A1 (en) 1993-07-07
JPH05242014A (ja) 1993-09-21
SG44430A1 (en) 1997-12-19
CN1029168C (zh) 1995-06-28
AU2979292A (en) 1993-07-08
CA2080608A1 (en) 1993-07-03
US5544346A (en) 1996-08-06
CN1074050A (zh) 1993-07-07
TW318224B (zh) 1997-10-21
KR950014183B1 (ko) 1995-11-22
AU663536B2 (en) 1995-10-12
KR930016873A (ko) 1993-08-30

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