NZ242386A

NZ242386A - Digital multiplexer/demultiplexer

Info

Publication number: NZ242386A
Application number: NZ24238692A
Authority: NZ
Inventors: Bruce Francis Orr; Carl Peter Renneberg
Original assignee: Alcatel Australia
Priority date: 1991-04-16
Filing date: 1992-04-16
Publication date: 1994-07-26

Description

<div class="application article clearfix" id="description"> 24 2 3 8 6 i ^ V - CO t • ! jJ i O tO V.' . : Chns: ! SS>;. : Jh-U- 9Z, i P*=> ;Pub;ica'.:on Do's: .. .2.6.JUI.BM ;»0. Joc.u!, P'c: /3S^. ;TRUE COPY ;NEW ZEALAND PATENTS ACT 1953 COMPLETE SPECIFICATION ;■fAJ ;\z ;^23 APR 1992 ^ ;'DISTRIBUTED MULTIPLEXER FOR DIGITAL COMMUNICATION SYSTEM" ;WE, ALCATEL AUSTRALIA LIMITED, A Company of the State of New South Wales, of 280 Botany Road, Alexandria, New South Wales, 2015, Australia, hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: ;l ;This invention relates to multiplexing/demultiplexing techniques for signals in digital communication systems, particularly telecommunication systems. ;In digital communication systems a plurality of signals may be combined or multiplexed into a higher rate aggregate signal for transmission from a transmit ter-5 minal to a receive terminal. At the receive terminal the multiplexed signals are separated or demultiplexed by a compatible demultiplexer into the original separate signals. ;One of the most common multiplexing/demultiplexing techniques is known as time-division multiplexing (TDM). In TDM, information from different input signals 10 is placed into different time slots in a defined frame structure. ;In typical network applications of TDM it is often necessary to implement multiplexers/demultiplexers which are sufficiently flexible to, among other things, support a variety of channel combinations; also, it is often required to provide a number of separate multiplexers in one equipment shelf. A typical multiplexer is 15 partitioned into channel units which provide interfaces for information signals to be multiplexed, and a common unit which contains a multiplexer/demultiplexer and aggregate signal interface. Channel units and common units may typically be realised as circuit cards which are fitted into a shelf in numbers to suit individual multiplexing requirements. ;20 A disadvantage of the above approach is the limited flexibility introduced by the need for a mixture of channel units and common units in an equipment shelf. The shelf can typically be wired to support multiplexers with a fixed maximum number of channels or a limited number of separate multiplexers in a shared shelf. The known approach becomes particularly restrictive where it is desired to implement 25 multiplexers that support a combination of channel types, for example, data, voice and other service channels. ;An object of the present invention is to provide a method and arrangement in which multiplexing and demultiplexing functions are realised in a distributed way without using a common multiplexer/demultiplexer unit. ;According to the invention there is provided a method of 5 multiplexing/demultiplexing signals in a digital communication system, said method comprising the steps of providing a plurality of channel means coupled to a common bus, each of said channel means comprising a signal transmit section and a signal receive section, provide each signal receive section with receive frame alignment means for direct demultiplexing of received channel information, provide each signal 10 transmit section with means to generate a transmit frame alignment signal, and select one signal transmit section to function as a master synchronisation source upon the generation of said transmit frame alignment signal. ;A method according to the invention eliminates the need for separate multiplexer/demultiplexer units and allows flexibility in the number of 15 multiplexer/demultiplexer groups in a shared shelf; in the assignment of channels to the groups; in the assignment of time slots or phases of a time slot to channels; in the physical positioning of channels; and in the bit rates/bandwidth/information capacity of low speed channels. ;In order that the invention may be readily carried into effect, embodiments 20 thereof will now be described in relation to the accompanying drawings, in which: ;Figure I shows a block diagram of a channel interface providing the distributed multiplexing function of the present invention. ;Figure 2 is a diagram showing the relationship between time slots and channels in a first order multiplexer application of the present invention. ;25 Figure 3 is a diagram showing the relationship between time slots and channels in a zero order multiplexer application of the present invention. ;Figure 4 shows another embodiment of the channel interface shown in Figure ;1. ;Referring to Figure 1, channel interface 1 is partitioned into a transmit section 2 and a receive section 3. A channel card or unit (not shown) would typically contain a plurality of such channel interfaces. The transmit section 2 outputs information onto transmit bus 4 via a transmit time slot acccss arrangement 5. A synchronisation source 6 for the transmit time slot acccss arrangement may be selected from a local frame synchronisation source 7 (master sync mode), an external frame sync source (common sync mode) from the frame sync bus 8, or a synchronisation source 9 derived from the transmit bus (slave sync mode). In the case of slave mode operation a frame alignment arrangement 10 is used to sense the frame alignment pattern of the transmit bus 4 so that the transmit time slot access arrangement 5 may output into the correct time slot. The transmit channel input 11 is processed by transmit channel interface 12 and fed to transmit buffer store 13. A frame alignment word generator 14 produces a frame alignment pattern which is inserted into specified time slots by the transmit time slot access arrangement 5 if the transmit section 2 is configured as a master. In common sync mode one channel must still be configured as the master. ;In the receive section 3 a reccive frame alignment arrangement 15 produces a receive frame synchronisation signal 16 enabling the receive time slot access arrangement 17 to access a specified time slot of receive bus 24. Information from the receive time slot access arrangement 17 is passed to receive buffer store 19 and then output-ted by receive channel interface 23. ;For the selection of programmable parameters, eg. synchronisation mode, a time slot may be selected via an external control interface 21 which may be connected to a microprocessor. Alternatively, the control interface may be connected to the time slot access arrangements 5, 17 with the control information carried in ;2*3 APR 1992 .A o time slot. In the case of the time slot access arrangements 5 and 17, the control interface may select the time slot(s) to be accessed. These time slots are located with reference to the frame synchronising signals 6 and 16 respectively. The channel input 11 and output 22 signals may be digital or analogue at vari-5 ous bit rates or bandwidths. The channel interfaces 12 and 23 convert the signals to/from a digital form respectively. The buffer 13 and 19 provide temporary storage of the digital information. The invention may be applied to a first order multiplexing application where different signals are multiplexed into different time slots on a bus, eg. time slots 1 -10 31 and the frame alignment pattern is in one time slot, eg. time slot 0. An example of such a multiplexing system is in CCITT specifications G.732 and G.737. Figure 2 shows an example of a first order multiplexing application. Channel 1 is the master and generates the frame alignment pattern (F bits) into time slot 0. Channel 1 also outputs data (D bits) into time slot 1. Channel 2 is a slave and in this example is 15 programmed to output data into time slot 5. Alternately the invention may be applied to zero order (sub-rate) multiplexing wherein different signals are multiplexed into the same time slot in different frames (phases). In this case the sub-rate multiframe alignment signal may be contained in one bit of each time slot with data and/or control information in the remaining bits. 20 An example of such a multiplexing system is in CCITT specification X.50. Figure 3 shows an example of a zero order multiplexing application according to CCITT X50. Each time slot contains an eight bit envelope consisting of a framing bit (F bit), six data bits (D bits) and a supervision bit (S bit). Channel 1 is the master and generates the frame alignment pattern in the first bit (F bit) of a specified time slot (TSn). TSn 25 appears regularly on the bus and the master outputs successive bits of the frame alignment pattern into the first bit of successivc time slots. In the case of X50 division <V.. :r "n fes APR 1992 ~ 24 3 the frame pattern is 20 bits long and repeats after 20 envelopes. In this example channel 1 outputs data and supervision into phase 0 and channel 2 outputs data and supervision into phase 7. The invention may also be applied to multiplexing at more than one level. As 5 an example, a combined zero and first order distributed multiplexer may be implemented by providing separate frame alignment circuits 10, 15 for each level and providing the time slot access arrangements 5 and 17 with both zero and first order frame ^synchronising signals. The control bus would then specify the zero order time slot (phase) and first order time slot (phase) and first order time slot to the time slot access 10 circuit. The master for each level of multiplexing need not be in the same channel interface and the total function will normally be distributed. The invention can work with different framing methods at each level of multiplexing. Referring to Figure 4, the buses 25, 26 carry a time-division multiplexed signal at 2.048 Mbit/s and contain 32 time slots each with an information capacity of 64 15 kbit/s. In this embodiment conventional (centralised) first order multiplexing using a common multiplexer unit 27 is used to multiplex 64 kbit/s channels to CCITT G732 or G737 format. In this case the common multiplexer adds the first order frame alignment pattern in the transmit direction and locks onto the first order frame alignment pattern in the receive direction. A first order frame synchronising pulse is 20 outputted onto bus 28 by the common multiplexer unit. This pulse is used by the various channel units on the bus to locate time slots. Each 64kbit/s time slot may be used to carry a number of low speed signals multiplexed for example as in CCITT recommendation X.50. In this application the invention enables X50 multiplexed aggregate signals to be built up directly on given 25 64 kbit/s time slots of the buses 25, 26. 6 24 2 The first order frame synchronising pulse from frame synchronising bus 28 is fed to the time slot access arrangements 5, 17. The time slot access arrangements pass first order time slot specifying pulses 29, 30 to the zero order frame alignment arrangements 10, 15. The zero order frame sync signals 6, 16 are fed back, to the time 5 slot access arrangements so that a specified zero order phase within a first order time slot may be accessed. The control bus 21 may be used to program the time.slot access arrangements for the required first order time slot and zero order phase. One low speed channel in each X50 multiplex group is assigned the master function by selecting the master sync source 7 and generates the X50 frame 10 synchronisation pattern in the specified 64 kbit/s time slot. The other channel units multiplexing to the same X50 aggregate time slot may be configured as slaves by selecting the slave sync source 10. If the master channel fails or is removed, a slave channel may be automatically re-configured to take over the master function. In this embodiment the channel interfaces 11, 22 may be, for example, CCITT 15 X2I or X21bis type. Alternatively the interface may be diphase (Manchester) coded to a 2-wire or 4-wire interface for longer distance transmission. In the case of 2-wire transmission the transmit and receive interfaces are combined using a hybrid coupler arrangement. The channel interfaces 12, 23 convert between the required channel signal and the internal digital form. 20 In the above arrangement X50 data channel units may share common buses with PCM voice channel units etc. and may be fitted in unrestricted combinations. One X50 channel only is shown in Figure 4 for clarity. This embodiment of the invention provides distributed X50 sub-rate (zero order) multiplexing to 64 kbit/s time slots without the use of separate sub-rate multiplexer units. This arrangement offers sub-25 stantial advantages in terms of space savings, cost and flexibility. While the present invention has been described with regard to many particulars, it is understood that equivalents may be readily substituted without departing from the scope of the invention. 10 15 20 </div>

Claims

<div class="application article clearfix printTableText" id="claims"> What we claim is:-

1. A method of multiplexing/demultiplexing signals in a digital communication system, said method comprising the steps of providing a plurality of channel means coupled to a common bus, each of said channel means comprising a signal transmit section and a signal receive section, providing each signal receive section with receive frame alignment means for direct demultiplexing of received channel information, providing each signal transmit section with means to generate a transmit frame alignment signal, and selecting one signal transmit section to function as a master synchronisation source upon the generation of said transmit frame alignment signal.

2. An arrangement for multiplexing/demultiplexing signals in a digital communication system, said arrangement comprising a plurality of channel means coupled to a common bus, each said channel means comprising a signal transmit section and a signal receive section, each signal receive section including receive frame alignment means for direct demultiplexing of received channel information, means in each signal transmit section to generate a transmit frame alignment signal, one signal transmit section being selected to function as a master synchronisation source upon the generation of said transmit frame alignment signal.

3. An arrangement as claimed in claim 2, wherein each said signal transmit section includes transmit time slot access means via which information is coupled to a transmit bus, and each signal receive section includes receive time slot access means via which information is received via a receive bus.

4. An arrangement as claimed in claim 3, wherein said transmit time slot access means is synchronised by a synchronisation source selected from a local frame synchronisation source, an external frame synchronisation source, or a synchronisation source dervied from said transmit bus. ■y t ^ *• , /m 'j v _ A? ' „ i,, f V ^ -3 JUN 1994 ; & ,: I 10 15 9 20

5. An arrangement as claimed in claim 4, including a frame alignment arrangement for sensing the frame alignment pattern of said transmit bus when the said synchronisation source is derived therefrom.

6. An arrangement as claimed in any one of claims 1 to 5, adapted for first order multiplexing in which different signals are multiplexed into different time slots, the frame alignment pattern being in one time slot.

7. An arrangement as claimed in claim 6, wherein said first order multiplexing is in accordance with CCITT specifications G.732 and G.737.

8. An arrangement as claimed in any one of claims 1 to 5, adapted for zero order multiplexing wherein different signals are multiplexed into the same time slot in different frames.

9. An arrangement as claimed in claim 8, wherein said zero order multiplexing is in accordance with CCITT specifications X50.

10. An arrangement as claimed in claim 9, wherein one low speed channel functions as said master synchronisation source.

11. An arrangement for multiplexing/demultiplexing signals in a digital communication system, substantially as herein described with reference to Figures 1 - 4 of the accompanying drawings. ALCATEL AUSTRALIA LIMITED ^ B. O'Connor Authorized Agent P5/1/1703 </div>