NZ235800A - Extended addressing circuitry and computer adapter card. (51) g06f12/06; - Google Patents

Description

235 800 Priority Date(s): . ....

Cwnpiate Specification Filedi^r.Qc&l^D Class: &9Mi7.&j.Q<P„ &?k>.VX^DQ Publication Date: ..F.^ P.

P.O. Journal, No: .. (SHTl NEW ZEALAND PATENTS ACT, 1953 No.: Date: NEW ZEALAND PATENT OFFICE 2 4 OCT 1990 RECEIVED COMPLETE SPECIFICATION EXTENDED ADDRESSING USING SUB-ADDRESSED SEGMENT REGISTERS ^YWe. INTERNATIONAL BUSINESS MACHINES CORPORATION, a corporation of New York, United States of America, of Armonk, New York 10504, United States of America hereby declare the invention for which XI we PraY that a patent may be granted to rja^/us, and the method by which it is to be performed, to be particularly described in and by the following statement:- (followed by page la) 235 800 BACKGROUND of the INVENTION This invention pertains to computers and, more particularly, to an extended addressing circuit that permits segments of memory associated with a second address/data bus to be accessed from a first address/data bus. -la- 235800 I/O adapter cards for certain prior art personal computer systems have included a plurality of registers referred to as Programmable Option Select (POS) registers. Each adapter card plugged into the main processor bus is connected to a unique Card Setup line on the main bus, and the POS registers can only be accessed when the Card Setup line for that adapter is active. The number of POS registers is limited, typically to eight (8) , and it would be desirable if this number could be increased. Furthermore, when the adapter card is intelligent, i.e., when it includes its own processor, address/data bus and associated memory, it would be advantageous if some of the memory associated with the adapter card bus could be accessed'through the POS registers.

Accordingly, the invention described below uses extended addressing, or. sub-addressing, to permit a large segment of the memory associated with the adapter card to be accessed through the POS registers. This.invention also permits this large segment to be placed anywhere,.within the address space associated with the adapter card bus, and also provides for auto-incrementing, such that sequential addresses within this segment of memory can be easily and quickly accessed.

SUMMARY of the INVENTION Briefly, the invention is an extended addressing circuit for use with first and second address/data buses having, respectively, first and second addressable memory spaces associated therewith. The extended addressing circuit includes first and second registers wherein the first register is capable of storing values of data that lie within first, second and third non-overlapping ranges. Included is a means for accessing the second register from the first bus in response to a first address signal on the first bus. 235 80 The means for accessing the second register is enabled in response to a first predetermined value of data stored in the first register. This first predetermined value lies within the first range of values. Data may be transferred between the second register and the first bus when the second register is so accessed. Also included is a means for selecting a first segment of the second memory space. The base address of the first segment corresponds to the data stored in the second register. Furthermore, a means for accessing a selected address of the first 10 segment of the second memory space in response to the first address signal on the" first bus is also provided. The address of the selected address within the first segment corresponds to the data stored in the first register. The means for accessing the selected address of the first segment is enabled in response to a value of 15 data stored in the first register that lies within the second range, such that data may be transferred between the selected address and the first bus when the selected address is so accessed.

In another embodiment, the invention is an adapter card circuit having extended addressing capability. The adapter card circuit is for use in a computer having a first address/data bus which has a first memory space associated therewith. The adapter card circuit includes a second address/data bus which has a,second memory space associated therewith. A memory is coupled to the second bus and the memory is addressable within the second memory space. Means for transferring data between the first and second buses is coupled to the data bus of the second bus. Included are first and second registers wherein the first register is capable of storing values of data that lie within first, second and third non-overlapping ranges. Also included is a means for accessing the 3 0 second register from the first bus in response to a first address signal on the first bus. The means for accessing the second register is enabled in response to a first predetermined value of 3 235 BOO data stored in the first register. This first predetermined value lies within the first range of values. Data may be transferred between the second register and the first bus when the second register is so accessed. Also included is a means for selecting a first segment of the second memory. The base address of the first segment corresponds to the data stored in the second register. Furthermore, a means for accessing a selected address of the first segment of the second memory in response to the first address signal on the first bus is also provided. The" address of 10 the selected address within the first segment corresponds to the data stored in the first register. The means for accessing the selected address of the first segment is enabled in response to a value of data stored in the first register that lies within the second range, such that data may be transferred between the 15 selected address and the first bus when the selected address is so accessed. ' BRIEF DESCRIPTION of the DRAWINGS Figs. 1A and' IB are a schematic diagram of the current invention.

Fig. 2 is a schematic diagram of the POS7 and POS6 registers of Fig. 1A.

DESCRIPTION of the PREFERRED EMBODIMENTS Referring to Figs. 1A and IB, a first address/data bus 102 includes an address bus 104 and a data bus 106. The address bus 25 also includes a line 108 called "Card Setup". First bus 102 is adapted to receive adapter cards 110, which can be plugged into first bus 102. Although only one Card Setup line 108 is 4 235800 illustrated in the figure, the first bus actually includes a separate Card Setup line for each adapter card plugged into the first bus. First bus 102 is typically the main bus of a personal computer. A first memory 112 is coupled to the bus and is addressable within the "memory space" 114 of the first bus; the memory space including all memory locations or addresses that can be directly addressed from the bus. The adapter card includes a second address/data bus 116, which also includes an address bus 118 and a data bus 12 0. A second memory 122 is coupled to second bus 116 and this memory is addressable within the memory space 124 of the second bus. Both buses 102 and 116 also include conventional, non-illustrated control lines, including READ and WRITE lines.

Two registers labeled POS7 (126) and POS6 (128) (POS stands for "Programmable Option Select") are connected to the data bus 106 of first bus 102, and to the address bus 104 through, respectively, address decoders 130 and 132. Address decoders 130 and 132 are of conventional design and when card setup 108 is active, they decode, respectively, addresses 7 and 6. Consequently, the Card Setup line 108 must be active and the lower three (3) address bits must be equal to 7 for SEL POS7 ("Select POS7") to go active. Similarly, Card Setup must be active and the lower three (3) address bits must equal 6 for SEL POS6 to be active. When each of these registers 126 and 128 are addressed, data can be transferred between the data bus 106 and the registers.

Although POS7 and P0S6 can be individually accessed from the first bus, they otherwise function as a single sixteen (16) bit register, which will be referred to as P0S7/6. In addition, the data that is stored in POS7/6 will be represented as a four (4) digit hexadecimal number, e.g., FFF6. An "X" in this number 235 8 ( indicates a "don't care" state. P0S7/6 has an auto-incrementing function. When a pulse occurs at the "I" input of POS6, the register is incremented. When a pulse occurs at the "I" input of P0S7 and the "carry out" or "CO" output of POS6 is active, thereby causing the "carry in" or "CI" of P0S7 to be active, P0S7 is also incremented. P0S7 and POS6 are described in greater detail below with regard to Fig. 2.

The' data stored in POS7/6 is broken down into three (3) non-overlapping ranges. Specifically, a first range from FFFOto FFFF, 10 a second range from 0001 to FFEF, and a third range . from' 0000 to 0000 (i.e., only zero is included in the third range). Address decoder 134 decodes five (5) particular values or ranges of values stored in POS7/6. Specifically, ALL ZEROES (0000 or the third range of values) and its inverse NOT ALL ZEROES, FFF5, FFF6 and NOT 15 ' FFFX (i.e., not in the first range of values). Address decoder 134 is of conventional design.

Registers POS4 (13 6) and POS3 (138) are conventional 8 bit data registers that are connected to data bus 106 of first bus 102. P0S4 is coupled to address bus 104 through address decoder 140 and AND gate 142, while P0S3 is coupled to the first bus through address decoder 144 and AND gate 146. SEL POS4goes active when the lower three (3) address bits of address bus 104 are equal to 4, and card setup 108 is active. Similarly, SEL P0S3 goes active when the lower three (3) address bits are equal to 3 and card setup is active. For P0S4 and POS3 to be selected, however, there is an additional constraint that the data stored in P0S7/6 must be within the third range, i.e.,0000. Consequently, data can be transferred between either POS4 or P0S3 and data bus 106 only when the register is correctly addressed from address bus 104 and P0S7/6 contains 30 0000. 6 235 S 0 Segment Registers SEG REG4 and SEG REG3 are of conventional design, except that the eight (8) data output lines "DO" are connected directly to the latch outputs of the registers; consequently, they are continuously enabled. The conventional Input/Output lines "I/O" are enabled and disabled through the "SEL I/O" (Select Input/Output) line. Thus, data can only be transferred into and out of the "I/O" port when SEL I/O is active. Since the output of AND gate 152 is connected to the SEL I/O input of SEG REG4, and its inputs are connected to the FFF6 output of Address Decoder 134 and the SEL P0S4 output of address decoder 140, the I/O port of SEG REG4 is only enabled when P0S4 has been addressed and the value of the data stored in POS7/6 is FFF6. Consequently, SEG REG4 can only be accessed (written to or read from) when POS4 is addressed and the data stored in POS7/6 equals FFF6. Similarly, since the inputs of AND gate 154 are connected to the FFF5 output of decoder 134 and the SEL P0S4 line, SEG REG3 can only be accessed when POS4 is addressed and the data stored in POS7/6 equals FFF5. It should be emphasized that both segment registers SEG REG4 and SEG REG3 are accessed by addressing POS4 (i.e., SEG REG3 is not accessed by addressing P0S3) .

The eight (8) data output (DO) lines of SEG REG4 are coupled through eight (8) AND gates 156 and eight (8) OR gates 160_to the upper eight (8) address lines of the second bus 116 (the numeral "8" in the center of the gate signifies that the gate is repeated eight (8) times, one for each separate line). Since the other three (3) inputs to AND gate 156 are connected to the NOT FFFX and NOT ALL ZEROES outputs of address decoder 134, as well as to SEL POS4, the eight (8) lines output lines of SEG REG 4 are gated onto the eight (8) upper address lines of second bus 116 only when POS4 is addressed and the value of the data stored in POS7/6 is in the second range (0001 to FFEF) . The eight (8) lines at the output of SEG REG 4 are used to select a first 64KB segment of memory space 7 235 8 0 124 .

Similarly, two of the inputs to AND gate 158 are connected to the NOT ALL ZEROES output of address decoder 134 and to the SEL POS3 line. Consequently, the eight (8) output lines of SEG REG3 are gated onto the upper eight (8) address lines of second bus 116 when POS3 is addressed and the value of the data stored in POS7/6 lies in either the first or the second range, such that SEG REG3 is used to select a second 64KB segment of second memory space 124.

The eight (8) outputs of P0S7 and the eight outputs of POS6 10 are coupled, respectively, to the eight (8) middle address lines and the eight lower address lines of second bus 116 through AND gates 162 and 164. The second input to AND gates 162 and 164 are coupled to address decoders 134, 140 and 144 through AND gates 166 and 168 and OR gate 170. Consequently, the sixteen (16) outputs 15 of POS7/6 are gated onto the sixteen (16) lower address lines of second bus 116 when either P0S4 is addressed and the value of the data stored in POS7/6 is in the second range (0001 to FFEF), or POS3 is addressed and the value of the data stored in POS7/6 is in the first or second range (0001 to FFFF).

Thus, a location in a selected segment of the second.memory space can be indirectly accessed from the first bus by loading the appropriate value into POS7/6 and addressing either P0S4 or P0S3. When a location in the second memory space is so accessed, data is transferred between the memory 122 attached to the second bus 116 25 (via data bus 120) and the data bus 106 of the first bus 102 through eight (8) AND gates 172 and eight AND gates 17 4. The lines labeled READ and WRITE are the non-illustrated read and write control lines from the first bus.

To summarize, the segment registers (SEG REG4 and SEG REG3) 8 235 8 0 are.used to select two 64KB segments of second memory space 124. ^ The base address of the first segment is loaded into SEG REG4 by w storing FFF6 in P0S7/6 and then addressing POS4. similarly, the base address of the second segment is loaded into SEG REG3 by 5 storing FFF5 in POS7/6 and then addressing P0S4.

^ Next, a particular location in the first segment of memory ™ " 122 is addressed by loading the address of the desired location within the segment into POS7/6 (this address must fall -in the range 0001-FFEF) and the selected location is accessed by addressing 10 POS4. Similarly, a particular location in the second segment of memory 122 is addressed by loading the address of the desired location into POS7/6 (this address must fall in the first or second range, i.e., it cannot be zero) and then addressing POS3. After each such access of a location within a segment of the second 15 memory space, P0S7/6 is incremented, such that it points to the next location in the selected segment.

To access POS4 and POS3, P0S7/6 is loaded with 0000 and POS4 and POS3 are addressed from the first bus. ft Fig. 2 is a detailed schematic diagram of P0S7 and P0S6. 20 Referring to this figure, POS 7 includes two 8 bit data latches 202 and 204. Latch 2 02 is clocked from a Register Load Clock signal from the first bus, or whenever one of the segments of the ^ second memory space 124 are accessed from the first bus. Data from ^ the first data bus 106 is loaded into latch 202 through AND gates 25 206 and OR gates 208 when P0S7 is addressed. Similarly, data at the output of adder 210 is loaded into latch 202 through gates 212 when either POS4 or POS3 is addressed, the value of the data in POS7/6 is non-zero, and Auto Increment Enable ("AUTO INC EN") is enabled, as determined by AND gate 214 and OR gate 216. Auto 3 0 Increment Enable is simply a bit in another register (POS5, which 9 235 8 0 is not illustrated in the drawings) which can be set or cleared from first bus 102 and which is used to turn the auto increment feature ON and OFF- One input to Adder 210 comes from the output of latch 2 04, while the other input is the "carry input" from the "carry output" of POS6. Consequently, POS7 will only be incremented when POS6 contains FF. POS6 is similar in design to POS7 except that the "carry input" to adder 218 is set to logic one. Thus, POS6 will be incremented anytime one of the segments of the second memory space is accessed, assuming" that Auto Increment is active.

Claims (19)

1. o o rm r ■ o o ^ * ~;WHAT WE CLAIM IS:;1. Extended addressing circuitry, for use with first and second address/data buses and a memory coupled to said second bus, said extended addressing circuitry comprising in combination:;first and second registers, said first register storing values of data that lie within first, second and third non-overlapping ranges;;range means for determining the range of the data stored in said first register;;means for accessing said second register from said first bus in response to a first address signal on said first bus, said means for accessing said second register being enabled by said range means in response to first data stored in said first register, said first data lying within said first range, whereby data may be transferred between said second register and said first bus when said second register is so accessed;;means for selecting a first segment of said memory, the base address of said first segment corresponding to second data stored in said second register; and means for accessing a first selected address of said first segment of said memory in response to said first address signal on said first bus, said first selected address corresponding to third data stored in said first register, said third data lying within said second range,;11 ^;N.Z. PATENT OFFICE;12 mar 1993;said means for accessing a first selected address of said first segment being enabled by said range means in response to said third data stored in said first register, whereby data may be transferred between said first selected address and said first bus, when said first selected address is so accessed;;whereby, to set the base address of said first segment of said memory, said first data within said first range is loaded into said first register, thereby enabling access to said second register, and then said second data corresponding to the base address of said first segment is loaded into said second register by addressing said first address; and whereby, to access said first selected address of said first segment, said third data lying within said second range and corresponding to said first selected address is loaded into said first register, and then said first selected address of said first segment is accessed by addressing said first address.;
2. 2. The extended addressing circuitry of claim 1, further comprising:;a third register;;means for accessing said third register from said first bus in response to said first address signal on said first bus, said means for accessing said third register being enabled in response to fourth data stored in said;12;12 MAR 1993;first register, said fourth data lying within said first range, whereby data may be transferred between said third register and said first bus when said third register is so accessed; and means for selecting a second segment of said memory, the base address of said second segment corresponding to fifth data stored in said third register.;
3. 3. The extended addressing circuitry of claim 2, further comprising:;means for accessing a second selected address of said second segment of said memory in response to a second address signal on said first bus, said second selected address corresponding to sixth data stored in said first register, said sixth data lying within said first or second ranges, said means for accessing a second selected address of said second segment being enabled in response to said sixth data stored in said first register, whereby data may be transferred between said second selected address and said first bus when said second selected address is so accessed.;
4. 4. The extended addressing circuitry of claim 3, further comprising:;means for auto-incrementing said first register after an address of said memory has been accessed.;13 j N.Z. PATENT OFFICE;ji;J 12 MAR 1993;
5. 5. The extended addressing circuitry of claim 3 or claim 4, further comprising:;fourth and fifth registers;;means for accessing said fourth register from said first bus in response to said first address signal on said first bus, said means for accessing said fourth register being enabled in response to seventh data stored in said first register, said seventh data lying within said third range, whereby data may be transferred between said fourth register and said first bus when said fourth register is so accessed; and means for accessing said fifth register from said first bus in response to said second address signal on said first bus, said means for accessing said fifth register being enabled in response to said seventh data stored in said first register, whereby data may be transferred between said fifth register and said first bus when said fifth register is so accessed.;
6. 6. The extended addressing circuitry of claim 2, further comprising:;means for auto-incrementing said first register after an address of said memory has been accessed.;
7. 7. The extended addressing circuitry of claim 2 or claim 6, further comprising:;a fourth register; and;14 | ;vl.Z. PATENT OFFICE;| 12 MAR 1993;REC-;235800;means for accessing said fourth register from said first bus in response to said first address signal on said first bus, said means for accessing said fourth register being enabled in response to sixth data stored in said first register, said sixth data lying within said third range, whereby data may be transferred between said fourth register and said first bus when said fourth register is so accessed.;
8. 8. The extended addressing circuitry of claim 1, further comprising:;means for auto-incrementing said first register after an address of said memory has been accessed.;
9. 9. The extended addressing circuitry of claim 1 or claim 8, further comprising:;a third register; and means for accessing said third register from said first bus in response to said first address signal on said first bus, said means for accessing said third register being enabled in response to fourth data stored in said first register, said fourth data lying within said third range, whereby data may be transferred between said third register and said first bus when said third register is so accessed.;'J;(,;15;
10. 10. An adapter card for use in a computer having a first address/data bus, said adapter card comprising in combination:;a second address/data bus having a memory coupled to said second bus;;means, coupled to the data bus of said second bus, for transferring data between said first and second buses;;first and second registers, said first register storing values of data that lie within first, second and third non-overlapping ranges;;range means for determining the range of the data stored in said first register;;means for accessing said second register from said first bus in response to a first address signal on said first bus, said means for accessing said second register being enabled by said range means in response first data stored in said first register, said first data lying within said first range, whereby data may be transferred between said second register and said first bus when said second register is so accessed;;means for selecting a first segment of said memory, the base address of said first segment corresponding to second data stored in said second register; and means for accessing a first selected address of said first segment of said memory in response to said first address signal on said first bus, such that data may be transferred between said first bus and said first selected;16;12 MAR 1993;CUuL';address, said first selected address corresponding to third data stored in said first register, said third data lying within said second range, said means for accessing a first selected address of said first segment being enabled by said range means in response to said third data stored in said first register, whereby data may be transferred between said first selected address and said first bus when said first selected address is so accessed;;whereby, to set the base address of said first segment of said memory, said first data within said first range is loaded into said first register, thereby enabling access to said second register, and then said second data corresponding to the base address of said first segment is loaded into said second register by addressing said first address; and whereby, to access said first selected address of said first segment, said third data lying within said second range and corresponding to said first selected address is loaded into said first register, and then said first selected address of said first segment is accessed by addressing said first address.;
11. 11. The adapter card of claim 10, further comprising:;a third register;;means for accessing said third register from said first bus in response to said first address signal on said;17;N.Z. PATENT OFi '■;12 MAR 1993;-n n " >' ; A, o 1/ u ^ v first bus, said means for accessing said third register being enabled in response to fourth data stored in said first register, said fourth data lying within said first range, whereby data may be transferred between said third register and said first bus when said third register is so accessed; and means for selecting a second segment of said memory, the base address of said second segment corresponding to fifth data stored in said third register.;
12. 12. The adapter card of claim 11, further comprising:;means for accessing a second selected address of said second segment of said memory in response to a second address signal on said first bus, said second selected address corresponding to sixth data stored in said first register, said sixth data lying within said first or second ranges, said means for accessing a second selected address of said second segment being enabled in response to said sixth data stored in said first register, whereby data may be transferred between said second selected address and said first bus when said second selected address is so accessed.;
13. 13. The adapter card of claim 10 or claim 11 or claim 12, further comprising:;18 | v. PATENT Ortv"Jr£;1;12 MAR 1993;Fwf;";° ° ~ t\ 0 i "•;means for auto-incrementing said first register after an address of said memory has been accessed.;
14. 14. The adapter card of claim 12 or claim 13,;further comprising:;fourth and fifth registers;;means for accessing said fourth register from said first bus in response to said first address signal on said first bus, said means for accessing said fourth register being enabled in response to seventh data stored in said first register, said seventh data lying within said third range, whereby data may be transferred between said fourth register and said first bus when said fourth register is so accessed; and means for accessing said fifth register from said first bus in response to said second address signal on said first bus, said means for accessing said fifth register being enabled in response to said seventh data stored in said first register, whereby data may be transferred between said fifth register and said first bus when said fifth register is so accessed.;
15. 15. The adapter card of claim 13, further comprising:;a fourth register; and means for accessing said fourth register from said first bus in response to said first address signal on said;19;N.Z. PATENT 0' <=;12 MAR 1993;o "9 ~ ;;£, t..i O * •' ^■» ^ first bus, said means for accessing said fourth register being enabled in response to sixth data stored in said first register, said sixth data lying within said third range, whereby data may be transferred between said fourth register and said first bus when said fourth register is so accessed.
16. 16. The adapter card of claim 11, further comprising: a fourth register; and means for accessing said fourth register from said first bus in response to said first address signal on said first bus, said means for accessing said fourth register being enabled in response to sixth data stored in said first register, said sixth data lying within said third range, whereby data may be transferred between said fourth register and said first bus when said fourth register is so accessed.
17. 17. The adapter card of claim 10, further comprising: a third register; and means for accessing said third register from said first bus in response to said first address signal on said first bus, said means for accessing said third register being enabled in response to fourth data stored in said first register, said fourth data lying within said third • 20 N.Z. PAT.-::- 12 MAR 1993 range, whereby data may be transferred between said third register and said first bus when said third register is so accessed.
18. 18. Extended addressing circuitry substantially as herein described with reference to the accompanying drawings.
19. 19. An adapter card substantially as herein described with reference to the accompanying drawings. 21 N.Z. PATii'Yf O 12 MAR 1993