NZ231845A

NZ231845A - Deriving off-hook subset circuit supply at appropriate voltage

Info

Publication number: NZ231845A
Application number: NZ23184589A
Authority: NZ
Inventors: Ronald Christopher Shaw Fox
Original assignee: Alcatel Australia
Priority date: 1989-12-19
Filing date: 1989-12-19
Publication date: 1992-02-25

Description

<div id="description" class="application article clearfix"> 231845 Priority \ CorprV*»~ f?pec!ijc3lic."s File.± ... CVdZis: .H.Oil-.CO,J..yfe.0.1 ..HCiW.rDl.9j../oQ Fusion p*»= ...1?^. »?2 ^ P.O. r-te: 19 DEC 1989 ^<C eiv3> NEW ZEALAND PATENTS ACT 1953 COMPLETE SPECIFICATION "A CIRCUIT ARRANGEMENT FOR PROVIDING POWER FOR AN IC CHIP IN A TELEPHONE SUBSET" WE, STANDAKD TELEPHONES AND CABLES PTY. LIMITED, A Company of the State of New South Wales, of 252-280 Botany Road, Alexandria, New South Wales, 2015, Australia, hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: 1 23 1 8 45 o o 0 This invention relates to telephone subsets and in particular to telephone subsets of the high voltage type which incorporate a semiconductor line switch and at least one microprocessor to perform and control various circuit func-5 tions such as visual display, memory dialling, clock, calendar, call duration timer, alarm etc. Some of these functions are required when the subsets are in the on-hook mode. Such microprocessors require relatively high current 10 for operation and normally, when one such subset is connected to a single exchange line and is in the on-hook mode, the microprocessor is energized by energy stored in a storage capacitor. The voltage across the storage capacitor is monitored such that when it is below a predetermined value a 15 control circuit operates the line switch to rapidly charge the storage capacitor to a voltage sufficient to maintain the microprocessor. Thereafter the voltage on the storage capacitor is maintained via a bleed circuit. When, however, two or more such subsets are connected 20 In parallel to a single exchange line, a problem arises in providing sufficient energizing power to the microprocessor of any subset in the on-hook mode when one other subset Is In the off-hook mode. Momentarily operating the line switch, as described above, in the subset/s in the on-hook 25 mode is highly undesirable because of interference which this would cause to the transmission from the off-hook subset . 2 23 18 45 It Is therefore an object of the present invention to provide an arrangement for providing power to microprocessor means incorporated in a"telephone subset, which avoids the aforementioned disadvantage. According to the present invention, in a telephone subset of the high voltage type incorporating line terminal means, at least one processor means and a controllable semiconductor line switch means, a circuit arrangement for providing power, derived from line current connected to the line terminal means, to said processor means when said telephone subset Is in an on-hook mode and voltage dropped across said line terminal means Is either of a first magnitude, or a second magnitude which is below first magnitude, said circuit arrangement comprising a storage capacitor means coupled across power terminal means of said processor means, a first capacitor charging circuit adapted to operate said line switch means for a short predetermined period when said subset is In the on-hook mode and connect said line current via the operated line switch means to said storage capacitor means to charge said storage capacitor means to a first predetermined voltage and thereafter maintain said first predetermined voltage with a second storage capacitor charging circuit which couples said line current to said storage capacitor means, wherein said circuit arrangement Includes a third capacitor charging circuit for maintaining a charge of a second predetermined voltage, of less magnitude than said first predetermined voltage, across said 231845 storage capacitor means when the voltage across said line terminal means is of said second magnitude to power said processor means. In order that the invention can be readily understood 5 an embodiment thereof will now be described with reference to the figure of the accompanying drawing which shows a schematic circuit of part of a high voltage telephone subset . Referring to the drawing, subset circuit 1 Includes a 10 polarity guard arrangement D1 to whose input terminals are connected line LI and L2 terminals for connexion to an exchange line (not shown) and across which a parallel subset (not shown) may be connected. The negative output of polarity guard D1 is connected to the subsets - ve voltage rail 15 VDD, and the positive output is connected to terminal "a" of a controllable semiconductor line switch 2. The line switch's controllable switching path appears across said terminal "a" and "b" thereof. The control element input of the line switch Is at terminal "c" which is connected to a 20 high voltage line switch control transistor TRl via resistor R4. Terminal "b" of the line switch is coupled to the subset's transmission circuit (T/X) (not shown). The subset's circuit further comprises a microprocessor (uP)3s a storage capacitor C2 and a parallel voltage reference device in the 25 form of zener diode D3 coupled across terminals VSS and VDD of microprocessor 3 via the "in" terminal and "out" terminal of a conventional three terminal voltage regulator VR. The 231845 characteristics of voltage regulator VR ensure a constant 3 volts at the "out" terminal irrespective of any voltage above 3 volts at its "in" terminal. The subset circuit further includes a first capacitor charging circuit comprising 5 line terminal LI, resistor Rl, line switch 2, diode D4, inductance II to plate of capacitor C2; a second capacitor charging circuit comprising line line terminal LI, resistor R2, collector/emitter junction of transistor TR3 to plate of capacitor 02; and a third capacitor charging circuit com-10 prising line terminal LI, resistors Rl, R3 and R4, collector/emitter junction of transistor TRl, diode D2 to plate of capacitor C2. The base element of transistor TR2 is coupled via resistor R6 to the "DP" terminal of microprocessor 3 and controlled thereby. A diode D5 couples the 15 collector/emitter junction of transistor TR2 to the base of transistor TR4 whose collector/emitter junction Is coupled to the base of transistor TR3. Inductance II in the first capacitor charging circuit ensures that speech current is not shunted away from the transmission circuit. 20 In operation, when the line terminals LI and L2 of the on-hook subset and a parallel on-hook subset (not shown) are Initially connected to an exchange line with capacitor C2 uncharged, 50v exchange battery appears across line terminals LI and L2 subset, transistor TRl is turned on via re-25 sistor R2. Line switch 1 is thereby turned on via resistor R4 and terminal "c". Line current via LI, resistor Rl, switching path "a" - "b" of line switch 1, diode D4, 5 231845 inductance LI charges capacitor C2 which rapidly charges to 3*5 volts whereupon transistors TR4 and TR3 turn on. Transistor TRl is now turned off and thus turns off the line switch. The 3.5 volt charge on capacitor C2 is sufficient to energize microprocessor 2 which thereupon produces a signal at terminal DP for 1 second. This signal Is extended to the base element of transistor TR2 via resistor R6. Transistor TR2 operates and thereby operates transistor TRl. Line switch 1 operates and connects line current via line terminal LI, switching path "a" - "b" of line switch 1, diode D4, inductance LI to storage capacitor C2. The voltage across capacitor C2 now rises to 6.8 volts equal to the knee voltage of zener diode D3. After 1 second the microprocessor removes the signal from terminal DP, transistor TR2 and TRl turn off in turn. The relatively high voltage across capacitor C2 ensures that transistor TRl is fully turned off. This is necessary to prevent transistor TRl from presenting a DC loop to the exchange equipment during an incoming ring condition, and tripping the ring. The charge on capacitor C2 is maintained at the zener voltage (6.8 volts) by line current via line terminal LI, resistor R2 and collector/emitter path of transistor TR3. Voltage regulator VR now provides a regulated 3V at VSS of microprocessor 2 which ensures sufficient power to provide any on-hook functions. In the event of the parallel subset going off-hook, the microprocessor 2 in subset circuit 1 which is in on-hook 23 1 8 45 mode still requires about 12 uA to provide on-hook functions. As soon as the parallel subset goes off-hook the voltage across the line terminals LI and L2 drops from 50 volts to about 10 volts. This causes the voltage across capacitor C2 to decay from 6.8 volts towards 3-5 volts. This occurs because the voltage across resistor R2 is not sufficient enough to provide the 12 uA required by microprocessor 2. When the voltage across capacitor C2 falls to 3«5 volts the difference between the voltage on the "in" terminal and the voltage on the "out" terminal of voltage regulator VR falls to 0.5 volts and therefore the b/e voltage of transistor TR4 is not sufficient to keep that transistor on. Transistors TR4 and TR3 turn off. Line current via resistor R2 is now directed into the base of transistor TRl which is turned on sufficiently to conduct enough current to maintain capacitor C2 at 3-5 volts. If the voltage across capacitor C2 rises above 3.5 volts transistors TR3 and TR4 turn on more, thereby subtracting base current from transistor TRl. Line current via line terminal LI, resistors Rl, R3, R4 collector/emitter of transistor TRl, diode D2 maintains, by virtue of the regulating effect of transistor TRl, a voltage of 3»5 volts across capacitor C2. This current, however, which is typlcaly 12 uA, is insufficient to turn on line switch 1. While the present invention has been described with regard to many particulars, it is understood that equivalents 231845 may be readily substituted without departing from the scope of the invention. 3 8 </div>

Claims

<div id="claims" class="application article clearfix printTableText"> 23 184 What wc claim is :

1. In a telephone subset of the high voltage type incorporating line terminal means, at least one processor means anil a controllable semiconductor line switch means, a circuit arrangement for providing power, derived from line currcnt connected to the line terminal means, to said processor means when said telephone subset is in an on-hook mode and voltage dropped across said line terminal means is cither of a first magnitude, or a second magnitude which is below the first magnitude, said circuit arrangement comprising a storage capacitor means couplcd across power terminal means of said processor means, a first capacitor charging circuit adapted to operate said line switch means for a short predetermined period when said subset is in the on-hook mode and conncct said line current via the operated line switch means to said storage capacitor means to cliargc said storage capacitor means to a first predetermined voltage and thereafter maintain said first predetermined voltage with a second storage capacitor charging circuit which couples said line current to said storage capacitor means, wherein said circuit arrangement includes a third capacitor charging circuit for maintaining a charge of a second predetermined voltage, of less magnitude than said first predetermined voltage, across said storage capacitor means when the voltage across said line terminal means is of said sccond magnitude to power said processor means.

2. A circuit arrangement as claimcd in claim 1, wherein said first capacitor charging circuit includes a first semiconductor switch means a switching path of which is coupled to a control element of said controllable semiconductor line switch, and a control element of which is couplcd to an output of said processor means at which is provided a signal for a short predetermined period to momentarily operate said first semiconductor switch means and connect line currcnt to said capacitor 9 f-j.z. fat: ;.t orj 2 2 J A J. 1302 RECEIV ") 23 1845 storage means via a path including the so operated said line switch to charge said storage capacitor means to said first predetermined voltage.

3. A circuit arrangement as claimcd in claim 2. wherein said path connccting said line current to said storage capacitor means further includes a serially conncctcd diode and inductance.

4. A circuit arrangement as claimcd in any one of the preceding claims, wherein said second capacitor charging circuit includes a second semiconductor switch means a switching path of which is conncctcd between said line terminal means and said storage capacitor means and a control element of which is couplcd to said power terminal means of said processor means, whereby said second semiconductor switch means is rendered conducting when the charge on said storage capacitor means reaches said first predetermined voltage.

5. A circuit arrangement as claimcd in any one of the preceding claims, including a voltage regulator means having an input coupled to said storage capacitor means and an output coupled to said power terminal means, said voltage regulator's characteristics being such that a substantially constant third predetermined voltage is provided at said output when the charge on said capacitor storage means is either the first predetermined voltage or the second predetermined voltage.

6. A circuit arrangement as claimcd in claim 5, wherein said voltage regulator means is a three terminal voltage regulator.

7. A circuit arrangement as claimed in claim 5 or 6, wherein said third capacitor charging circuit includes said first semiconductor switch means whose said switching path couples said line terminal means to said storage capacitor means, and whose control element is couplcd to a voltage controlled device, said voltage controlled device being arranged to monitor the difference between a voltage on the input and the voltage on the output of said voltage regulator means and when said difference equals N.Z. PATENT OFFICE 22 JAM 1392 10 23 1845 a fourth predetermined voltage, cause said first semiconductor switch means to conduct sufficient line currcnt to maintain a charge of said second predetermined voltage on said storage capacitor means.

8. A circuit arrangement as claimcd in claim 7, wherein said voltage controlled device comprises a third semiconductor switch means a switching path of which is coupled between the control element of said first semiconductor switch means and the output of said voltage regulator means, and a control element of which is couplcd to the input of said voltage regulator means, said third semiconductor switch means being rendered non-conducting when the difference between the voltage on the input and the voltage on the output of the voltage regulator means equals said fourth predetermined voltage.

9. A circuit arrangement as claimcd in claim 8, wherein said switching path of said third semiconductor switch means is conncctcd to the control element of said second semiconductor switch means, which is rendered non-conducting when said third semiconductor switch is non-conducting, the charge on said storage capacitor means being maintained by said third capacitor charging circuit.

10. A circuit arrangement as claimcd in any one of claims 2 to 9, wherein a voltage reference device is connected across said storage capacitor means.

11. A circuit arrangement as claimcd in claim 10, wherein said voltage reference device is a zener diode.

12. A circuit arrangement, substantially as herein described with reference to the figure of the accompanying drawing. STANDARD TELEPHONES AND CABLES PTY. LIMITED B.O. Connor Authorized Agent P5/1/1703 r-'.Z. P Vr.-A'T OFFICE 22 JAN 1992 ii RECEIVTD </div>