NZ212245A - Multiple memory loading system - Google Patents

Description

IMSSff NEW ZEALAND PATENTS ACT 195 3 COMPLETE SPECIFICATION swiyriTUTiDF;c AFPUCAIVT I wwfs ?Ecrm 24 1 "MULTIPLE MEMORY LOADING SYSTEM" ^£n,c.vcj fry LlN{7^ I WE, IN?ERNATTONA"L STANDARD-ELECTRIC'~CORPORAT-ION, a Corporation of the State of Delaware, United States of America, of 320 Park Avenue, New York 22, New York, United States of America, hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The invention relates to a multiple memory loading system with a plurality of intercoupled modules including memories and processing means and at least one of which is able to transmit each of a plurality of data packets to the memories of a number of modules wherein said data packet may then be stored.

Such a system is already known in which each of said data pakcets is simultaneously transmitted from one module to all the modules to be loaded. But each of these modules has previously been so conditioned that it is only able to accept predetermined ones of these .data packets. Such a conditioning 10 operation has to be individually performed for each mobile and is therefore time consuming. This time may be relatively high in accordance with the number of terminal modules, as is the case for instance in an automatic telecommunication switching system with distributed processor control such as described in various articles published in Electrical Communication, Volume 56, N° 2/3, 1981, and particularly on pp. 135 to 160 and 173 to 183.

An object of the present invention is to provide a multiple memory loading system of the above type, but which permits a faster loading of the module memories.

According to the invention this object is achieved in that the transmiss-20 ion of each of said data packets frcm said one module only occurs directly to the memories of a number of predetermined modules of an initial set arid indirectly from said memories to memories of other modules.

Preferably the transmission of said data packet to said number of predetermined modules of an initial list and storing the identities of the modules of said initial set, constitutes the first step of an iterative process each step of which consists in transmitting said packet from a source module storing a list of the identities of the modules of a set to a number of predetermined destination modules of res pective sublists of said list, together with said respective sublist and in storing said data packet in the memory 30 of said predetermined destination module which during a following step becomes the source module and then uses said sublist.

One module may be adapted to transmit said data packets successively to a number of predetermined modules of respective initial lists of said modules.

The data packet may be simultaneously transmitted to said number of predetermined modules.

As soon as the one module has transmitted a data packet directly to each of a number of predetermined modules of an initial set together with a respective sublist of the modules to be loaded by this predetermined module, the 40 one module may immediately start the transmission of another data packet to a number of predetermined modules of another initial set, since in the former initial set the memory loading operation of the other modules may be performed with the help of the received sublist and independently fron the one module. Thus a fast loading operation of the various data packets fran the one module in the respective initial sets is ensured, and the speed of the loading operation is further enhanced by the fact that during each step the predetermined modules are loaded simultaneously.

During each of said steps said initial list may be transmitted to said predetermined modules together with parameters permitting to derive said 10 sublists fron said initial list.

During each of said steps a parameter may also be transmitted to each of said predetermined modules enablinq it to derive frcm said initial list the same sublists as those derived fran said initial list by said one module during said first step of said iterative process, and that after its memory has been loaded said predetermined module derives said same sublists from said initial list and attempts during an additional memory loading operation to load said data packet into homologous modules of these sublists.

The modules may be inter coupled through a switching network.

In this way, during the additional memory loading operation homologous 20 modules in the sublists attanpt to load each other's memory. This means that the manory loading of each module is attempted during the iterative normal loading process as well as at least once during the additional loading operation. These attempts are performed by different modules and therefore also through different paths of the switching network. A module which had not been loaded during the normal loading process, e.g. due to a preceding module being faulty, may new possibly be loaded by another module, thus isolating the effect of such a fault. Thus the additional loading operation considerably enhances the reliability of the system.

The present invention also relates to a multiple memory loading system 30 such as defined in the first paragraph of the present specification and characterized in that it includes at least two of said one modules which each are adapted to load respective data packets of said plurality into the memories of predetermined modules of respective sets and that after any of them has finished its loading operation it attempts to perform the loading operation nrcmally executed by the other one module.

Preferably the memory of each of said modules to be loaded stores a phase indicator which is braight in a predetermined condition when this memory has been loaded with said data packet and which then prevents a renewed loading of said memory. 40 Because the manory loading operation is shared by two modules the speed of this operation is enhanced. Moreover, since each of these modules, after having performed its job, attempts to load the module manories normally to be loaded by the other module the reliability of the system is considerably increased. Finally, by the presence of the phase indicator no time is spent to load memories which were already loaded.

The abovementioned and other objects and features of the invention will becane more apparent and the invention itself will be best understood by referring to the following description of an embodiment taken in conjunction with the accanpanying drawings in which: Fig. 1 is a schematic view of a multiple memory loading system accord ing to the invention; Figs. 2 and 3 shew parts of the memories MP A. and MPl of Fig. 1 respectively; Fig. 4 illustrates the operation of the system of Fig. 1.

The present multiple msnory loading system forms part of an automatic telecommunication switching system of the type described at length in the above-mentioned number of Electrical Ccmnunication, and more particularly in the following articles thereof to which reference is made : "Hardware Description" by S. Das et al, pp. 135-147; "Digital Switching Network" by 20 J.M. Cotton et al pp. 148-160 and "Software Concepts and Implenentation" by L. Datzschner et al, pp. 173-183. Reference is also made to U.S. Patent 4 418 396.

This multiple memory loading system includes a plurality of terminal modules or terminal control elements TCEl to TCEn and TCEA and TCEB which are all coupled to a digital switching network DSN. The control elements TCEl to TCEn are all identical and therefore only TCEl is shown in relative detail. The same is true for TCEA and TCEB of which only TCEA is represented in some detail.

The digital switching network DSN is a four-stage network and the network 30 address of each control elenent is a four digit number ABCD by means of the digits of which a connection may be set up through the respective stages of the network. Connections between control elements only penetrate into the network as far as necessary. For instance, to establish a connection between the control elements with addresses 6231 and 1331 the stages 4 and 3 are not used since the D and C digits of these addresses are equal. This means that these control elements are close to each other in the network. On the contrary, if these addresses are for instance 6231 and 1342 all the stages are involved in the connection between the control elements.

In the following only TCEl and TCEA are described. Terminal control 40 element TCEl includes a terminal interface Til, a microprocessor MPl and a memory MEMl which are all able to communicate via a high speed bus HS1 operating at 64 Megabit/sec. The terminal interface Til includes a RAM memory and five ports which are all connected to a time division multiplex bus TDM1. The two ports Pi and P2 are connected to the digital switching network DSN through links Lll and LI2 relatively, whilst the two ports P3 and P4 are each connected to respective ones of two terminal units. More particularly, link LI3 connects port P3 to a terminal circuit TCI in terminal unit TUl which is for instance connected to a plurality of subscriber lines or trunk lines (not shewn), as well as to a low speed bus LSI to which also 10 microprocessor MPl has access. This bus operates at 64 kilobit/sec.

Finally, port P5 connects the high speed bus HSl to the time division multiplex bus TDM1.

Terminal control interface TCEA. is similar to TCEl/n and includes a terminal interface TIA which is connected to DSN through links Lai and La2, a microprocessor MPA and a memory MEMA which are all able to caimunicate via a high speed bus HSA. However, the latter bias HSA is now connected to a data storage disc DA in a terminal unit TUA.

All the abovementioned links are bothway links used on a TOM basis with 32 channels for each direction, 30 of which are used for data transmission. 20 The ranaining 2 serve for synchronization and signalling purposes. Hence a total of 60 effective incoming and outgoing data channels is available between each terminal control element and DSN.

The unit comprising TCEB and TUB is similar to the unit TCEA, TUA and each of them is used for loading data pakcets into the memories of respective groups of the control elements TCEl to TCEn. As these two units share the work load they speed up this data packet loading operation. They also increase the reliability of the system since each of them is able to perform the loading operation of all these memories on its am. The data packets to be loaded by TCEA, TOA and TCEB, TUB are stored on each of the discs DA and 30 DB and comprise a number of m application programmes GLS1 to GLSm (Generic Load Segments) to be loaded in m corresponding sets of control elements of TCEl/n as well as specific data packets DLSl/n to be loaded in respective ones of these control elements. These two loading operations and a subsequent restart operation are successively performed in three distinct operation phases 0, 1 and 2, as will become clear later.

The data packet loading operation is performed under the control of a fast load initialization programme (FLINIT) and a fast load programme proper (FLOAD) stored in the memories of TCEA and TCEB, aixi of a multichannel cascading programme MCC stored in the memories of each of the control elements 40 TCEl to TCEn together with a phase indicator PI, (Fig. 2) to indicate the last mentioned operation phases. More particularly, and as will be explained in detail later, each of the programmes GLS1 to GLSm is transmitted directly and simultaneously to the manories of a number, say 4, of predetermined terminal control elements of a corresponding initial set under the control of the programme FLINIT and FLOAD and from these predetermined modules this application programme is transmitted or cascaded to the other terminal control elements of the initial set in iterative steps under the control of the programmes MCC of these control elements.

The transmission of data packets and the camrunication between the con-10 trol elements TCEA, TCEB and TCEl to TCEn is performed by means of messages. Each of these messages is prepared by the microprocessor of a source control element under the control of the programme stored in the memory thereof, and under the control of the same programme the microprocessor then registers this message in the RAM memory and finally transmits it from this matiory to a destination control element. For instance, MPl controlled by MCC stored in MEM1 prepares a message and stores it in RAM via HSl, P5 and 1DM1 and afterwards transmits it on link Lll or L12 via TDMl and Pi or P2 respectively.

To be noted that to speed-up a loading operation the carrnunication by 20 means of messages is basically undirectional frcm source to destination.

Indeed, the sole backward carrnunication is performed by negative acknowledgement signals (NAK) which are normally used to signal a failure, e.g. when the phase indicator of a message is different fran that of a destination control element or if such a control element is not available.

The messages used are : OPEN : a message used to open a channel of a link to be used for memory loading. This message includes a phase indicator and the identities of the source and destination control elanents of this message. This message is only stored in the memory of the destination control element if the phase 30 indicator of this message equals the phase indicator PI stored in the memory of this control element; CASCADE : a message used to order a destination control element of a set having received a data packet in its memory to transmit or cascade this packet to the memories of other control elements' of this set. Details of this message will be given later; LOCATE : a message used to define the start address of a data packet in the memory of a destination control elanent. This message may itself contain data; DATA : a message containing data only; 40 DOCK : a message ordering the lock-out of unopened channels by putting them in the maintenance state wherein no messages can be written in the RAM of this element.

The loading of the memories of the data packets GLSl/m in the memories of the various TCEl to TCEn is described in detail below. To this end only the unit TCEA, TUA is considered. To be noted that TCEA as well as TCEB have a very low network address because the abovementioned selection bits A, B and C thereof are 0.

When the progranme FLINIT stored in memory MEMA of TCEA runs, the following lists are set up in the memory MEMA : - a control list CL (Fig. 2) wherein the data packets GLS1 to GLSm are ordered in such a way that the number of iterative steps required to load these programmes, i.e. the cascading time, decreases fran top to bottom; m task lists or initial lists TL1 to Tim (Fig. 2) providing the identities or addresses of the control elements forming part of the abovementioned m sets of control elements into which the data packets GLS1 to GLSm have to be loaded respectively. In each such task list the terminal control elements of the corresponding set are ordered with their network addresses decreasing fron top to bottom. This is done to minimize the danger of blocking in the switching network DSN during cascading, as will be explained 20 later.

Fig. 3 represents task list TLl in more detail: it stores the network addresses of the q TCEs, TCEl to TCEq with e.g. q = 50, whose memories have to be loaded with the programme GLS1.

After having performed the progranme FLINIT, the unit TCEA, TUA executes the progranme FLOAD which comprises itself a fast load input from disc progranme FLOID and a fast load output to network progranme FLOON.

Under the control of the progranme FDOID of TCEA, the odd numbered application progranme GLS1 indicated by the control list CL (Fig. 2) is first read from disc DA into memory MEMA via the high speed bus HSA. Afterwards 30 the progranme FLOON of TCEA controls the loading of this progranme GLSL simultaneously into a number of predetermined control elements of the corresponding set TCEl/q. TCEA then starts reading the following odd numbered application progranme GLS3 from disc DA and transmits it simultaneously to predetermined control elements of a corresponding set of control elements, etc. During the operation of TCEA, the unit TCEB, TUB successively reads the even numbered application programmes GLS2, GLS4, ... etc. from disc DB and transfers them to predetermined corresponding sets of control elements. Obviously by proceeding in this way the loading operation is speeding up.

In the following only the loading of progranme GLSl in TCEl/q is cons-40 idered, reference being particularly made to Fig. 4. Hereby it is assumed that the phase indicator PI of all these control elanents is on 0, meaning that nothing is loaded in their memories.

The programme FLOON gets fron the memory MEMA the task list TL1 as well as the maximum number p of predetermined TCEs to be simultaneously loaded by TCEA and the maximum number c of channels to be simultaneously used for transmission of GLS1 to each of these TCEs. The latter number c depends on the size of the RAM and is for instance at most equal to 15. In this case and because 60 channels are available p is equal to 4.

If p is greater than or equal to the length q of TLl, the progranme FLOON can load the memories of TCEl to TECq in one go. It launches c OPEN messages on c channels to each of these TCEs and waits on each channel during a predetermined time interval for a negative acknowledgement signal NAK which is for instance received when the phase indicator of the message is different frcm that stored in the TCE or when the channel or the TCE itself is not available. A LOCK message is sent to each of the available TCEs to tell the progranme MCC in these TCEs to put unopened channels in the maintenance state.

On the contrary, if p is less than the length q of task list TLl, then GLSl is transferred or cascaded from memory MEMA of TCEA to the memories of TCEl to TCEq in several iterative steps. To this end the progranme FLOON of TCEA first divides the task list TLl of length q into a number of at most p primary sublists at least two of which have a maximum length s. In this way each control element of a sublist has at least one homologous partner in the other sublist(s). This fact is exploited in an additional loading operation performed to increase the reliability of the systan, as explained in detail later.

The above maximum length s could be obtained by taking the rounded up value of s = ^ , but because the processor of a control element is only able P to calculate the rounded down value of a quotient and also in order to obtain a correct value if the quotient and also in order to obtain a correct value if the quotient ^ and subtracts frcm ^ respectively. The proc- P P P essor therefore calculates the rounded down value of the expression s = q + P ~ 1 P All p primary sublists of TLl are then given the same length s, apart frcm the last which is given the length q - s(p - 1) and may be shorter than s. For instance, when q = 50 and p = 4 then 4 primary sublists TCEl/13, TCE14/26, TCE27/39 and TCE40/50 having a length s equal to 13, 13, 13 and 11 respectively are formed.

Assuming such a division, the progranme FLOON of TCEA then selects the first TCEs of the p primary sublists TCEl/13, 14/26, 27/39 and 40/50 and 2122-i5 launches c OPEN messages on c channels to each of these predetermined TCEs and waits on each channel during a predetermined time interval for a negative acknowledgement signal NAK.

Supposing that all c = 15 channels to each of the predetermined or first terminal control elements TCEl, TCEl4, TCE27 and TCE40 of the above sub-lists are available, the programme FLOON of TCEA successively sends to each of these a LOCK message and also a CASCADE message which comprises : a phase indicator; the location in memory wherein the task list TLl is to be found at the 10 end of a loading operation; the number s (13, 13, 13 or 11) of TCEs contained in the sublist TCEl/ 13, 14/26, 27/39, 40/50 starting with the TCEl, 14, 26, 40 under consideration; a divisor n = p to be used during an additional loading operation to be described later; the maximum number p' of TCEs to which data may be simultaneously transmitted fran the TCE under consideration; the maximum number c' of channels to be used for this data transmission. The programme FICON of TCEA then sends to each of the abovaiventioned 20 four predetermined TCEs LOCATE messages containing the location of the men-ory wherein data has to be stored. These data comprise the task list TLl and GLSl and are transmitted by these LOCATE messages and by DATA messages.

To be noted that TLl and GLSl are sent to each control element in packets, each packet being subdivided in c parts which are transmitted independently on the c channels. As a consequence, the transmission speed of these packets is c times larger than the channel speed which is for instance equal to 8 kbyte/sec.

Upon receipt of the messages LOCK, CASCADE, LOCATE and DATA the progranme MCC in the predetermined TCEs, TCEl, TCEl4, TCE27 and TCE40 puts all 30 unopened channels in the maintenance state and stores the task or initial list TLl, the application progranme GLSl and the parameters s (13, 13, 13, 11), n = p, p' and c' in its manory. It also changes its phase indicator PI to 1 indicating that the loading of the GLSl has been performed.

The progranme MCC of each of these four predetermined TCEs further finds the corresponding primary sublist TCEl/13, TCE14/25, TCE27/39, TCE40/ 50 in the task list TLl by means of its own address and the corresponding parameter s. It then subdivides this primary sublist into at most p'+l secondary sublists of maximum lengths s' by using a formula which is the same as the one given above. Thus the maximum length of the secondary sub-40 lists of this primary sublist is obtained s' = 5 J? V c> when p' = 4 the primary sublist TCEl/13 has five secondary sublists TCE1/3, TCE4/6, TCE7/9, TCE10/12 and TCE13 with lengths s' equal to 3, 3, 3, 3 and 1 respectively. Likewise, the primary sublists TCEl4/26 and TCE27/39 each have five secondary sublists containing 3, 3, 3, 3 and 1 TCEs respectively, and the primary sublist TCE40/50 has only four sublists containing 3, 3, 3 and 2 TCEs respectively.

It should be noted that this second split is somewhat different from the initial one since one new divides by p1 + 1 instead of p' as one would expect. Thus, TCEl is for instance included in the first of the 5 second-10 ary sublists TCEl/3, 4/6, 7/9, 10/12 and 13 obtained by subdividing the primary sublist TCEl/13 although TCEl has already been loaded previously. However, by proceeding in this way TCEl can take care of the loading of TCE2 and TCE3 after GLSl has been transmitted to TCE4, 7, 10, 13 via p'c' ^ 60 channels. Thus the speed of the loading operation is increased. This would not be so if only TCE2.13 would have been subdivided in sublists since after TCEl would have transferred GLSl to say TCE2, 5, 8, 11 it would have remained inoperative.

In an analoguous way as described above, the progranme GLSl, the task list TLl and corresponding parameters s' (3, 3, 3, 1), n = p, p" and c' are 20 then transmitted on c' channels from TCEl, TCE14, TCE27 and TCE40 to each of the first TCEs of the corresponding secondary sublists, except the first one. For instance these information are transmitted from TCEl to TCE4 (with s' = 3), TCE7 (with s; = 3), TCE10 (with s' = 3) and TCE13 (with s* = 1) .

Afterwards and again in an analoguous way, the length s" of ternary sublists is calculated with the help of s' and p" is transmitted together with GLSl and other parameters such as s" from TCE4 to TCE5 and TCE6; from TCE7 to TCE8 and TCE9, and finally fran TCE10 to TCE11 and TCE12. Meanwhile TCEl also calculates a parameter s" and transmits GLSl to TCE2 and TCE3. The same is true for the other TCEs so that at the end of the iterative or 30 cascaded loading operation the memories of all the TCEs of the set TCEl/q have normally been loaded with the progranme GLSl. If this is so their phase indicator PI is on 1.

However, when one of the control elements fails, a number of control elements will not have been loaded with GLSl and their phase indicator will remain on 0. For instance, when TCE4 fails the control elements TCE5 and TCE6 will not have been loaded. To minimize the effect of such a failure each TCE starts an additional loading operation as soon as GLSl has been loaded therein and if it has no more cascading work to do. This additional loading operation consists in subdividing the initial task list TLl by the 40 divisor n = p to get again the same primary sublists as those obtained by TCEA and in then attainting to load partner control elements one at a time. Partner control elements are defined as TCEs which are at honologous positions in the primary sublists. For instance, when TCEl8 (18 = 5 mod 13) starts an additional loading operation, it subdivides the task list TLl in the 4 primary sublists TCEl/13, TCE14/26, TCE27/39 and TCE40/50 and attempts to load its partners TCEl5, TCE31 (31 = 5 mod 13) and TCE44 (44 = 5 mod 13) which have not been loaded during the normal loading operation i.e. for which PI is still on 0. Nothing is done in the TCEs for which PI = 1.

In this way every TCE which is not faulty attempts to load GLSl in a 10 number of TCEs via paths different frcm those via which the loading of these TCEs was attempted during the cascading operation. This means that by the additional loading operation the reliability of the systan is considerably increased.

To be noted that due to at least two of the sublists, e.g. TCEl/13, 14/26, 27/39, 40/50 being longer than the other sublists, e.g. TCE40/50 each control element of any of these sublists always has a partner. This would not be the case if there would have been only one longer sublist.

As already mentioned above, when TCEA transmits GLSl to predetermined control elements of a corresponding initial set of TCEs, then TCEB transmits 20 GLS2 to predetermined control elements of another corresponding initial set of TCEs. Afterwards TCEA and TCEB transmit the programtes GLS3, GLS5,... etc. and GLS4, GLS6, etc., to predetermined control elements of corresponding initial sets of TCEs. When each of the control elanents TCEA and TCEB ccmes to the end of the control list CL, it attempts to load the CLSs normally loaded by the other one, i.e. GLS2, GLS4, .... and GLSl, GLS3, ..., into predetermined control elements of corresponding initial sets respectively. This means that by TCEA and TCEB two attempts are made to load a GLS in predetermined control elements of the respective initial sets. As already mentioned, in each control element wherein a GLS has been loaded, the 30 phase indicator is set frcm 0 to 1 so that TCEA or TCEB only attempts the loading of contorl elements for which PI is on 0.

The abovementioned data DLSl/n are then loaded in the respective control elements TCEl/n and in each of these which was previously loaded by a GLSl/ m the phase indicator PI is then changed fron 1 to 2. It should be noted that the data are loaded in the order indicated by a corresponding list wherein DLSl/n are so ordered that the longest cascade should be performed last. In this way a maximum time is provided to load each of the GLSs.

After having thus tried to load the GLSs and DLSs in all the TCES, TCEA (TCEB) informs its mate TCEB (TCEA) and waits until the latter has finished 40 its loading operation. If this mate TCEB (TCEA) then confirms this end of operation, TCEA (TCEB) restarts all TCEs and informs the mate TCEB (TCEA) of the end of such a restart operation. Fran the above it follows that which of TCEA and TCEB first finishes a memory loading operation is responsible for restarting the TCEs.

As mentioned above, the TCEs of each task list such as TLl are ordered in such a way that the TCE network addresses decrease fran top to bottom. This measure and the splitting of the list into sublists used by FLOON and MCC with equally spaced TCEs minimizes the chances of blocking during the cascading operation. Indeed, although it is true that the number of TCEs 10 involved in a cascading operation increases as the cascading progresses, the network addresses of cascaded TCEs, e.g. TCE4 and TCE5, then beane less different because the TCEs are ordered in TLl so that the paths in the DSN between such TCEs became shorter, such paths having a lover blocking probability. Moreover, because the TCEs are reversely ordered and TCEA/B each have a very low network address ABCD with A=B=C=0 interference is avoided between channels of the same switch of the first stage of the network DSN to which e.g. TCEA and several TCEs are connected. Indeed, TCEA may only be connected to a control elanent having a higher network address via an outgoing channel, whilst the last mentioned TCEs may only be reached fran a 20 control element with a higher network address via an incoming channel.

Fran the above it follows that the transmission of the complete task list TCI from TCEA ot all the TCEs is only required because this list is used in a subsequent additional loading operation. Otherwise it would be sufficient to transmit only the sublist of modules to which a received data packet has to be transmitted. For instance it vrould be sufficient to transmit to TCEl only the list TCEl/13.

While the principles of the invention have been described above in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation on the 30 scope of the invention.

Claims (25)

What we claim is:-

1. A multiple memory loading system comprising one or more terminal control interface arrangements (TCEA) each having a data memory (DA, MPA), an interface control processor (MPA), and and Interface circuit (TIA), through which, via a first data bus (HSA) the data memory and interface control processor is connected to a communication network (DSN), the system including a plurality of terminal control elements (TCE) each having a terminal interface circuit (TI) including a second data bus (TDM1) connected to the communication network via corresponding first ports (PI, P2), and to one or more terminal units (TU) via corresponding further ports (P3j P4), the terminal control elements each including a terminal control processor (MPl) and a terminal memory (MEM) connected to a third data bus (HS1), which is connected to the second data bus via an additional port (P5), the terminal interface circuit including a message memory (RAM) connected to the second bus, the terminal units each being connected to one or more corresponding trunk or subscriber lines, wherein the or each control interface arrangement is able to transmit each of a plurality of data packets (GLS) from its data memory to the terminal memories of one or more predetermined terminal control elements of an initial list of such elements (TCE), wherein the data packets may be stored, and wherein the one or more predetermined terminal control elements of the initial list are enabled by a predefined message in the data packet initiating the corresponding terminal control processor to relay the data packets to the terminal memories of other terminal control elements.

2. A memory loading system as claimed in claim 1 wherein the terminal control elanents to which the data packages are relayed may be enabled to relay the data packages to further terminal control elements. A > o x V <■ M •<* "A C 14 OCT 1988 ij 13 v / e e i vs,r '31S P 4 5

3. A memory loading system as claimed in claim 1 wherein the terminal control elements are divided into sets in a hierarchy through which the data packages are relayed under the control of predefined messages in the data packages.

4. A multiple memory loading system as claimed in any one of claims 1 to 3, wherein the transmission of a data packet to the predetermined terminal control elements of an initial list and storing the identities of the terminal control elements of the initial list constitutes the first step of an iterative process, each iterative step of which consists in transmitting a data packet from a source terminal control element storing a list of the identities of predetermined destination terminal control elements to the terminal control elements of respective sublists of the list, together with the respective corresponding sublist and in storing the data packet in the memory of the predetermined destination terminal control elements which during a following step become the source terminal control elements and then use the sublist as the list.

5. A multiple memory loading system as claimed in any one of claims 1 to 4, wherein the terminal control elements or terminal control interface arrangement are adapted to transmit the data packets successively to a plurality of predetermined terminal control elements of respective initial lists of said terminal control elements.

6. A multiple memory loading system as claimed in claim 5, wherein the data packet is simultaneously transmitted to the plurality of predetermined terminal control elements.

7. A multiple memory loading system as claimed in claim 4 or any one of claims 5 and 6 as appended to claim 4, wherein the list used during a step, except the initial list used by the terminal control interface arrangement during the first step, includes the identity of-the. terminal con- 14 \ 14 OCT 1988 •// \ i <o/ '212245 trol element in the memory of which the data packet has been loaded during a previous step.

8. A multiple memory loading system as claimed in claim 7 as appended directly or indirectly to claim 4, wherein during the first step of the iterative process the terminal control interface arrangement subdivides the initial list into a maximum number of sublists equal to the maximum number of destination terminal control elements to which the data packet may be simultaneously transmitted by the terminal control interface arrangement.

9. A multiple memory loading system as claimed in claim 7 or claim 8 both as appended either directly or indirectly to claim 4, wherein during each of the steps of the iterative process, other than the first step, the source terminal control element subdivides the list into a maximum number of sublists equal to the maximum number of destination terminal control elements to which the data packet may be simultaneously transmitted by the source terminal control element plus one.

10. A multiple memory loading system as claimed in claim 9, wherein during each step other than the first step the previously loaded source terminal control element transmits the data packet to predetermined terminal control elements of the subsets which do not include the previously loaded terminal control interface arrangement or terminal control element, and that during a following step the previously loaded terminal control interface arrangement or terminal control element transmits the data packet to predetermined terminal control elements of the sublist of which it forms part.

11. A multiple memory loading system as claimed in any one of the preceding claims, wherein the switching network is a multi-stage digital switching network and the terminal control elements and terminal control interface arrangements each have an address comprising a number,-of.digits 14 OCT 1983^ 15 * ' W- ' 512845 equal to the number of stages of the network and are each able to control path set up in respective ones of the stages and that in each of the lists the terminal control elements thereof are ordered according to their network addresses.

12. A multiple memory loading system as claimed in claim 11, wherein in the list the network addresses are ordered in a decreasing order.

13. A multiple memory loading system as claimed in claim 11 or 12, wherein the predetermined terminal control elements of the initial lists are the first of the sublists.

14. A multiple memory loading system as claimed in claim 4, wherein during each of the steps the initial list is transmitted to the predetermined terminal control elements together with parameters permitting to derive the sublists from the initial list.

15. A multiple memory loading system as claimed in claim 14, wherein the parameters indicate the number of terminal control elements in the list and the maximum number of sublists to be derived from the list respectively .

16. A multiple memory loading system as claimed in claim 14, wherein during each of the steps a parameter is also transmitted to each of the predetermined terminal control elements enabling it to derive from the initial list the same sublists as those derived from the initial list by the terminal control interface arrangement during the first step of the iterative process, and that after its memory has been loaded the predetermined terminal control element derives the same sublists fran the initial list and attempts during an additional memory loading operation to load the data packet into homologous terminal control elements of these sublists. 16 '-'12245

17. A multiple memory loading system as claimed in claim 16, wherein at least two of the sublists of the initial list have a length larger than the length of the other sublists.

18. A multiple memory loading system as claimed in claim 4, wherein the plurality of data packets are arranged in a list in such a way that the number of iterative steps required to load these packets in the terminal control elements of respective initial lists decreases from top to bottom of the list, and wherein it includes two terminal control interface arrangements to load alternate data packets of the list starting at the top thereof, in the terminal control elements of respective initial lists.

19. A multiple memory loading system as claimed in claim 18, wherein after either of the terminal control interface arrangements has finished the loading of the alternate data packets into the terminal control elements of the respective initial list, it attempts to load the data packets in the corresponding terminal control elements normally to be loaded by the other interface arrangement.

20. A multiple memory loading system as claimed in claim 14 or 15, wherein the memory of each of the terminal control elements to be loaded stores a phase indicator which is brought in a predetermined condition when the memory has been loaded with the data packet and then prevents a renewed loading of the memory.

21. A multiple memory loading system as claimed in claim 4 or 11, wherein each of said terminal control elements is coupled to the switching network via time division multiplex links comprising a plurality of time channels and that during each of the steps the data packet is transmitted to each of the predetermined terminal control elements simultaneously on a plurality of the channels, together with a parameter indicating the maximum number of channels which may be used by the predetermined,, terminal^ control r?4 OCT 1988^ 17 21224 element for the transmission of the data packet to each of other predetermined terminal control elements.

22. A multiple memory loading system as claimed in any one of claims 14, 16 or 21, wherein the transmission of the data packets and the parameters is performed from the terminal control interface arrangement to the destination terminal control element by means of messages and is substantially unidirectional, return signals being only transmitted from the destination terminal control element to the source terminal control element or terminal control interface arrangement in case of error.

23. A multiple memory loading system as claimed in claim 22, wherein prior to the transmission of the messages other messages are transmitted from the terminal control interface arrangement or source terminal control element to the destination terminal control element on the channels to check the availability thereof.

24. A memory loading arrangement substantially as herein described with reference to the accompanying drawings.

25. A method of loading memories as herein described with reference to the accompanying drawings. STANDARD TELEPHONES AND CABLES PTY. LIMITED o \* 1 A nn 19881 v P.M. Conrick Authorized Agent P5/1/1703 18