NZ206167A - Single port gyrator:transformer coupled - Google Patents

Description

*06/ 6 TRUE COPY Priority Date(s): .

Complete Specification Filed: Class: ti 2 NOV Publication Date: ...

P.O. Journal, No: .... (& »,^ T ,~~c ■4 NOV 1983 II s$>/ 4 NEW ZEALAND THE PATENTS ACT, 1953 COMPLETE SPECIFICATION "A CURRENT SINK CIRCUIT" WE, INTERNATIONAL STANDARD ELECTRIC CORPORATION , a Corporation of the State of Delaware, United States of America, of 320 Park Avenue, New York 22, New York, United St&tes of America, hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement *06 f 67 This invention relates to a circuit arrangement for use, though not exclusively, in an incoming signalling circuit which couples a two wire junction to telephone exchange equipment of a telephone system provided with a multi-metering arrangement of the type which uses "silent" reversals of line polarity for conveying metering pulses over the junction to the exchange equipemnt. The aforementioned incoming signalling circuit includes a current looping circuit which on the one hand, provides a path for current of sufficient magnitude to operate an outgoing signalling circuit at the other end of the junction, and on the other hand provides a high impedance to voice frequencies transmitted over the junction in order to minimize speech loading by the current looping circuit. The signalling circuit must not, however, generate harmonics v/hen the metering pulses in the form of polarity reversals are received, otherwise noise would be introduced into the voice frequency circuit. In order to achieve low harmonic generation, low-pass filter sections incorporating capacitors and inductors are used in prior art incoming signalling circuits. Because the lower end of the voice frequency band normally transmitted over the junction is about 300HZ these inductors and capacitors are of a relatively large value and are consequently large in size and somewhat expensive. Furthermore, because these large inductors, which typically have a value of 50 HENRYS, *°6l67 would introduce unacceptable distortion to DC dialling impulses transmitted over the junction by the current looping circuit, additional relay circuitry is provided in the incoming signalling circuit to switch the inductors out of the current looping circuit before commencement of dialling.

This adds to the cost and size of the incoming signalling circuit.

It is an object of the invention to provide a circuit arrangement for an incoming signalling circuit which includes a current looping circuit having a high impedance to AC signals.

It is a further object of the invention to provide a circuit arrangement for an incoming signalling circuit which does not incorporate large inductors.

It is a still further object of the invention to provide a circuit arrangement which has substantially low harmonic generation during polarity reversal.

The novel circuit arrangement of the present invention allows a relatively small value of inductance, due to the action of the circuit, to exhibit an impedance whose magnitude corresponds to an inductance of a much larger inductor. lit According to the invention in its broadest form there is provided a circuit arrangement comprising an input means across which is connected the primary winding of a trans- *°67 6? former serially connected with the collector/emitter path of a transistor arrangement comprising at least one transistor whose base circuit includes bias means by which the collector/emitter path is rendered conducting thereby providing a DC current path between said input means, wherein said base circuit further includes a secondary winding inductively coupled to said primary winding, whereby AC signal applied across said input means induces a voltage in the secondary winding which is applied to said base circuit causing the said at least one transistor to apply a feedback voltage in series with the primary winding, the phase of said feedback voltage in relation to said AC signal being so arranged that the resultant voltage drop across said primary winding is lowered by the action of said feedback voltage thereby causing the apparent impedance of the said DC current path to said AC signal to be substantially high.

In order that the invention may be readily carried into effect, it will now be described in detail by way of example with reference to the accompanying diagrammatic drawings in which: Fig. 1 is a circuit diagram of a first embodiment of the invention; Fig. 2 is a circuit diagram of an incoming signalling circuit incorporating a second embodiment of the invention.

N.Z. PATBNT OFFICE 1 C SEP 1986 RECEIVED 206167 Referring to Pig. 1 the circuit shown comprises a transformer T1 consisting of a primary and secondary winding having a turns ratio of 3:1 and a primary inductance of 2 HENRYS at 25ma. One end of the primary winding of T1 is connected to a line terminal A, while its other end is connected to the col- r " lector element of a transistor TRl arranged in a common emitter amplifier mode. The emitter element of TRl is connected to line terminal B via a current sensing resistor Rl. The . base element of transistor TRl is connected to one end of the secondary winding of transformer T1 whose other end is con nected to the Junction of bias resistors R2 and R3 whose distal ends are respectively connected to the junction of the collector element of transistor TRl and the primary winding of transformer T1 and line terminal B. 15 The following equation shows the approximate relationship between the applied DC voltage (V) and the DC current drawn by the circuit: I = V(R1+R2+R3) (R2+R3)R1 '^~20 It can be seen from this equation that the circuit behaves approximately resistively to DC with an effective resistance RE = (R2+R3)R1 R1+R2+R3.

By choosing suitable values for resistors Rl, R2 and R3 the 25 effective loop holding resistance can be set to a predeter mined value . ♦ —10 } 206167 When an AC signal is applied across line terminals A and B a voltage is induced into the secondary winding of transformer T1 which applies a feedback voltage VB to the base element of transistor TRl which feedback voltage is 180° out of phase with the applied voltage (V). As transistor TRl is operating in a common emitter mode there is a further 180° phase shift between the base signed and the resultant collector signal. This feedback arrangement causes the collector voltage to track in phase with the applied AC voltage, consequently the AC voltage drop across the primary winding of transformer T1 is kept at a low level While the impedance to an AC signal across the line terminals A and B is substantially high. To illustrate this, the normal impedance of a 2 HENRY inductance to a frequency of 300HZ is approximately 3.7K-ohms, whereas the apparent impedance of the above embodiment to this frequency is approximately 30,000 ohms.

Referring to Fig. 2 the incoming signalling circuit comprises a transformer T2 whose primary winding is coupled to the line terminals A and B of the signalling circuit via a DC blocking capacitor C2, and whose secondary winding is coupled to the voice frequency (VP) circuit (not shown); a loop/dial control relay RL coupled to control circuitry (not shown) and a modification of the circuit arrangement of Pig. 1. A polarity detection circuit (not shown) is also coupled to line terminals A and B. The modifications to the circuit of Pig. 1 incorporated in Pig. 2 comprise an additional transistor TR2 of an opposite polarity type which, together with transistor TRl, ,.i. PATSNT OFFIC£ \ 1 C SEP 1986 RECEIVED 6 206167 " ! :1 jj $ X. t .J *-• ds r+~ s — forma a complementary pair for providing a loop holding path under both normal and reverse polarity conditions. Diodes D3 and D*» respectively connected in the collector path of each transistor ensures that the collector/base junctions of the transistor do not become forward biased. The parallel arrangement of diodes D1 and D2 connected between resistor R3 and line terminal B cancel the VBE drops of transistors TRl and TR2 respectively. The feedback circuit from the secondary winding of transformer T1 to the bases of transistors TRl and TR2 incorporates a high pass filter section consisting of a capacitor CI and a resistor R4 which reduces low frequency noise during reversals of polarity.

The base circuit common to transistor TRl and TR2 includes a serially connected make contact FL1 which is operatively associated with relay RL.

The arrangements of zener diodes D5 and D6 connected across the distal ends of resistor R2 and diodes D1/D2 provide a protection circuit for transistors TRl and TR2 against transient voltages generated by dialling or external sources.

In operation, and under normal polarity, when the control circuitry associated with relay RL operates the relay, contacts RL1 close switching transistor TRl "on" thereby providing a current path to loop the distant exchange equipment via line terminal A, primary winding of transformer Tl, diode D3, collector/emitter path of transistor TRl, resistor Rl and line terminal B. Dialling impulses are provided by the aforementioned current path upon contact RL1 relaying the impulses A 206167 from the control circuitry associated with relay RL to the base circuit of transistor TRl. Upon a subsequent signal from the distant exchange equipment In the form of a reversal of polarity at line terminals A and B there is a smooth transfer _ of the current path from the collector/emitter path of tran- sistor TRl to the collector/emitter path of transistor TR2. The complementary configuration of transistor TRl and TR2 allows conduction down to +-0.6V. In the region -0.6<V<0.6 cur-rent can still flow via resistors R2 and R3. These factors, combined with the smoothing effect of the Inductance of the primary winding of transformer Tl, reduce generated reversal noise to a low level.

During conversation the current path of the looping circuit exhibits a high impedance to voice frequencies by virtue of the feedback circuit action described in relation to Pig. 1.

O N.2. PATENT OF f :;)- i o J: ; f i • i C uU t. i.j (3167 While the present Invention has been described with regard to many particulars, it is to be understood that equivalents may be readily substituted without departing from the scope of the invention defined in the claims.

I NPATL~NT Of F fCE re JUL 1986

Claims (10)

206167 What we claim is:

1. A circuit arrangement comprising a pair of input terminals across which is connected the primary winding of a transformer serially connected with the collector/emitter path of a transistor arrangement comprising at least a first transistor whose base circuit includes bias means by which the collector/emitter path is rendered conducting thereby providing a DC current path between said input terminals, wherein said base circuit further includes a secondary winding inductively coupled to said primary winding, whereby AC signal applied across said input means induces a voltage in the secondary winding which Is applied to said base circuit causing at least said first transistor to apply a feedback voltage in series with the primary winding, the phase of said feedback voltage in relation to said AC signal being so arranged that the resultant voltage drop across said first transistor tracks the AC signal In response to the feedback voltage thereby causing the apparent impedance of the said DC current path to said AC signal to be increased.

2. A circuit arrangement as claimed in claim 1, wherein said first transistor is connected in a conmon emitter amplifier configuration, said bias means comprising a first current sensing resistance means serially connected in the emitter path of said first transistor, and a voltage divider network comprising a second and third serially connected resistor means whose distal ends are respectively connected to the junction of the first resistance means and the input means and •' * x; : C^FiCE I 0SEP 1986 RECEIVED 10 206167 the Junction of the collector of said first transistor and the primary winding, the junction of said voltage divider network being connected to the base of said first transistor via the said secondary winding.

3. A circuit arrangement as claimed in claim 1 or 2, wherein said bias means further includes a controllable switch means for rendering said first transistor conducting or nonconducting .

4. A circuit arrangement as claimed in claim 3 as appended to claim 2, wherein said controllable switch means is serially connected between the second resistor means and its junction with the third resistance means.

5. A circuit arrangement as claimed in any one of the preceding claims, wherein said transistor arrangement comprises two transistors, the second transistor being of an opposite polarity type to that of said first transistor, the base and emitter elements of said first transistor each being directly connected to similar elements of said second transistor, and the collector element of said first transistor being connected via a first serially connected diode means to a common point to which the collector element of the second transistor is connected by a second serially connected diode means the polarity of the first and second diode means being such as to prevent the respective first and second transistors from becoming forward biased. | tiZ. PATENT Of FICE j 167

6. A circuit arrangement as claimed in claim 5, incorporated in a signalling circuit means for coupling a two wire junction to telephone exchange equipment of a telephone system provided with a signalling arrangement of the type which uses reversals of line polarity for conveying signals from the distantly connected exchange to the said exchange equipment, said signalling circuit including an AC signal circuit for receiving AC signals transmitted over the said junction, and a control means for controlling said controllable switch means in said circuit arrangement whose input means are connected across said junction.

7. A circuit arrangement as claimed in any one of claims 3 to fi, wherein said controllable switch means are make contacts associated with a relay means.

8. A circuit arrangement as claimed in any one of claims 2 to 7 wherein at least one second diode means is serially connected between the distal end of the third resistance means and the junction of the first resistance means and the input means, the polarity of said second diode means being such as to cancel the base/emitter voltage drop of the transistor/s.

9. A circuit arrangement as claimed in any one of the preceding claims, wherein zener diode means is connected across the collector/emitter path of said transistor/s for protecting said transistor/s from transient voltages. - 12 -

10. A circuit arrangement substantially as herein descx'ibed with reference to Figs. 1 and 2 of the accompanying drawings. INTERNATIONAL STANDARD ELECTRIC CORPORATION P.M. Conrick Authorized Agent 5/1/1223 - 13 -