NO302600B1 - Method and switching device for transmitting a data stream - Google Patents

Abstract

The invention relates to a method and an arrangement for the transmission of an auxiliary data flow (Sz) in a CMI-coded or MCMI-coded main data flow (Sb), the bit combination '10' being transmitted twice for one bit = '1' to be transmitted of the auxiliary data flow (Sz). The possible delays in the transmission of the auxiliary data bits are considerably reduced in that the first bit combination '10' can be used as a replacement for a bit combination '11' or '00'. A further reduction in the jitter is achieved by a transmitted auxiliary data bit always being passed on to the auxiliary data flow (Sz') with a constant delay after the arrival of the first bit combination '10', rather than being passed on as soon as the second bit combination '10' arrives on the reception side. <IMAGE>

Description

The invention relates to a method for transmitting a data stream i

according to the preamble of claim 1 as well as a coupling device for carrying out the method.

For digital data transmission in optical systems, a 2-level code is usually used, which compared to the 3-level code makes less demands on the transmission

and the receiving units. In the journal "Technische Mitteilungen PTT",

7/1979, page 256, it is shown that the CMI (Coded Mark Inversion) code is particularly suitable as a 2-level code for this application. Next to the generation rule for the CMI code, its advantages (high rate information, error detection possibility, code transparency, power spectrum without a share of low frequencies, simple code converter) are also described.

It appears from the generation rule for the CMI code that corresponding to the data to be transmitted, the bit combinations "11" or "00" (for a data bit = "1") or the bit combination "01" (for a data bit = "0") are transmitted to the transmission line. The bit combination "10" not used in the generation rule is used in various methods for the simultaneous transmission of another data stream,

so that a main data stream and an auxiliary data stream can be transmitted over a transmission line at the same time. The generation rule for the CMI code is therefore extended corresponding to the chosen method, which leads to a modified CMI code (MCMI code). As the binary and pseudo-ternary CMI code for the data bits "0" and "1" respectively in each case transmits one of the three bit combinations "11", "00" and "01", more often a ternary coded data signal is converted to a CMI -encoded data signal.

CH-PS 666 150 describes a method by which the concept of digital auxiliary channel for optical waveguide systems is realized with HDB-3/MCMI coding. A data bit respectively equal to "1" and "0" is transmitted on the auxiliary channel in that a selected bit pattern "110011" or "001100" is replaced by a modified bit pattern ("011011", "100111", "101101 or "001001", "000110", "010010"), which on the receiving side can again be unambiguously detected as a modification. The disadvantage of this method is that in case no data can be transmitted on the main channel, no data can be transmitted on the auxiliary channel, because the bit patterns "110011 and "001100" in CMI code does not occur when the HDB-3/MCMI converter is fed only HDB-3 coded data zeros. Furthermore, it is possible that the bit pattern "110011" and "001100" respectively, which on average occur at a high rate, only occur scattered with large time intervals. This leads to an occasional strong increase in jitter in the transmitted auxiliary data stream.

In EPO-A1 0 250 729 a method is described in which, for data bit = "1" to be transmitted, first a replacement of a bit combination "11" and then of one of the following bit combinations "00" with a bit combination "10" takes place ". This method, which allows data transmission even when no data is transmitted over the main channel, will be briefly explained in the following in connection with the transformation of the HDB-3 code into MCMI code.

In a first step, the ternary HDB-3 signal is split into two binary signals pc and nc respectively, which respectively pass on the positive and negative pulses of the HDB-3 coded signal. In a following step, the signals pc and nc are changed in such a way that a bit = "1" of the auxiliary data stream determined for the transfer, when a pulse of the signal pc occurs, a further pulse is simultaneously added to the signal nc and that on the subsequent occurrence of a pulse of the signal nc at the same time a further pulse is added to the signal pc. In a further step, the modified signals pc' and nc' are transformed into an MCMI coded signal. A possible course of the transmission of an auxiliary data bit B(n) is

indicated in the following table 1.

From lines 1, 4 and 7 of this table, it can be seen that regardless of the occurrence of an auxiliary data bit = "1", a bit = "0" of the main data stream is in each case, according to the generation rule of the CMI code, transformed into the bit combination "01". When an auxiliary data bit is missing, positive and negative pulses of the HDB-3 code are each converted to the bit combination "11" and "00", respectively. In lines 4 - 9, a possible course of an auxiliary data transfer for a bit B(n) = "1" is shown. After the transfer of the bit B(n), in line 10 the transfer of an auxiliary data bit B(n +1) = "1" starts. The auxiliary data bit B(n) = "1" is transmitted by first forming the bit combination "10" in the MCMI code for an HDB-3 signal = "+1" and then for an HDB-3 signal = "-1" (lines 6 and 9). It must therefore be observed that in the event of the auxiliary data bit B(n) = "1", a bit combination "11" expected in line 6 and a bit combination "00" expected in line 9 are replaced by a bit combination "10". Accordingly, each time the first bit combination "11" that follows a bit combination "00" and then the second following bit combinations "00", is replaced by the bit combination "10". This method thus has two disadvantages. Since the transmission of an auxiliary data bit first begins with the occurrence of one to one bit = "-1" followed by bit = "+1" in HDB-3 code, a relatively low transmission rate is obtained for the auxiliary channel. Furthermore, it is possible that the bits "+1" and the following "-1" in HDB-3 code appear very early or very late. This leads respectively to a high jitter and a fast and strongly varying speed of the data transfer over the auxiliary channel. The purpose of the present invention is therefore to specify a method and a device for carrying out the method which enables data transmission over the auxiliary channel with high transmission speed and low jitter. This purpose is achieved according to the invention respectively with a method according to claim 1 and a device according to claim 4.

The advantages of the specified method and the specified device are the increased transmission rate and the reduced jitter in the data transmission over the auxiliary channel.

In connection with the drawing, the method according to the invention and a coupling device for its implementation shall be explained in more detail in the following by means of an example. Fig. 1 shows the block diagram of a transmission system operated by the method according to the invention.

Fig. 2 shows a logic circuit LC according to the block diagram of fig. 1.

Fig. 3 shows a timing diagram for the logic circuit LC.

Fig. 4 shows a further logic circuit LD1 according to the block diagram of

fig. 1.

Fig. 5a shows a further logic circuit LD2 according to the block diagram on

fig. IN-

Fig. 5b shows the logic circuit LD2 in detail.

The transmission system of fig. 1 comprises a ternary/binary converter TB which divides a ternary coded HDB-3r signal Sb into two binary signals pc and nc respectively, which comprise pulses corresponding respectively to the positive and negative pulses of the HDB-3 signal. In the subsequent logic circuit LC, the signals pc and nc are changed corresponding to the data of the auxiliary data stream Sz to be transmitted. For a bit of the auxiliary data stream Sz to be transmitted, in that connection, for a pulse of the signal pc or nc that follows a pulse of the signals nc or pc, a further pulse is superimposed on the signal nc or pc respectively. Furthermore, at the next occurrence of a pulse of the opposite signal nc or pc respectively, a further pulse is added to the signals pc or nc respectively. The condition for imposition, which states that the first pulse of the signal pc respectively nc at which a pulse of the opposite signal nc respectively pc is superimposed, follows a pulse of the opposite signal nc respectively pc, must therefore be observed in order for the signals pd and nd on the receiving side, it must again be possible to correctly regenerate the corresponding signals pc and nc, which is important for later error-free conversion of the binary signals pd and nd into a ternary signal. In the event that bipolarity violations do not occur, as described in P. Bocker, Dateniibertragung, vol. 1, 2nd edition, Berlin 1983, p. 130, in the code of the main data stream, then this condition for imposition that prevents violated pulses from being used for transmission must of an auxiliary data bit, is not observed. In this case, an imposed pulse would under all circumstances correspond to the last occurring pulse pd or nd.

The signals pc' and nc' formed in this way from the signals pc and nc are correspondingly transformed in an MCMI coder C into an MCMI signal Sc, which after transmission e.g. over a light waveguide, decoder D is converted to the signals pd' and nd' which correspond to the signals pc' and nc'.

The structure of the MCMI encoder C and the decoder D is sufficiently known and can also be easily implemented afterwards. These links should therefore not be explained further.

In the logic circuit LD1 which receives the signals pd' and nd', the pulses pda and nda applied in the logic circuit LC to the signal pc and nc respectively are detected, removed from the signal pd' and nd' respectively and delivered to the logic circuit LD2. The above-mentioned condition for imposition now allows it to be determined which of the simultaneously occurring pulses pc' = "1" and nc' = "1" respectively in the signals pd' and nd' were imposed. According to the condition for imposition, the signal pd' or nd' which last delivered a pulse carries the imposed pulse. After the imposed pulses have been extracted from the signals pd' and nd', the logic circuit LD1 gives two resulting signals pd and nd, which correspond to the signals pc and nc, further to the binary/ternary converter BT which consequently emits the transmitted HDB-3 coded main data stream Sb'. From the separate (imposed) pulses pda and nda supplied to the logic circuit LD2, the transmitted auxiliary data stream Sz' is formed in this connection.

The one in fig. 2, the logic circuit LC shown in certain features will be explained in more detail in the following in connection with the timing diagram according to fig. 3. A pulse of the signal pc respectively nc produces at the output of the flip-flop CK1 respectively CK2 a pulse of the signal a respectively b and at the same time (the gate transition times are omitted in the time diagram in fig. 3) at the output of the OR gates COl respectively C02 a pulse pc' respective nc'. In the event that on the AND gate CU1 and CU2, next to a logical "1" of the signal a and b, respectively, there is a logical "1" of the signal b' and a' respectively and the signal z, then the OR gates COl and C02 receive the OR -gate C03 supplied with a logical "1", so that a logical "1" is simultaneously emitted at the output of the OR gates CO1 and C02. In this connection, the signals a' and b' which appear at the output of the flip-flop stage CK3 indicate which signals a and b have most recently had a logic "1" applied to them. After the occurrence of an auxiliary data bit, the signal z is set equal to logic "1" until the flip-flops CK4 and CK5 after the transmission of the auxiliary data bit are reset by the signal r. The AND gates CU1 and CU2 therefore ensure that only an additional pulse is applied to the signal nc respective pc in case the auxiliary data bit still is not transmitted and in case the logical "1" of the signal a respectively b follows a logical "1" of the signal b respectively a. The signal z is reset only after the transmission of the auxiliary data bit respectively after the occurrence of the value logical "1" twice for the signal w . After the first appearance of a logic "1" in the signal w, the output of the flip-flop CK6 is set equal to logic "1". After the occurrence of the next logic "1" for the signal w, the inverting output of the flip-flop CK7 is set to logic 0 during one clock period, whereby the flip-flops CK4, CK5 and CK6 are reset. The signals pc' and nc' are then encoded in the MCMI encoder C, then transmitted and finally in the decoder D again decoded to the signals pd' and nd'.

The one in fig. 4 shows logic circuit LD1, which supplies the signals pd' and nd', has two tasks. Firstly, the applied pulses must be detected and passed on to the logic circuit LD2. Second, the imposed pulses are to be removed from the signals pd' and nd' and the resulting signals pd and nd are output to the binary/ternary converter BT. In this connection, the non-inverting outputs of the flip-flops DK1 and DK3 are set to logical "1" by the signal pd' and a logical "0" by the signal nd' via the AND gate DU1 and the OR gate DOl at the same time. 1". On the simultaneous occurrence of a logical "1" of the signal nd' and a logical "0" of the signal pd', the non-inverting output of the flip-flop DK2 and the inverting output of the flip-flop DK3 via the AND gate DU4 and the OR gate D02 are set to logical "1". In contrast to the flip-flop stages DK1 and DK2, in the flip-flop stage DK3 the state set last by a pulse pd' or nd' remains maintained until the next pulse of the signal pd' or nd' is obtained. With the simultaneous occurrence of logic "1" of the signals pd' and nd', depending on the state of the flip-flop DK3, the output of the AND gates DU2 or DU3 becomes logic "1", which at the same time corresponds to an imposed pulse ndarrespective pda. The imposed pulse ndarrespectively pda is transmitted from the output of the AND gate DU2 respectively DU3 on the one hand to the logic circuit LD2 and on the other side as a replacement for the unimposed pulse which is blocked by the AND gate DU1 respectively DU3 to the OR gate DOl respectively D02. Consequently, the signals pd and nd are emitted from the flip-flops DK1 and DK2 and, in contrast to the signals pd' and nd', no longer have any imposed pulses. The binary signals pd and nd are finally transformed again into an HDB-3 signal in a binary ternary converter BT.

As mentioned in the introduction, the transmission rate is increased by the method according to the invention and the jitter is reduced. By one in fig. 5a, b shows logic circuit LD2 which from the supplied signals generates the auxiliary data stream Sz' to be transmitted, a further reduction of the jitter is obtained. In addition, errors in the data transmission can be detected using the circuit.

The one in fig. 5a, drawn as a block diagram, logic circuit LD2 comprises a logic module LM, a counter Z and an OR gate D03. The applied pulses pda and nd are applied to the input El of the counter Z via the OR gate D03. In this connection, the counter Z is started by the first arriving imposed pulse pda or nda. After a period of time tmax, the counter Z emits at its output Al a signal to the logic module LM, which as a result emits a bit = "1" to the auxiliary data stream Sz' to be transmitted, in the event that until the end of the period of time tmax next to the first imposed pulse pdarespective ndaalso occurred another imposed pulse ndarespective pda. In this connection, the time interval tmax is dimensioned corresponding to the maximum possible distance between two imposed pulses pda and nda. After sending the signals at the counter output Al, a reset signal is sent via the counter output A2 to the logic module LM. In this connection, the counter Z is simultaneously reset with the logic module LM, so that the logic circuit LD2 is ready for a further reception of a pair of imposed pulses pda and nda.

In the following, the logic circuit LD2 will be explained in detail in connection with fig. 5b. For two imposed pulses pda and ndarespectively nda and pda which occur within the predetermined time period tmax, the logic circuit LD2 emits a bit = "1" to the transmitted auxiliary data stream Sz'. In this connection, a counter Z is started by the first occurring imposed pulses respectively via flip-flops DK4 and DK6 respectively via flip-flops DK5 and DK7 and the OR gate D03, as the counter Z monitors that the second pulse respectively pda occurs within a predetermined time period. As a result, eight clock cycles are counted across the AND gate DU5, DU6, DU7 and the flip-flops DK9, DK10, DK11 and DK 12 and after the cycles have ceased, a logical "1" is added from the output of the flip-flop DK12 to an input of the AND- gate DU8.1 if the second imposed pulse ndarrespectively p also occurs during the counted eight clock cycles, at this point all the inputs on the AND gate DU8 are at logical "1", so that over the AND gate DU8 and the flip-flop DK8 as a result a bit = "1" to the auxiliary data stream Sz' to be transferred. At the logic "1" at the output of the flip-flop DK 12, the counter and after one to two clock periods thereafter all flip-flops in the logic circuit LD2 are reset, so that the logic circuit LD2 is ready to receive a further pair of imposed pulses.

Without the couplings according to the invention, the jitter of the transmitted auxiliary data stream Sz' is composed of the alternating delay at

the transmission of the first and second pulses. By the fact that the auxiliary data bit in the link according to the invention is always first transmitted eight clock cycles after the occurrence of the first of the two imposed pulses, the resulting jitter can be reduced in the transmission of the first imposed pulses pdarespective nda.

In connection with the used ternary code for the signal Sb and the occurring conditions for imposition, it can be calculated for the present example that the second imposed pulse pdarespective nda must follow the first imposed pulse pdarespective ndasenest within eight clock cycles. In the event that the second imposed pulse pdarespective does not appear within the counted eight clock cycles, there is an error. The logic circuit LD2 is then reset without an auxiliary data bit being output.

The clock signals ct and dt respectively used in the connection are each extracted from the corresponding main data streams Sb and Sc respectively.

Claims (4)

1. Method for transmitting an auxiliary data stream (Sz) in a CMI-coded main data stream (Sb), where the bit combination '10' is transmitted twice for a bit B(n) = T of the auxiliary data stream (Sz) to be transmitted, characterized in that before the transmission of the main data stream (Sb) becomes, for each bit B(n) = '1' of the auxiliary data stream (Sz) in the main data stream (Sb), first bit combination '11' or '00' following bit B(n) = '1' and which follows a bit combination '00' or '11' inverse to this bit combination, and a second bit combination '00' respectively. '11' which follows the modified first bit combination '11' or '00' and is the inverse of this, replaced with a bit combination '10', since after transmission of the main data stream (Sb), upon arrival of the first and second bit combination '10', it is determined whether the latter was transmitted instead of the bit combinations '00' or '11', and where, if the replaced bit combinations are inverse relative to each other ('00' and '11' or '11' and '00'), bit B(n) = '1' is supplied to the auxiliary data stream (Sz') after a time tmax from the arrival of the first bit combination '10'. 2. Procedure according to claim 5, characterized in that the time period tmax corresponds to the maximum distance between two pulses pc = '1' and nc = '1' in the HDB3 code. 3. Procedure according to claim 1 or 2, characterized in that the 2-bit MCMI-encoded signal is generated by conversion from an HDB3-encoded signal, the positive and negative pulses (pc and nc respectively) of the HDB3-encoded signal being fed as separate pulses (pc' and nc' respectively) to an HDB3 to MCMI encoder which for one pulse (pc') emits the bit combination "11" on the transmission line, for one pulse (nc') emits the bit combination "00", in the absence of the two pulses (pc' and nc') emits the bit combination "01" and upon the simultaneous occurrence of the two pulses (pc' and nc') the bit combination emits "10", and that upon the occurrence of a bit B(n) = "1" of the auxiliary data stream (Sz) to be transmitted, at the next pulse (pc or nc) that follows a pulse (nc respectively pc), together with a pulse (pc' respectively nc') simultaneously generates an imposed pulse (ncarrespective pca), and that upon the occurrence of one to the pulse (pc respectively nc) subsequent pulse (nc respectively pc), together with a pulse (nc' respectively pc') an imposed pulse (pca respectively nca) is also generated at the same time. 4. Switching device for decoding a modified CMI coded signal (Sc) with a decoder (D) which is applied to the signal (Sc) and which, when the bit combination '11' occurs, emits the pulses pd' = '1' and nd' = '0 ', with the bit combination '00' emits the pulses pd' = '0' and nd' = T, with the bit combination '01' emits the pulses pd' = '0' and nd' = '0' and with the bit combination '10' emits the pulses pd ' = T and nd' = T to a logic circuit (LD1) which includes a storage (DK3) where it is maintained which of the two pulse combinations pd' = '1' and nd' = '0' or pd' = '0' and nd' = '1' which has occurred most recently, and which by the simultaneous occurrence of two pulses pd' = '1' and nd' = '1' generates the second pulse combination which is not stored in the storage (DK3), pd = '0 ' and nd = '1' respectively. pd = '1' and nd = '0', and delivers the imposed pulse pda= '1' respectively. nda= '1' derived from the pulse combination pd' = '1' and nd' = '1' to a further logic circuit (LD2), characterized in that the logic circuit (LD2) is equipped with a counter (Z) connected to a logic module (LM), which counter is started at the first applied pulse pda= '1' or nda= T and after a time tmax emits a signal to the logic module (LM), which then emits a bit = '1' to the auxiliary data stream (Sz') if the logic module (LM) in addition to the first applied pulse pda= '1' or nda= '1' has also been added to the second imposed pulse nda= '1' respectively. pda= T before the end of the time tmax.