NO20050967D0 - Memory device and methods for operating it - Google Patents

Memory device and methods for operating it

Info

Publication number
NO20050967D0
NO20050967D0 NO20050967A NO20050967A NO20050967D0 NO 20050967 D0 NO20050967 D0 NO 20050967D0 NO 20050967 A NO20050967 A NO 20050967A NO 20050967 A NO20050967 A NO 20050967A NO 20050967 D0 NO20050967 D0 NO 20050967D0
Authority
NO
Norway
Prior art keywords
readout
memory cell
read
sequence
voltage pulses
Prior art date
Application number
NO20050967A
Other languages
Norwegian (no)
Other versions
NO20050967L (en
Inventor
Goran Gustafsson
Hans Gude Gudesen
Peter Dyreklev
Per-Erik Nordal
Isak Engquist
Original Assignee
Thin Film Electronics Asa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thin Film Electronics Asa filed Critical Thin Film Electronics Asa
Priority to NO20050967A priority Critical patent/NO20050967L/en
Publication of NO20050967D0 publication Critical patent/NO20050967D0/en
Priority to PCT/NO2006/000072 priority patent/WO2006091108A1/en
Priority to NO20060897A priority patent/NO20060897L/en
Publication of NO20050967L publication Critical patent/NO20050967L/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5607—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using magnetic storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5657—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using ferroelectric storage elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

I en minneinnretning omfattende én eller flere elektrete eller ferroelektriske minneceller, er minnecellene forsynt med multibits lagringskapasitet ved å være fremstilt med en rekke spatialt definerte områder med forskjellige koersivspenninger. I en fremgangsmåte for å skrive data til en minnecelle av denne art benyttes en sekvens av spenningspulser med forskjellige verdier for å oppnå suksessiv skrivning av hvert område med henholdsvis forskjellige polarisasjonsverdier. I en første fremgangsmåte for utlesning fra en minnecelle av denne art benyttes en lignende sekvens av spenningspulser, men i omvendt orden for å muliggjøre en suksessiv utlesning av hvert område. I en annen fremgangsmåte for utlesning påtrykkes minnecellen en lineær spenningsrampe og den resulterende utgangsstrømrespons overvåkes. I en tredje fremgangsmåte for utlesning benyttes en skriveoperasjon for å svitsje alle områder etterfulgt av en utlesningsoperasjon lik enten den første eller den annen fremgangsmåte til utlesning. I en fjerde fremgangsmåte til utlesning benyttes en sekvens av spenningsramper eller spenningspulser med forskjellige verdier og utgangsstrømresponser registreres for å skaffe en entydig signatur for minnecellen baser både på lagrede data og de dynamiske responskarakteristikker.In a memory device comprising one or more electret or ferroelectric memory cells, the memory cells are provided with multibit storage capacity by being provided with a number of spatially defined regions with different coercive voltages. In a method of writing data to a memory cell of this kind, a sequence of voltage pulses of different values is used to achieve successive writing of each region with different polarization values, respectively. In a first method of readout from a memory cell of this kind, a similar sequence of voltage pulses is used, but in the reverse order to allow a successive readout of each region. In another method of readout, the memory cell is applied to a linear voltage ramp and the resulting output current response is monitored. In a third method of read-out, a write operation is used to switch all areas followed by a read-out operation similar to either the first or second read-out method. In a fourth method of readout, a sequence of voltage ramps or voltage pulses of different values and output current responses are recorded to provide a unique signature for the memory cell bases on both stored data and the dynamic response characteristics.

NO20050967A 2005-02-23 2005-02-23 Memory device and methods for operating it NO20050967L (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
NO20050967A NO20050967L (en) 2005-02-23 2005-02-23 Memory device and methods for operating it
PCT/NO2006/000072 WO2006091108A1 (en) 2005-02-23 2006-02-23 A memory device and methods for operating the same
NO20060897A NO20060897L (en) 2005-02-23 2006-02-23 Memory device and methods for operating it

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NO20050967A NO20050967L (en) 2005-02-23 2005-02-23 Memory device and methods for operating it

Publications (2)

Publication Number Publication Date
NO20050967D0 true NO20050967D0 (en) 2005-02-23
NO20050967L NO20050967L (en) 2006-08-24

Family

ID=35229536

Family Applications (1)

Application Number Title Priority Date Filing Date
NO20050967A NO20050967L (en) 2005-02-23 2005-02-23 Memory device and methods for operating it

Country Status (2)

Country Link
NO (1) NO20050967L (en)
WO (1) WO2006091108A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103578532B (en) * 2012-08-01 2016-08-10 旺宏电子股份有限公司 The operational approach of storage device and memory array and operational approach thereof
US9219225B2 (en) 2013-10-31 2015-12-22 Micron Technology, Inc. Multi-bit ferroelectric memory device and methods of forming the same
DE102015015854B4 (en) 2015-12-03 2021-01-28 Namlab Ggmbh Integrated circuit with a ferroelectric memory cell and use of the integrated circuit
KR102599612B1 (en) * 2019-06-27 2023-11-08 브이메모리 주식회사 Controlling method for electric current path using electric field and electric device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07122661A (en) * 1993-10-27 1995-05-12 Olympus Optical Co Ltd Ferroelectric memory device
US6091621A (en) * 1997-12-05 2000-07-18 Motorola, Inc. Non-volatile multistate memory cell using a ferroelectric gate fet

Also Published As

Publication number Publication date
WO2006091108A1 (en) 2006-08-31
NO20050967L (en) 2006-08-24

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