NO162098B - PROCEDURE FOR TRANSFER OF VOICE AND DATA. - Google Patents

Description

The present invention generally relates to digital data communication and telecommunications, and in particular a method for the simultaneous transmission of voice and data in the same communication channel between two or more terminals, which terminals can preferably be PABX subscriber terminals, each terminal also includes voice - as data connections, such as a telephone and a data terminal. The invention is particularly well suited for Electronic Private Automatic Branch Exchanges (EPABX) which have the ability to process both voice and data, for transmission to the public telephone network, work terminals and intelligent terminals. Data can be used by the user at the end terminal or for control and signaling between source and destination in the voice path.

Various forms of PABX equipment have previously been known. Examples of this are shown in US patents no. 3,943,297, 4,028,498 and 4,136,263. The first generation of EPABX equipment had stored program control and used either electromechanical switching networks, e.g. in the form of coordinate selectors with crossing conductors or reed relays or electronic analog networks. These systems offered greater possibilities than those previously available with standard telephone sets by activating special codes that were deciphered by the system.

The second generation of EPABXs, which is also earlier

known, use digital switching networks that are either structured as time-space-time selectors (TST) or space-time-space (STS), which resulted in a significant size reduction. Examples of

such second generation EPABX equipment is ROLM CBX as well as Wescon digital PABX.

Today, telephone sets are being developed towards multifunctional equipment that can both provide voice communication and data transmission from a digital data interface. Thus, the telephone set is effectively developed in the direction of a digital data interface and the EPABX equipment towards a digital data link network in addition to being a standard voice network. It is therefore necessary to transmit digitized voice and data through a digital connection network. A digitized switching network capable of switching digitized voice and data through the network is described in US Patent No. 4,201,891. Another example of a switching network for voice and data is US Patent No. 4,317,962. The present invention, which may be considered a third generation EPABX technology, is capable of providing simultaneous transmission of voice and data over the same PCM channels, and is particularly advantageous in combination with digital switching networks such as that shown in previously mentioned US patent no. 4,201,891, while digitized voice and data are transmitted in the same PCM channels. However, the digitized speech and data in US patent no. 4,201,891 are transmitted sequentially, while in the present invention they are really transmitted simultaneously, i.e. within the channel time in each individual frame.

This is achieved by using a data-splitting technique where

the PCM speech transmitting data field is used to accommodate both digitized speech (e.g. from a telephone set) or other data (e.g. from a computer terminal) in the same channel within a frame that has several channels, e.g. 32, all of which contain information. This enables voice and data to be combined in a common information field and transmitted simultaneously in the same channel, frame-by-frame, through a digital connection network to other users of the system, including PABX subscribers. According to the present invention, users of the system can also individually and selectively gain access to a database system through the PABX device, so that the same information can be retrieved from the database system for several PABX subscribers or so that different information can be retrieved from the database system by several PABX -subscribers and simultaneously sent to different users in different channels. The information is transferred from the database system via the tone bus to a telecommunications system.

In order to achieve the possibility of simultaneous voice and data information connected to the same subscriber by a digital switching system such as that described in the above-mentioned patent No. 4,201,891,

it has been discovered that the remaining 5-bit of the 16-bit PCM word per channel can be predetermined for data transmission in such a way that it requires two frames to transmit one bit. The respective 5-bit and 8-bit information fields are not separated, but the complete channel is transmitted to both data and voice destinations. The equipment at the destination, which may take the form of a computer terminal or a telephone set with key operation, etc., can extract the information field that it needs. Alternatively, the data and voice fields can be separated in the PABX and sent/received from the data terminals and telephone sets in an independent manner. A system in accordance with the present invention combines

the 5-bit and 8-bit data and voice information fields in one channel, thus enabling two fields to be transmitted simultaneously to a destination such as a telephone set with a keypad and with a digital telephone.

Of course, when such a terminal does not require or allow simultaneous communication of both voice and data, the equipment could be used to communicate with other data terminals, the data using the voice channel as a transmission medium with modems, as is also currently done in the known technique. This does not prevent the simultaneous additional transmission of 5-bit data, if desired.

As an example, a four-wire termination of a digital telephone can provide a transmission path for 8-bits of digitized speech and 5-bits of data. Voice and data originating at a terminal can be switched via a digital switching network to two or more destinations independently, but combined in a 16-word PCM channel. With a digital interface, voice and data bits written from two different PCM network channels can be extracted for transmission to one and the same digital telephone.

Data can be switched to terminals from a data source via a telephone tone bus. Tonebussen provides e.g. about. 20 free channels for high-speed (64 kbit/sec.) transmission of large amounts of data when using the voice path, and 5-bit per channel per frame can be used to provide a 32 kbit/sec. serial path for up to 30 terminals at the same time, regardless of the use of the voice paths.

The main purpose of the present invention is therefore to provide, generally speaking in a telecommunications system and particularly in a PABX system, the possibility of simultaneous transmission of voice and data in the same channel between one or more user terminals.

Another purpose of the present invention is to provide simultaneous voice and data communication in a channel between several users of the system and/or several PABX subscribers.

It is a further object of the present invention to provide simultaneous voice and data communication in a channel between one or more users of the system and/or PABX subscribers and a database system.

It is a further object of the present invention to provide for several system users, including PABX subscribers, access to simultaneously send or receive voice and data selectively to each other individually or in a "broadcast" manner, i.e. spread to several users at the same time, and to provide simultaneous access to a database system so that each subscriber can receive the same or different data information from the database system at the same time over the system or the PABX tone bus together with one or more other users of the system and/or several subscribers. This is achieved by using a method in accordance with the patent claims set out below.

To provide a clearer understanding of the present invention, reference is made to the detailed description of embodiment examples below, as well as to the accompanying drawings, where

- fig. 1 is a generalized block core showing a PABX comprising the provision of simultaneous full duplex transmission of voice and data to two-port system users, - fig. 2 shows a generalized block diagram of the system according to FIG. 1 used for use by many two-port system users, - fig. 3 shows a generalized block diagram of the system according to FIG. 1 and 2, extended to a three-port system providing voice and data transmission as well as access to a database system. - fig. 4 is a generalized block diagram for 4 system users, each of which has voice and data capability, and is interconnected via a digital connection network to each other and to a database system, - fig. 5 shows a data format for combining digitized speech and data in the same channel for simultaneous transmission, in accordance with the present invention, - fig. 6 shows a block diagram for a digital interface in accordance with the present invention, - fig. 7 shows a shift register of a form which can be useful when converting data words with one bit length to data words with a different bit length, - fig. 8 shows a tone bus configuration suitable for use in connection with the present invention,

- fig. 9 shows a Channel Associated Signaling (CAS) data stream

in the voice path between CAS/data RAM and serial-to-parallel data conversion circuit, - fig. 10 shows packet data (nibble data) insertion and extrusion between the CAS/data frame and a series-to-parallel conversion circuit, - fig. 11 is a CAS-data-RAM control that is suitable for use when generating addresses and mapping the read/write control for

data transfer in and out of CAS/data RAM.

In fig. 1 shows the simultaneous transmission of voice and data in a two-port communication system. Voice and data are connected to a PABX (Private Automatic Branch Exchange) 10 from several voice and data terminals, where one of the voice terminals is shown in the form of a telephone subscriber device 12, and where one of the data terminals is shown in the form of a data terminal 14.

The telephone set 12 and the data terminal 14 are connected via two-wire lines 16 and 18 to a transmission interface 20 in the PABX 10, which is adapted to positive and negative pulses and also has the ability to recover a time pulse signal (clock). A conventional RS-232 modem for a computer terminal interface can alternatively be used for this purpose and connected in that case at each end of the line 18.

Digitized voice and digitized data are connected to the digital interface 22 to provide a full duplex communication link between the digital interface 22 and a digital switching network 24 with half-duplex connection between the transmission interface

20 and data terminal 14 as well as subscriber device 12. Alternatively, full duplex transmission can be obtained in a known manner v.hj.a. PABX 10 using the so-called "ping-pong" technique or echo cancellation technique or using 4-wire lines. The digital switching network 24 preferably comprises a distributed control network, and the details of this are described in US patent no. 4,201,889. The digital switching network 24 connects frames in channels of digitally encoded data and digitized speech from any desired subscriber or data terminal to any other desired telephone subscriber or data terminal. Fig. 1 shows in a representative way the mutual connections between subscriber 12 and data terminal 14 on the one hand and subscriber 26 and data terminal 28 on the other hand via the connection network 24. The terminal interface 30 and the digital interface 32 work in an identical way as the terminal interface 20 and the digital interfaces 22. The control circuits 34 and 36, which are described below and in the previously discussed US patent no. 4,201,889, act to establish and maintain transmission paths within the switching network 24. The control circuits 34 and 36 also contain processing capabilities that can process protocols between the digital interfaces 22 and 32 for the subscriber devices and data terminals respectively. Control circuit 34 can e.g. include an Intel 8086 microprocessor for use e.g. for detecting signaling indicating that the fork switch has been operated, and for adding ringtones as described in US patent no. 4,349,703.

With reference to fig. 2 shows a simplified block diagram for the mutual connections between several voice and data terminals to a PABX arrangement according to fig. 1. The telephone subscriber sets 1-N are connected to the analog-voice interface 100, which forms part of the transmission interface 20. The data terminals 1-N are connected to the data interface 101 of the transmission 20 Auxiliary equipment 104, which is common to the telephone line circuits mentioned above , is also shown, e.g. the ringing signal generator as discussed in previously mentioned US patent no. 4,349,703. It also acts as a keyboard interface for control/data exchange with control circuit 34. While only one plane of the transmission interfaces 20 is shown, it is understood that multiple identical planes are used in a PABX, and the use of such multiple planes in a switching network is previously known and discussed in the previously mentioned US patent no. 4,201,891. Pulse code modulated (PCM) voice and data buses are shown schematically at 106, 108 and 110 respectively, and they are bi-directional, so that each bus comprises a pair of one-way transmission paths, each earmarked for one direction of data flow . Each such one-way transmission path in connections 106, 108 and 110 leads e.g. 32 channels of digital information, time division multiplex (TDM) in bit series format. Each frame in the TDM format contains 32 channels, where each channel e.g. has 16 bits of information with a bit transfer rate of 4,096 Mb/s. PCM voice and data buses 106 respectively. 108 is connected to the digital interface 22, where voice and data are combined as described below for simultaneous transmission through the switching network 24. The keyboard interface is connected to the digital interface v.hj.a. the transmission path 110. As previously mentioned, the control processors 34 and 36 operate to set up connections through the network 24.

Reference is now made to fig. 3, where a three-port system is shown, where a voice or data system user at port 1 with subscriber device 200 and data terminal 202 can communicate selectively with either port 2 or port 3. Port 2 includes a voice and data system user at subscriber device 204 and data terminal 206. Port 3 comprises a database system comprising a data processor 208 and a database interface at 210. The processor 208 can comprise any equipment, e.g. a computer with stored program and stored data for retrieving users at ports 1 and 2. The interface 210 operates to connect the data streams directly to PCM channels, and includes a digital interface such as the digital interface 22 in accordance with the present invention and described below. Similarly, port 2 is connected via transmission interface 212 and digital interface 214 to switching network 24. Port 1 is connected to switching network 24 via transmission interface 216 and digital interface 218.

The wooden gate system according to fig. 3 is a full duplex system, where both the subscribers 200 and 204 have a simultaneous voice connection with joint cooperation over their respective data terminals 202 or 206, with a database system 208. In accordance with a feature of the present invention, both subscribers cooperate with a common database 208, so that (a) each of them receives identical data returned from the database 208, although each subscriber may send out different data , or (b) retrieves different data for each subscriber from the database. Line 220 comprises a high-speed parallel data bus. Digital interface 210 performs serial/parallel shaping, channel assignment and synchronization for 2 PCM connections at 222 and 224, such as can have 32 channels each.

"Broadcasting" or the simultaneous sending of digital information from one port to several ports is previously known and described in US patent no. 4.2 93,946. Fig. 3 shows the transmission of data and digitized voice through network 24 between ports 1 and 2 and the database at port 3. Although it is known to send out voice or data to several ports in the voice field, see e.g. US patent no. 4,293,946, the problem remains of combining data in the number of bits (e.g. 5-bit) in the data word that is used. Therefore, one must be able to get digitized speech from port 1 to port 2 and data from port 1 to port 3. This is done by "broadcasting" a single data word, which contains both digitized speech and data in a combined information field to both destinations (port 2 and port 3). At the digital interface 214 to port 2, voice is only recovered, and data is ignored (is discarded). At the digital interface 210 to port 3, only data is found, and speech is ignored. In the same way, the same technique is used to

transfer voice and data from port 2 to port 1 and respectively port 3.

However, a problem occurs with the prior art when data is to be fed back from port 3 (database system) to both port 1 and port 2 and delivered to the same terminals as transmitters. The 16-bit PCM code can be "broadcasted" in a similar way as described above, but whereby only 30% of the available bandwidth is used, to another available voice channel at ports 1, 2. Thus an additional "broadcasting" is required and combination to get an efficient system. It has been discovered that the already existing tone bus in a telephone PABX can effectively serve this purpose. Alternatively, a separate "broadcast" bus may be used just for this data purpose in addition to the pre-existing tone distribution mechanism in the PABX equipment, whatever its type, and even if such tone distribution mechanism is of a similar kind. Tone bus 230 can e.g. be a 32-channel PCM transmission link, running between each digital interface 218 and 214 to each telephone subscriber port, such as port 1 and port 2. The conventional use of a tone bus in a telephone subscriber network is to switch audio signals such as ringing, busy signal, hold- the line signals etc. so that a telephone subscriber hears the tones on the tone bus. Since each telephone subscriber can always connect to tone bus 23 0, i.e. each of the 32 channels on the tone bus can be connected to each individual telephone device, both the subscribers at port 1 and port 2 can be connected to data transmitted in any of the ports 1 and 2, and they can therefore request different data from port 3. Thus, data can simply be transferred through the tone bus 230 to different channels within the 32 channels available on time-division multiplex in the PCM data frame. The tone interface is shown in 232. It is sufficient for an understanding of the present invention that the tone generation and the transmission circuit are of a conventional type as previously used within telephony. A suitable tone bus configuration is shown with reference to fig. 8. While the database interface 210 may be similar to the digital interfaces 214 and 218, it should be understood that only data entry and data extraction are required, and therefore the digital interface 210 for database system 208 may be comprised of any known data entry and extraction equipment.

Fig. 4 shows a simplified block core for connecting 4 individual system users A, B, C and D, each of whom has voice (telephone) and data (terminal) access to a database system 208. Several channels in the frames for PCM voice - and the data connections are switched through the digital connection network 24.

Voice and data from users A, B, C and D are combined at the digital interfaces 250, 252, 254 and respectively. 256, into digital words representing speech and data and are separated on two buses 258 and 260 by the digital interface 210. The bus 258 is a digitized voice bus, while the bus 260 is a pure data bus. Voice bus 258 connects users A, B, C and D to a conference circuit 262 to provide simultaneous voice connection to all users. The conference circuit can e.g. include the conference circuit described in the previously mentioned US patent no. 4,293,946. The data bus 26 0 simultaneously connects all users to the database system 2 08 in order to be able to individually send or receive data from this. The received data can be shared data that is simultaneously sent out (broadcast) to all or some of the users, or different data for each user. The database system 208 may be an Intel 8086 microcomputer or an IBM 370, depending on the amount of data required by the users. The database system will typically have a data processing facility in addition to database access to be able to manipulate and calculate the data pattern or number representations.

With reference to fig. 5, the data format used to provide simultaneous voice and data transmission can be seen in the block diagram of the digital interface shown in fig. 6, now be explained. Format A is a 16-bit data format that is generally used in telephony and represents the PCM channel content of one of the 3 2 channels in a data frame. The bit designation is:

P = protocol 2-bit

N = spare 1-bit

S = speech 8-bit

X = data 5-bit.

It should be understood that the protocol bits P in the system described may be a SPATA protocol such as "10" as described in the previously mentioned US patent no. 4,201,891.

The transmission speed is typically 4,096 Mbits/s.

Format B is the 8-bit digital speech sampling for channel words in A. It is a digital representation of an analog speech sampling. The 8-bit digital samples are either extracted or inserted into all frames of the channels. The voice sampling is removed or inserted when the interface to the voice transmission interface from the digital interface is 8-bit x 32 channels per frame. When PCM voice bus 106 in fig. 2 contains 16-bit words, the speech samples will not necessarily have to be inserted or removed. However, the voice samples can be inserted or removed more easily on a per termination basis at voice interface 100, as described in previously mentioned US patent no. 4,201,891. The voice transmission rate is 64 Kbit/s which is derived from 8 K frames/i and 8 bits/channel per frame.

Format C shows two 5-bit data words which are alternately inserted into the data field (the X bits) of 16-bit PCM format A. Only the first 4 bits in the 5-bit data field are valid data. The additional bit (nibble bit) is used to indicate which of the removed or inserted different or equal parts of C and D are represented. The additional bit, which can be either high or low (1 or 0) is sometimes called a "packet or level indicator" (nibble indicator),

and the two 4-bit data packets that are written from the same 8-bit data word D have opposite level indicators. That is, the packet or level indicators are never both 0 or both 1 for the two packets from the same data word.

Thus, the fifth bit in each packet (nibble) C is used for framing two 4-bit packets in each 8-bit data word D. The data word D has a transfer rate of 32 K bit/s. For combined fields, the samples C are inserted for transmission through the digital switching network. For separate fields, the samples C are extracted upon receipt from the digital switching network.

Reference is now made to fig. 6, where the digital interface 22 is shown. The frames in the PCM channels for voice and data in format A in fig. 5 is transmitted to and received from the switching network 24 on the lines Tx and Rx, which are connected to a synchronization detector and a buffer 300. The PCM input from the switching network 24 is used to resynchronize all and the other inputs to the digital interfaces 22. Thus, introduction and removal of data is done in synchronism with the frame and channel synchronization received from the digital switching network 24. This thus represents a fixed time relationship between the input from the switching network 24, the operation of the digital interface 22 and the transmission via lines/connections to users via transmission interface 20 to the lines 302 (the voice bus), lines 304 (the data bus) and lines 306 (for keyboard applications). 8-bit PCM in A or B data format from the user terminals' voice bus 3 02 is buffered at the PCM buffers 308 and connected in a 32-channel A or B format to a time recovery circuit RAM 310 to recover the time course for the connection network's data frame synchronization, which is connected from buffer storage 300 over line 312 to timing recovery circuit RAM 310, timing recovery and data-tone separation circuit 314, and timing recovery and synchronization circuit RAM 316.

The time-restoring RAM circuits are memories, into which information is written in frame synchronism with the received data from the lines, and where access and reading is obtained in synchronism with the internal digital interface and its time management. Each time recovery RAM has an address counter (not shown)

which is increased by one step for each channel's time channel N, N+1, N2 .....

so that bytes comprising 8-bits in series are written into successive locations in the memory. The address counter counts to 32 and then starts again at the same frequency but with a different phase. For addresses at a speed of 2048 Mbit/s and where 8-bit data is used in series, the counter will count at a speed of 256 Kbit/s. Logic is also provided (not shown) to start and synchronize the address counter to timing for frames A or B.

An 8-bit PCM speech is introduced in a 16-bit field to complement the format used for switching and transmission. This is carried out v.hj.a. an 8-to-16-bit converter in the 8/16-bit conversion circuit 320, which is shown in FIG. 7. When channel associated signaling (CAS) or data is to be mapped in the 16-bit channel, these are read from the CAS/data RAM 322 and introduced into the PCM word stream in addition to the speech field. When channel-associated signaling is used, it is introduced into or removed from the speech field. The 16 bits are transferred to the switching network 24 over line 324, the 8/16-bit conversion circuit 320 and lines 326 of the 16-bit format channel. The CAS part of the CAS/data-

The RAM 322 has a memory field that is 8 bits wide and has 128 positions, each of 8 bits (one for each channel). The data part of the CAS/data RAM is 128 positions, each 4-bit. The operation of the CAS part of the RAM is described later. DATA is read out of the data section of the CAS/data RAM 322, half a word at a time (+ 1 indicator-

bit) added while reading, as indicated by an address counter

(not shown) which is assigned to RAM 3 22 and which receives its input from address generating read/write control circuit 328. The address counter for RAM 322 circulates through each channel. The memory map is accessed, and data is read and inserted into memory. The memory map 328 receives and stores a data pattern from the control logic 34 which, when read back locally in 328, enables data to be read/written to the DATA RAM, one at a time. channel base from the various sources. A keyboard RAM 330 is structured similarly to the CAS/DATA RAM 322 and contains 2 to 2N memory word locations (assuming separate transmit Tx and receive Rx locations), depending on the number of channels (N) of data present required to send to a keyboard. Keyboard synchronization and buffer 332 is provided with read/write control from RAM 328 in the same way as for time recovery circuits 314 and 316 and 8/16-bit conversion circuit 320. Data to be sent/received from the keyboard is written or read from the key -tour's RAM v.hj.a. control logic 34 over the local control logic 329 on the parallel control interface. The control logic 34 can be similarly read/written to the CAS RAM 322

for the transfer of information.

Data in C or D format is connected from data bus 304 via data

PCM buffer 318 to time recovery RAM 316. Data is received on data bus 304 in sequential channels in which data in 5-bit or 8-bit fields is read in at an effective bit transfer rate of 3 2 Kbit per second. Sec. per channel. When the data fields received on bus 3 04 are 8-bit long, they are converted into 5-bit fields, which include a packet (nibble) bit. When the data fields are 5 bits long, they already include this packet bit. Data is time-restored to the selector's frame sync at 316 and written into CAS/data RAM 322 as 4-bit fields, the packet bit defining an unequal or equal address in RAM.

So far, the transmission to the switching network and data entry has been described, and it has included the simultaneous transmission of data written during the first 31 channel time intervals.

Transfer from the switching network 24 to the lines and the data extraction will now be described. Data is received from the switching network 24 at synchronization detector 300 in 16-bit format, and the synchronization is extracted. 8-bit speech is extracted by 8/16-bit conversion circuit 320 and written into time recovery RAM 310 or connected directly to PCM storage 308. If channel-associated signaling or data is mapped to the particular channel, data/CAS- field extracted at 320 and written into CAS/data RAM 322. If data is routed to tone bus 334, for reception at tone port 336, the tone bus data field is extracted by the timing recovery, synchronization and data/tone separation circuit 338 and written into CAS/data -RAM 322 under control of address generation and read/write control 328. Data is output simultaneously, i.e. within the next 31 channel time intervals,

and simultaneously transmitted data is read from CAS/data RAM 322 in a 4-bit field and is either combined into an 8-bit field or remains as 5-bit (4-bit + different/equal address packet (nibble) indicator) bit), is time-restored to the output PCM bit stream at 316 and transmitted on line 308 (and other lines at other digital interfaces 22 of identical configuration to that of FIG. 6). As already specified, PCM information in connection network time management can be asynchronous in phase with all other data, which is characteristic of connection network 24, as described in the above-mentioned US patent no. 4,201,891. CAS/data input, extraction and PCM time recovery for all PCM digitized voice and data, as well as tones from connections and lines, are synchronized to PCM information received from switching network 24.

The control logic 329, which includes backplane inputs and address connection inputs for line/connection selection, and an interface to a microcomputer, and the controller 34 in FIG. 1 such as an Intel 8086, is all conventional equipment and includes standard equipment for interfacing with the microcomputer. Therefore, control logic 329 provides a path for control words from the microcomputer to set and reset words in map control RAM 328 to control data flow, effectively allowing the microcomputer to read/write to CAS/data RAM 3 22 and to keyboard RAM 330 As a standard interface between the microcomputer and the rest of the digital interface 22, the control logic 329 includes conventional register buffers, decoders, address generation and recognition registers, and control equipment for initiation.

Reference is made to fig. 7 which shows the 8/16-bit conversion circuit 320 connected to the CAS/data RAM 322 in a simplified manner. The circuit includes 8/16-bit conversion, injection and extraction of data/CAS. The circuit 320 consists of serial-to-parallel 16-bit and 8-bit shift registers 4 00, 402, 4 04 and 4 06, which ensure that serial data in is converted to parallel data out and parallel data in to serial data out, as shown. Counters scan each of channels 0 through 31 to ensure that data is routed through the registers in the correct channel. Protocol bits and NACK bits are set.

Fig. 8 shows the tone bus circuit and the distribution from the tone generation through a hierarchy of buffer stores to several digital interfaces. Tone bus 230 is a phase asynchronous 32-channel 16-bit PCM digital stream as in switching network 24. The tone bus is distributed via a hierarchy of buffer stores 500 to several digital interfaces shown as 22, 22A ... 22N, connected to switching network 24 or other desired destinations. The digital interfaces 22A and 22N are illustrative of many digital interfaces with tone buses distributed via buffers 1, 2A ..... 2N, i.e. tone buses 230, of which 2 are shown as 2 AL and 2 NM.

The tone circuit 502 consists of a digital tone generator 504 which produces digital PCM frequencies at 8-KHz per 8-bit sampling for different tones of the exchange (or PABX). These tones can be programmable in frequency, amplitude, harmonic content and other parameters v.hj.a. the controller 34, which connects instructions to the tone generator 504 and control bus 506.

An external interface 508 converts or receives external sources such as music, continuous announcements, etc. and encodes these into 8-KHz, 8-bit PCM stream. A time slot allocator 510 receives 32 channels of 16-bit PCM from the digital interface 22 under the control of control circuit 34 and injects 8-KHz 8-bit PCM samples from the digital tone generator 504 and the external interface 508 into predetermined channels of the PCM frame in the speech field . The digital interface 22 receives the 5-bit data field, as described, in PCM form from the switching network 24 and sends this data to the time slot allocator 510 which multiplexes this with the other 8-bit 8KHz inputs, to form the aforementioned 16-bit PCM words on tone bus 230.

Fig. 9 shows data from the channel associated signaling circuit (CAS)

in the speech path between CAS/data RAM 322, as well as the serial-to-parallel conversion circuit 320. The parallel-in/serial-out register 323a and the serial-in/parallel-out register 323b correspond to the registers

400 respectively 404 in fig. 7.

CAS is data entered in preceding frames of the PCM stream on a channel, in bands, so that they form a repeated sequence known in telephony as a multiframe. When the correct channel is transmitted from or received by the digital interface 22, the contents of the voice field are read from or into the CAS RAM 322. The control circuit 34 can then write or read the CAS RAM 322 to send or receive control or signaling information. There are CAS possibilities both in the connection network 24 and/or in the terminal. The same channel as the CAS channel is used for signaling into the network or towards the terminal.

A counter 600, e.g. with 5-bit, one step for each frame is increased by the frame's clock to create a multiframe data sequence of 32 frames, and this gives for reception and transmission 8 x 32 = 256 bits of signaling in each direction on lines 602,604, 606 and 608. Transparent voice transmission is enabled on other channels when the CAS channel is not received or transmitted. Mapping of the channels, if this is required, is described elsewhere. CAS RAM 322 comprises 4 sections, each of which e.g. has 32 address locations, each 8-bit. The 4 sections of CAS RAM 322 are: IA, which serves as a buffer for data from control circuit 34 to network 24; IB, which serves as a buffer for data from network 24 to control circuit 34; 2A, which serves as a buffer for data from a subscriber terminal over line 606 to control circuit 34; and 2B, which serves as a buffer store for data from control circuit 34 to a subscriber terminal over line 608.

In fig. 10 shows packet data insertion and extraction between CAS/data RAM 322 as well as serial-to-parallel conversion

circuit 323.

Data, originally in 8-bit form, is held in two 64x4-bit RAM circuits 700 and 702, where each adjacent pair of address locations in the RAM circuit contains both packet bits in the 8-bit byte, and so that the least significant bit (LSB) at the address that characterizes the adjacent address location, serves as a high-low packet (nibble) indicator.

The data RAM section of the CAS/data RAM 322 can be considered as two sections of identical sizes. DATA RAM 1, shown at 700, is used as a buffer and channel mapping from terminal to network. DATA RAM 2, shown at 7 02, is used as a buffer and channel mapping

between the data source and a terminal or terminals.

DATA RAM 7 00 has as its address for reading a data output channel, which according to the PCM channel mapping is the one that is about to be transferred to the network. The contents of DATA RAM 700 at this address are loaded into shift register 323a before the PCM channel is switched over to network 24.

DATA RAM 700 has as its address for writing the number of the channel of data received from the terminal. Thus, at the PCM network channel to be transmitted, data will be retrieved from the mapped address location in RAM 700 by the data channel address retrieved from the mapping RAM 800, described in connection with FIG. 11.

DATA RAM 702 has as its address for reading, the count that applies to the channel where data is sent to a subscriber terminal. The address for writing DATA RAM 7 02 is the data input channel number obtained from the map control RAM 800 by accessing the address location in the map control RAM 800 addressed by the channel count of the received PCM channel from network 24. Thus, data is mapped to the network channel on line 602 from the data channel on line 704 and from the network channel on line 604 to the data channel on line 706.

There are two other sources of data to be entered

in the DATA RAM 702, and these are selected as a result of the contents of the mapping RAM 800. These other data sources are tone data or free patterns used when neither network nor tone data is connected to the data terminal.

The high/low packet indicator is used as the LSB of the address for writing and reading by the RAM circuits 700 and 7 02.

Reference is now made to fig. 11, where a CAS/data RAM control circuit 328 is described. The mapping RAM 800 consists of 32 address locations with 12 bits and is accessed twice per channel time, one for the channel sent to network 24, and one for channel received from network 24. Each direction has its own address counters 804 and 806, which are reset at each frame synchronization time connecting to counters 804 and 806 on lines 808 and 808 respectively. 810. As a result of each read access to the mapping RAM 800, data read is stored in buffer registers 812 and 814, one each for output and input directions of the PCM stream.

The mapping RAM 800 also has write and read access from control circuit 34 via control logic 329, which writes the mapping pattern into RAM 800 and can read this for testing purposes. RAM 8 00 is wider than 8-bit and can therefore be addressed in two ways, at 12-bit width (32 address locations) for channel mapping and a smaller control data width, e.g. a width of 8-bit (64 address locations, 32 of which are used) for access via control circuit 34.

The mentioned 12-bit data width of RAM 800 is preferable

given the following distribution:

1 bit - select free pattern for RAM 702

1 bit select CAS channel

5-bit - data channel mapping

5-bit - tone channel mapping.

If the voice bus 302 is to have a channel mapping to the switching network PCM in the digital interface 22, this can be performed by a similar technique as described above with reference to Figures 9, 10 and 11, and by expanding the width of the mapping RAM 800 to include a voice bus channel number field.

When a channel from network PCM is to be transferred to switching network on line 602, the channel number mapped by counter 804 is addressed so that it will read out mapping RAM 8 00, loading the read data from RAM 8 00 into output control register 812. The control word in register 812 contains a CAS enable bit. If this is "on", the speech field in shift register 323a is loaded from CAS RAM la (322), which is accessible from the multiframe address accessed via multiframe counter 600. CAS is also loaded into CAS RAM 2A (322) from the terminal of the 8-bit the speech field in line 606 at the counter address of the multiframe. The data field in DATA RAM 700 is loaded into shift register 323a from the DATA RAM 700 address specified by the mapping

RAM 8 00 data channel number previously loaded into output control register 812.

When a channel in the PCM network is received on line 604 of shift register 323b, this channel number found by counter 806 is used as the address to read the mapping RAM 800 and load the address contents into the input control register 814. If the CAS enable bit is "on", CAS is read into CAS RAM IB (322) from the received speech field in shift register 323b, and CAS is also sent to the terminal from CAS RAM 2B (322) in the speech field on line 608. CAS RAM addresses are determined by multiframe counter 600. DATA RAM circuit 702 is loaded from the 5-bit field of the received PCM network in shift register 323b, if the tone data channel mapping address in input control register 814 is 0 and the bit that selects the free pattern in register 814 is not set.

Drsom the tone data channel field in the input control register

814 is not 0, tone data is read from an address location addressed by this field in a RAM located in the data and tone time recovery and synchronization circuit 314, which is shown in FIG. 6, and is loaded into DATA RAM 702 at that address in RAM

702 which is found at the address from the data channel field that was previously read into the input control register 814. If the bit indicating selection of free pattern is set, a free pattern is inserted at the mapped address in DATA RAM 7 02. This is a control that dominates over the tone data channel's field content and its implications contained in register 814.

The read/write control and address mapping 328 also contain sequences that control the various read and write accesses in fixed time frames that are synchronized to the PCM network frames, the channel timing and the clocks operating at 4096 MHz.

Although the present invention has been described in connection with preferred embodiments, it is to be understood that additional embodiments, modifications and applications which are obvious to those working within this technique are covered by the invention as long as they lie within the framework set up by the patent - the requirements below. E.g. many modes of data transmission can be achieved with the present invention, using various known transmission interfaces. These include simple termination to simple termination, data only or data and voice at the same time, for data only data can be represented by 64 Kbit full duplex in the voice field, or data can be transmitted at voice bandwidths using modems and transmitted in the voice field. For data and voice at the same time, data can be transmitted at 32 K-bit and voice at 64 K-bit full duplex using 5 extra bits in SPATA format, or if a 32 K-bit voice is used that is coded and accepted, the bit fields on respectively, 5 and 8 bits are reversed so that 64 K-bit data can be sent in full duplex. For multi-termination (^2) with or without shared database access, data can be transferred in a conference mode with the following variations: The conference circuit extracts data and performs store-and-forward, routing/switching or access/manipulation for a common database so that common data is returned to all terminations or switching and messages are performed between terminations. Full duplex paths are established between each termination on the conference circuit. For multiple terminations connected in a non-conference mode (with or without common database access), data can be transferred between two terminations with direct voice connection, and data connection via a common database so that each termination receives the same returned data from the database or alternatively so that each termination broadcasts (with a broadcasting option) the 16-bit channels of data and voice combined to both the other terminations and the shared database, as well as that shared data is returned via the tone bus which allows broadcast access on 30 channels to all terminals. Two terminations that have a direct voice connection and data connection via broadcast can be connected to one or more databases so that each termination receives different returned data.

It should be noted that the bits that are called nibble indicators in the description are called half-byte indicators in the requirements.

Claims (8)

1. Procedure for transmission of voice and data over a digital switching network (24), in particular for automatic home telephone exchanges (10) (PABX), with two or more terminals and equipped for establishing connections between several telephone sets (12) and data terminals (14), and where optionally a data processor ( 208) is connected to the digital switching network (24), characterized in that a splitting and combining circuit at each terminal is connected to a transmission interface (20) which is each connected to the digital switching network (24) via a digital interface (22) and with a control unit (34); that the data processor (208) is connected to the switching network (24) via a further digital interface (210); that the N-bit data words that are received in the transmission interface (20) and are executed as half-byte data words with a half-byte indicator (HI/LO) are written into a data store (23) in the digital interface (22) ; that the digital speech as well as a first half-byte data word read from the data store (322) and received in the transmission interface (20) are incorporated into a multi-bit word in a channel within a multi-frame and are there synchronized to the frame time in the digital connection network; that each additional half-byte data word and digital speech sampling is interleaved and synchronized on the same channel in a subsequent frame and that these frames, containing channels of speech and data, are transmitted to all terminals and to the data processor (208) over the digital switching network (24), whereby voice and data are faded out in the digital interfaces (22). 2. Method according to claim 1, characterized in that each N-bit data word is derived from two half-byte data words and that the first half-byte data word is blended together with digital speech in a frame with a different number, while the second half-byte data word interspersed with digital speech in a frame with the same number. 3. Method according to claim 1 or 2, characterized in that the multi-bit words of a channel are produced as 16-bit PCM words, whereby 8 bits are used for digital speech, at least 5 bits for digital information, while the digital data word and the remaining bits are used as protocol bits. 4. Method according to any of the preceding claims, characterized in that the data word consists of 8 bits, which are divided into two half-byte data words, each of 4 bits, with the 5th bit using different digital information and used as half-byte indicator for the current half-byte data word. 5. Method according to any one of the preceding claims, characterized in that the converter (320) in the digital interface (22) contains series/parallel shift registers (402, 404) and parallel/series shift registers (400, 4 06) for fading in and out of half-byte data words and the speech bits; that the blanked half-byte data words are read into character/data store (322) and into a synchronization store (316) for transmission over a data bus (304) to the terminal, and synchronized; that the faded out speech bits are synchronized in a further synchronization store (310) for transmission over a speech bus (302) to the terminal; that an addressing and write/read control unit (328) controls the write/read process and provides the corresponding addresses, and that these processes take place in both directions. 6. Method according to any one of the preceding claims, characterized in that the digital interfaces are fed to a tone bus (230) which is designed as a multi-channel multiplex connection, and that the N-bit data words that are put together into half-byte data words with digital voice data in one channel, is transmitted over the tone bus (230) to all terminals and to the data processor (208). 7. Method according to any one of the preceding claims, characterized in that a conference circuit (262) is connected to the digital interface (210), and that this enables a simultaneous transmission of digital data words from the data processor (208) to the terminal. 8. Method according to claim 7, characterized in that the terminals can achieve simultaneous availability to the data processor (208) over the tone bus (230); that the same information, in the form of digital data words, can be transferred from the data processor (208) to all terminals, and that different information can be simultaneously transferred to different terminals in different channels over the tone bus (230). <9-> Method according to one of the preceding claims, characterized in that the channels of each of the transmitted frames contain all half-byte data words and digital speech samples that have been interpolated in each frame during the preceding number of channel times, and that this number corresponds to the number of channels in a frame.