NO136600B - - Google Patents

Description

The present invention relates to an antenna tuner to transform the impedance of an antenna into the load resistance required for transferring power to the antenna over a range of transmission frequencies. To provide an efficient transfer of power from the power amplifier in a radio transmitter to its antenna,

antenna tuning must be provided to achieve the effective power transmission. Generally, the function of the antenna tuner is to transfer the impedance of the antenna to the load resistance required for the power amplifier output stage of the transmitter power amplifier.

The provision of an automatic antenna tuner for a light-weight combined transceiver, such as a battery-powered portable radio transceiver, can present many difficult problems due to the need for rapid tuning and low power consumption to match the individual antennas of a majority. The difficulties are not limited to a single problem area and include physical control of the tuning elements required for high power transmission, which elements are not easily adaptable to the requirements of small volume and light weight equipment. Another problem area is enabling the use of more than one antenna, which imposes additional requirements on the tuner in that the tuning elements must be larger and a larger number of elements are required to include the additional parameters and wide frequency bands while maintaining sufficient resolution to meet the necessary antenna impedance matching requirements. In particular, as the reactive tuning elements become larger to provide adaptation of individual antennas, higher RF voltages develop in the tuner which in turn increases the physical distortion of the elements. Moreover, the requirements for the tuner become even stricter as the frequency range increases. At higher frequencies for example, an improved resolution is required in the tuning elements to provide the very small amounts of reactance required to provide effective power coupling between the power amplifier and the antenna.

By satisfying the previous requirements for greater reactance values and greater number of elements, and by protecting against the higher RF voltages due to physical distortion of the elements, further problems are introduced, namely that strb inductance and capacitance become a serious problem at higher frequencies where the strb impedance can become large enough to mask the antenna parameters and thereby make it difficult or impossible to find the correct tuned or resonance point which is below the permissible VSWR level. Furthermore, the automatic tuning must be carried out with a limited power supply available for mobile equipment. Consequently, the tapping of power to initiate the automatic tuning process must be limited to what is available from light weight and small volume power sources.

Full automatic operation of the tuner provides a desirable advantage in itself. Furthermore, the automatic operation should be completed within a minimal time period for tuning for rapid transmission of the signals, in practice it has been found that the desirable time period for tuning should be less than 10 seconds. One of the commonly used known tuners consists of a rotary switch containing combinations of fixed reactive elements.

The limited number of necessary combinations of inductors

and capacitors, that is, individual tuned circuits, and the time period required to insert each of the tuned circuits is longer than brittle, that is, substantially in excess of 10 seconds.

In many automatic tuning devices previously known, a certain method is used for preloading the antenna. This is necessary because of the wide frequency range for any given antenna, or if the same tuner is to interface between and provide tuning for more than one antenna. As the frequency range becomes large, the number of reactive elements increases, especially at the lower frequencies. This bending is required over the larger antenna impedance range while maintaining sufficient resolution to achieve the desired high degree of impedance matching detected by VSWR filters, eg 1.5:1 or less. However, if the number of switched elements is too large, the tuning time increases rapidly and the line losses also increase, which limits the maximum tunable frequency.

The radio frequency power level developed in a tuner can become a problem when fast switching devices and miniaturized packaging are used in the tuner design. During the transmission mode, high voltages are developed across the reactance tuning elements and across the switching devices for insertion or removal from the tuning circuit and at the present time most solid state switches are not capable of operating at these high voltages. ,

In the preferred embodiment of the automatic tuner of the present invention, a fully automatic tuner is provided which is adapted to nearly any of 5 different antenna configurations, for example, to the output of the transmitter power amplifier. The antenna matching network for the tuner is a T-network arranged in a low-pass configuration having latch-type relays with a fast response to selectively introduce inductances or capacitors to form an L-network to vary the reactance values of the input and shunt branches of the T-network which include the preload inductive elements. Digital control circuit enables selection of relays for introducing the individual reactive elements in the network and preload section. The fast response of latching relays enables activation and insertion of the elements in less than 3 milliseconds (3 msec). The power required for tuning is minimized and as soon as a tuning condition is reached, all primary power is removed from the tuner. A VSWR detector provides information relative to the tuned condition that has been reached and remains operative during all transmission intervals. The monitoring of the tuner by. using the VSWR detector also prevents hby effect during a transmission period should a mismatch occur

in the tuner, for example due to a change in the position of the combined transmitter/receiver.

As mentioned earlier, the use of a digital logic circuit enables high-speed selection of tuning elements having binary values by means of latching relays. The relays selectively introduce in turn the elements of the L-matching network to control the reactance values which are relative to each other in a binary sequence, which are given by individual counters for the inductances and capacitances which are introduced simultaneously.

Individual phase and load rectifiers are provided to detect voltage and current variations of the transmitted signal to provide positive and negative determinations with respect to phase and

.impedance above or below the loo ohm or 5o ohm impedance references. The loo ohm reference is provided to select eh proper fbrloading reactance for biasing the selected antenna below 5o MHz of the wide frequency range of 2 to 8o MHz. The preload device consists of a rotary switch that is changed as a result of

the deffler outputs and shifting continues until a reactance is selected, the L-matching network gives an antenna input impedance of approximately loo ohms. After the proper bias impedance is obtained, the phase and 50 ohm impedance load-eliminator outputs provide logic level outputs to direct the relay control logic circuit to insert and remove both the inductance and capacitance elements in a binary sequence in The L matching network to give the correct combination, out of 2 x lo^ possible combinations, for' in that

minimum a 1.5:1 VSWR operating condition.

The selected method of control of the tuning circuit elements requires two inputs, that is, phase and impedance inputs which indicate the reactive state of the selected antenna. The phase input is provided by the phase eliminator which supplies a digital signal to the logic control circuits to switch capacitors in the antenna impedance matching network.

The second control circuit responds to the detected impedance provided by the load shunt, which directs the logic control to switch the inductors in the antenna impedance matching network.

The phase and impedance control circuits are quasi-independent and are able to operate simultaneously to reduce the tuning cycle time. Since the inductive and capacitive elements are converted into value digitally, the logic control is operated in a binary count-

, sequence, that is, individual counters for inductive and capacitive components control the switching for insertion and removal of the individual capacitors and inductors in the impedance matching network.

In the very high frequency (VHF) band from 5o to 80 MHz, antenna impedance matching is greatly simplified by equipping a separate impedance matching network with fewer inductive and capacitive elements that correspond to the need for reactance when matching the antenna impedance at these higher frequencies . To reduce the effect of strb inductance and capacitance, the VHF impedance matching network is isolated from the HF impedance matching network, and in view of the smaller number of reactive elements required, the control sequence for tuning in lbpet is simplified by a substantial smaller time interval than that required for the high frequency range.

Digital development of a tuning algorithm provides a significant improvement with regard to automatic antenna tuning. Furthermore, the dual-deflector (phase and impedance) algorithm is far less complicated than a single de-deflector algorithm, that is, the dual de-deflector does not require any analog-to-digital conversion, for example, and results in approx. 9o% less power consumption during a tuning cycle.

Considering the foregoing, it is an object of the present invention to provide an automatic antenna tuner having the foregoing features and advantages.

Another object is to provide antenna tuning automatically to overcome the need for an experienced and trained operator of radio transmitters.

Another object of the present invention is the provision of digital logic circuitry for the control of an antenna matching network.

A further object of the invention is to provide an improved automatic tuner for reshaping the impedance of an antenna to the load resistance required for efficient transfer of power from the power amplifier to the antenna.

Yet another object of the present invention is to provide a high speed automatic antenna tuner for a portable transmitter.

Another object is to provide an antenna tuner for automatically tuning any selected antenna over a wide band of frequencies.

A further object of the present invention is the provision of individual reactances which are converted in value digitally and which are arranged in sequence to provide a maximum number of possible combinations which are available in a minimum period of time and with minimal logic control "interface" equipment.

A still further object is to provide a reduction in power required for tuning a portable radio transmitter.

Another object of the present invention is the provision of automatic selection of the correct biasing reactance required in an hby frequency band.

A further object is to provide continuous monitoring of the tuning status during transmission to detect conditions that affect the antenna impedance and resulting transmission efficiency.

A further object is the provision of independent and simultaneous attenuation and control of phase and impedance of the antenna impedance components which includes independent logic control for the respective components.

Other objects and features of the invention will be apparent from the subsequent patent claims as well as from the following description of a preferred embodiment of the invention with reference to the drawings. Figure 1 is a circuit diagram of a VSWR detector of the preferred embodiment of the present invention for detecting the voltage standing wave ratio to initiate and control the duration of a tuning cycle. Figure 1a is a diagram of a phase eliminator of the preferred embodiment for phasing the reactive component of the antenna coupling network and providing control signals for tuning to eliminate any unusually large reactive antenna component. Figure 1b is a circuit diagram of a load rectifier for detecting the antenna impedance components to control the inductive reactance in a tuning cycle in the preferred embodiment of the present invention. Figure 1c is a timing diagram illustrating the operation of the series of gates shown in Figure 1a. Figure 2 is a simplified schematic diagram of the automatic tuner in a preferred embodiment of the invention. Figure 3 is a schematic diagram of the preferred embodiment to show, by block diagram, the circuits for high frequency (HF) and very high frequency (VHF) antenna impedance matching networks and the de-attenuators and control logic circuits thereof. Figure 4 is a block diagram of the very high frequency VHF control logic device for controlling the VHF impedance matching network shown in Figure 3. Figure 4a is a timing diagram to illustrate the operation of the

VHF control logic device as shown in Figure 4.

Figure 5 is a block diagram of the high frequency (HF) control

logic device to control the HF impedance matching network and the biasing inductance for transmission frequencies in the high frequency range and as shown in Figure 3.

Figure 6 is a schematic diagram showing certain details of the interconnection of counters and relays as illustrated in the block diagram of Figure 5. Figure 7 is a logic schematic diagram showing details of the L and C detectors as shown in the block diagram of Figure 5. Figure 8 is a detailed logic schematic diagram illustrating the preload control logic device as illustrated in the block diagram of Figure 5. Figure 8a is a circuit diagram of a preload position detector circuit for applying control signals in the following frequency range in the t-?f band to preload detector as shown in block form in Figure 8. Figure 9 is a detailed logic schematic diagram of the hby frequency control logic device shown in Figure 5. Figures 1, 1a and 1b illustrate these schematic phase and impedance equalization circuits for automatic to disable the antenna parameter that includes selected antenna frequency preload requirements. In general, these circuits provide broadband coverage of the frequencies from 2 to 80 MHz for antennas of largely different impedance and each having significant impedance fluctuations over the band of frequencies, for example varying impedance characteristics in the range from 60 ohms to 1500 ohms around 26 MHz for 1.83m and 2.74m rod antennas. Two of the detuning circuits, the phase and load detuners as shown in Figures la and lb, provide independent and simultaneous detection of impedance and the phase antenna parameter to provide digital control signals for individual control of logic circuits controlling capacitive and inductive tuning elements respectively. The VSWR monitors the antenna voltage standing wave ratio (VSWR) for starting and ending tuning cycles,

for transmission in the frequency range of the broadband frequency^coverage.

Fblgéiig ef the branching circuits in figures 1, lay and 2a calculated on

to detect selected antenna conditions at the selected operating frequency to provide feedback control signals for controlling logic circuits for digital sequence arrangement of reactive components for tuning. To further satisfy the need

for rapid tuning over a wide range of frequencies > for example 2 MHz to 8o MHz, the tuning is carried out by parallel sequencing of passive and inductive tuning elements in the high frequency (HF) band of 2-5o MHz. Phase and load aff were me in figufehé lay and lb åhålyséfef independently the impedance and the phase components of the Selected antenna and provide separate control signals to the logic kbntfoll circuit for simultaneous frequency-matching arrangement of capacitors bg inductoféf in the tuning circuit to provide one tuned state at the transmission frequency.

As shown in figures 1>, low-power low-power carrier signals were connected to each of the outlets on a transmission line lb which is coupled to an RF amplifier requiring one 500 output irradiance for broadband transmission. - the frequency range of 2 tii 8o MHz. The transmission line terminations are preferably located within a minimal length of the line so that the sample input signals follow across the frequency range. Overall, the circuit and amplifiers maintain minimal losses to cover the broadband frequency range. The technical equipment includes, for example, one coaxial cable that has a length of 1.27 cm with a voltage outlet and toroidal transformers that are placed within the length of the cable. On the basis of the wire-siftition lihje taps and interruptions located in the minimum line length, the sampled voltage follows over the frequency range due to minimal change in tap or voltage level that directly affects the line current and the fblsability of the output outputs.

In Figure 1, the VSWR rectifier is provided with two outputs, namely the 3:1 and 1.5:1 outputs from respective operational amplifiers 12 bg 14, each of which is supplied with voltage and strbm samples of the transmitted signal at the respective voltage and tone formers - connector to the transmission line lo. The coupling transformers 16 and 18 are of opposite polarity to provide samples of forward and reflected current signals. The signals from the switching transformer 16 and a DC voltage tap 17 are combined to produce a positive detected voltage corresponding to the forward transmission signal on the transmission line lo. The signals from the second pair, the coupling transformer 18 and the voltage tap 19, are combined to provide a positive detected voltage corresponding to the reflected transmission signal on the transmission line lo. The diodes 2o and 21, in combination with their respective associated load resistors, provide the positive detected voltage on the respective lines 22 and 23 for the sample of the forward and reflected signal.

An AC filter is provided using capacitances 24 and 25

which is connected to ground as shown to provide positive DC signals to the VSWR eliminator.

The derived forward signal on line 22 is applied to the positive inputs of the two DC operational amplifiers 12 and 14 and the derived reflected signal on line 23 is applied to the negative inputs. Each positive input of the two operational amplifiers includes respective voltage dividers 27 and 28 to adjust the threshold level of the respective amplifiers. Filtered voltage supplies of +5 and -5 volts are connected to the amplifiers as shown and the outputs

is limited by diodes connected to output lines 29 and 3o.

The operational amplifier 14 provides 1.5:1 VSWR output whereby the higher level of the control signal indicates a standing voltage waveform ratio (VSWR) of 1.5:1 or less for termination of the tuning cycle. As long as this 1.5:1 output remains at the lower logic level (ov), the tuning cycle will continue as controlled by digital control circuitry in response to the phase and impedance eliminator outputs as described later.

The second control signal output from the operational amplifier 12,

on output line 29, provides a low logic level control signal indicating the voltage standing wave ratio (VSWR) greater than 3:1 which can be used to signal the operator to start the new tuning cycle or alternatively can provide a start signal for to initiate a reconciliation cycle.

In figure 1a, the circuit for detecting the phase of the antenna impedance is called the phase rectifier which derives voltage and strbm (voltage) signal samples from the transmission line at the voltage tap 31 and the strbm transformer 32. As in the VSWR rectifier in figure 1, a carrier signal with low power (for example 2 watts) to

provide deffbler input signalf. The voltage samples taken at the outlet 31 for the transmission line lo are applied undetected to the phase arrester in figure la and are also connected to the load arrester in figure lb after detection. As also discussed in connection with the VSWR eliminator in figure 1, the transformer 32 is connected in series with the transmission line lo to extract a sample or probe to detect any phase of the antenna reactance by means of the phase eliminator in figure 1a and applied also the load-disconnector in figure 1b after detection.

In the phase eliminator of Figure 1a, the signal supplied by the transformer 32 is capacitively coupled through an isolation network 33 to a series of three non-OR gates 34. These gates 34 and the remaining gates shown in Figure 1a provide fast rise times and constant amplitude pulse waveforms over the full frequency range of operation. A gate of this type is made by Motorola Semi-conductor Division as "MECL III" gates.

The other inputs to the phase eliminator are the voltage probe supplied from the voltage tap 31 which is connected into the phase eliminator through a constant load network 35. This voltage probe is then connected to a gate device comprising the nor-or gates 36 and 37 to provide a fixed delay, which delayed signal is applied to the input F of a summing gate 38.

The timing diagram in Figure 1c illustrates the operation of the series of gates to derive a pulse output from the summing gate 38 in response to signal samples obtained from the transformer 32 and the s<p>énning tap 31. As shown by the third column of waveforms, indicated + 0 (inductive), a positive pulse 4o is generated at the output H of the summing gate 38 only when the transformer signal test A is after the voltage take-off test B to give a positive pulse train at the output H of the summing gate 38 (figure la). The letters A-G are also shown in figure la as inputs to certain of the ports in the network. Thus, when the transformer and the voltage signal samples are in phase,

as shown in column 1 of Figure 1c, or a negative phase angle is present between the sample signals or test signals, as shown in column

2 in figure 1c, no pulse output is produced at the output H of the summation port 38. A pulse train therefore only occurs from a positive phase angle and preceding or following signals correspond to the antenna appearing either inductive or capacitive and the detection of the inductive state produces the pulse train at the output H. The output of the summing gate 38 is applied to the clock input CK of the flip-flop 42 which has interconnected J-K inputs which provides a pulse output Q at half the input pulse rate. While the pulse rate is reduced, the circuit gain is turned to control a driver stage 44 which is AC connected to the output Q. The output of the driver stage 44 is applied + the input of a DC operational amplifier 46 with hby gain and which has a - input which is connected to a. threshold adjustment to compensate for individual circuit parameters and to closely position the threshold level at o°. The positive input of operational amplifier 46 integrates the pulse train input to provide the digital output signal as shown, in which the high logic level (+5v) indicates a capacitive antenna load (-0) and the low logic level (ov) indicates an inductive antenna load (+0).

The operational amplifier 46 has hby gain and is used for rapid transition from capacitive to inductive levels, that is to say occurs within + or -6° around in phase or o° the phase differential over the broadband frequency range. As noted earlier, the transmission mains taps and interruptions are located at a minimal line length, for example preferably 1.27 cm and less than 1.91 cm, to enable sampling signals from the transmission line lo following over the frequency range 2-80 MHz. Any change in loss or voltage level directly affects the linearity and reliability of the amplifier outputs.

In figure 1b, the load rectifier is supplied with test signals from the voltage outlet 31 and the transformer 32 on the transmission line lo. While the phase rectifier independently analyzes the phase angle of the antenna load, the load rectifier in Figure 1b responds to the sample signals from the transmission line lo to analyze the impedance component of the antenna load under the phase conditions to provide a separate control signal to the inductive sequential logic device for the introduction of inductive elements including tuning transformers in the T matching network shown in Figure 3 including the biasing section of the T network.

The input circuit of the load disconnector detects the transformer and voltage tap signal. The two signals are diode-detected in opposite directions by means of the diodes 48, 49 in the input circuit 50, which detected signals are summed in a common load 52. The voltage level at the adjustable outlet 53 of the load resistor is applied to the opposite inputs of a double DC operational amplifier 54 which includes amplifiers 56 and 57. The voltage from outlet 53 is applied to the input of amplifier 56 to provide a digital output having a high logic level (+5v) indicating an antenna load of less than 50 ohms and a low logic level (ov) which indicates an antenna load greater than 5o ohms. The 5o ohm output is a command signal that is applied to the inductive sequential logic device in the high frequency (HF) digital control circuits (Figure 3).

The voltage level at the outlet 53 is applied to the + input of the amplifier 57 to give a digital signal at the loo ohm output whereby the high level signal indicates an antenna load greater than loo ohms and the lower level signal indicates an antenna load of less than loo ohms. This digital signal from the loo ohm output is a command signal from the load eliminator to the preload control circuits (Figure 3) of the antenna tuner. The negative input of amplifier 57 is connected to a threshold adjustment circuit 58 to provide a shifted base whereby circuit operation can be precisely adjusted to detect a loo ohm impedance and provide a change in level at the output at loo ohms.

The time period required for tuning is kept to the minimum possible by the application of automatic tuning of the antenna parameters and any preload requirement. Parallel detuning of the phase and impedance parameters using individual detuners significantly reduces the tuning cycle, including an average preload tuning time interval of 1/2 second and an L-matching network tuning time interval of 0.8 seconds, or a total average time period of one tuning -cycle in 1.3 seconds.

At the present time, the reduction of the time period of the tuning cycle is limited primarily by relay activation time and

as solid state devices become available which can tolerate the resonant power conditions, the tuning cycle time period will be significantly reduced.

One of the more important features of the present invention is the wide frequency range for the deflection circuits, and in particular that the monitoring of the antenna reactances continuously provides a fast flat response over the full frequency range which enables close tuning to voltage standing wave ratio (VSWR) of less than 1.5:1. Likewise, independent and simultaneous tuning and control of the real and reactive antenna components reduces the tuning cycle time by approximately 5o%. In addition to having the individual rectifier circuits, from the two independent phase and load rectifiers whose operation is quasi-independent, separate logic control circuits are obtained to control the inductive and capacitive tuning elements.

In Figure 2, the simplified schematic diagram shows the configuration of the present invention which includes an RF input connected to the output of the radio transmitter phase and impedance eliminators in the input control logic device, an antenna matching T-network and multiple antennas selectively connected to the antenna matching network. The impedance matching of any antenna of said plurality of antennas over the high frequency range is provided with fast tuning and low power consumption by parallel de-phasing of antenna phase and impedance to provide command signals for individual digital control circuit for inductive and capacitive tuning requirements. The impedance matching networks for respective frequency ranges include series-inductive and shunt-capacitive elements in an L-configuration

tion. Both inductive and capacitive elements are step variable ■

in binary value and is varied using digital control of latching relays to switch component values for inductors and capacitors in a binary sequence.

Briefly, the tuning operation for VHF consists of, for example

allowing inductive elements to step through the range of binary inductance values continuously as the capacitive value changes one step at the end of each inductive cycle. On the other hand, for HF, the inductive and capacitive elements are staged by means of parallel sequential arrangement via separate control circuits: In figure 3 a more detailed diagram of the present invention is shown by means of block and circuit schematic diagram in which the combined transmitter/receiver circuits, which include the radio transmitter,

and the power amplifier therefor, is illustrated by means of a block 60 having an output connected to a transmission line lo to provide the RF input to the antenna tuner system of the present invention. The RF signal connected to the transmission line lo provides carrier inputs to the sweepers by means of voltage and transformer connections as shown in Figures 1, 1a and 1b, and the line lo is selectively connected to either high frequency (HF) antenna matching T- network, which includes biasing inductance or the very high frequency (VHF) antenna impedance matching L network. by means of movable switch contacts SKI-1,2 which are activated by means of the relay Kl according to the frequency range of the signal being sent. That is, a frequency detector 62 provides a digital output in accordance with the frequency range in which a high level output activates the relay Kl at the set input to connect the transmission line lo with the selected antenna of said plurality of antennas 64 via T- the matching network which includes the biasing inductance and via the L matching network by means of a low level output which inverts to activate the relay Kl at the reset input. The relay K2 reacts to the input signal at the input PL to provide isolated tuning of the preload for tuning

of the L portion of the hby frequency matching network. In the activated position of Kl, the RF signal is applied to the high-frequency matching network, bypasses the series-L circuit and the parallel-C circuit, and connects directly to the bias selector switch operated by a bias motor 66.

In the preferred embodiment, the frequency detector 62 responds to a transmitted signal in a frequency range of 2-5o MHz to select the high frequency (HF) matching network and responds to the VHF frequencies of 5o-8o MHz to select the VHF impedance matching network. The relay Kl positions the movable contacts SKI-1,2 to connect the transmission line lo with the VHF L matching network.

The individual control logic circuit responds to the command signals at the outputs of one or more of the amplifiers for the introduction or removal of inductive and capacitive elements in the respective circuits. The use of digital logic devices enables high speed selection of inductive and capacitive tuning elements by means of latching relays having contacts SLl-SLn and SCl-SCn, controlled by HF control logic device 68 and contacts SVL1-SVC4 controlled by VHF -the control logic device laughed. Separate bias control circuits 72 are provided for the HF frequencies and respond to command signals from the phase and load eliminators to provide an output to the bias motor 66 to drive the bias switch to selectively engage any of 32 inductors and matching transformers which are connected between respective pairs of contacts of the preload switch 74.

In operation, high frequency transmission (2-5o MHz) is connected to the rectifiers, and one of the outputs of the VSWR rectifier is connected back to the transmitter power amplifier to control the output level to 2 watts during the tuning cycle, and at the end of the tuning cycle , when the ratio is 1.5:1 or less, the power amplifier is allowed to increase the power to 5o watts from the low level of 2 watts. For example, the transmitter is provided with an automatic gain control in which the low level 1.5:1 output of the VSWR suppressor controls the gain to the lower power level of 2 watts during the tuning cycle.

The low power RF signal is coupled via the moving contact SKl-1 to the hby frequency matching network which is set to the HF position by relay Kl as a result of the hby level output from the frequency detector. Assuming a standing bblge ratio for the voltage greater than 1.5:1, a high level output is applied to the relay K2 to position the movable contacts SK2-1 and SK2-2 to connect the bias directly between the transmission line lo and the antennas 74, as the high-frequency L-matching network is bypassed to isolate preload tuning from the L-matching network. The bias motor 66 responds to a pulse output from the bias control output to step the movable contacts of the switch 74 to sequentially introduce inductances and tuning transformers connected between the contacts of the motor-driven switch 74, which has 32 positions for example, for. selection of the correct preload reactance.

The first function of the tuner is therefore to select the correct biasing inductance by connecting the transmission signal past the L network to the biasing inductance. The bias motor 66 steps the bias rotary switch 74 through the positions until the correct inductive impedance level of loo ohms or stbrre is detected at the loo ohm output of the load breaker.

After the correct bias inductance has been introduced into the tuning circuit, the loo ohm output from the load shunt goes to the higher level to indicate that the antenna load is loo ohms or less. If, in addition to detecting loo ohms or stbrre, the phase eliminator output is low to indicate an inductive reactance condition and not a capacitive reactance condition, the preload portion of the cycle is complete and relay K2 is reset by the change in level to move contacts SK2-1 and SK2-2 to the lower position connecting the hby frequency L matching network in the tuner circuit. At the beginning of the L network tuning cycle, the HF control logic device causes all the inductive elements LI-Ln to be removed from the L network by means of closed contacts SL1-SLn which shunts the inductive elements LI-Ln. At the beginning of the tuning cycle after preload, all capacitive elements Cl-Cn are also connected in shunt to provide the maximum capacitive state. As a result, all of the following variations in inductance vary the impedance magnitude while the variations in capacitance change the phase angle of the RF signal connected to the selected antenna. Subsequent load shunt outputs provide a change in inductance by introducing inductive elements while the shunt outputs decrease capacitance by removing capacitive elements as described more fully below. However, as there is some interplay between the inductive and capacitive elements L and C in corresponding impedance magnitude and phase as the proper tuning condition is approached, a change in any one of these various elements may cause the other to fire past. Thus, the control logic device can remove or insert an element to again approach the desired 50 ohm impedance level and o-phase condition.

Therefore, after the preload sequence, the L network tuning sequence is initiated with none of the inductive elements LI-Ln in the circuit, and all the capacitive elements Cl-Cn (C = C^^, L = . Since the VSWR rectifier monitors the antenna load , the tuning sequence will continue until the vsWR squelch output imposes a high logic level on the HF control logic 68. To achieve the desired ratio, a load and phase squelch output is connected to the HF control logic which directs the input and the removal of the reactive elements to achieve o° phase angle and 5o ohm impedance. In general, the tuning sequence involves decreasing the capacitive reactance in the L network and bending the inductive reactance until a tuning condition is reached. Since the values are binary, the step increment is carried out using a binary sequence that includes insertion and removal to increase or decrease reactance.

When the transmitted signal is in the very high frequency range, the frequency detector 62 provides a low level output which is inverted to activate relay K1 at its reset input to include the very high frequency (VHF) L matching network at the location of moving contacts SK1-1 and SK1-2 to complete the circuit from the transmission line lo to the selected antenna of the plurality of antennas 64. In the very high frequency range of 5o-8o MHz, no preload sequence is desired or necessary, and the tuner is operated directly into the tuning -the sequence in which connectors SKl-1, SK1-2 isolate the VHF, L matching network from the HF network. In the VHF, L network, contacts SVL1-4 shunt all the inductive elements VL1-4 and contacts SVCl-6 are open to

shunt all capacities VC1-4. The VHF control logic in block 70 is shown in greater detail in the block diagram of Figure 4.

In Figure 4, the VHF control logic device consists of a VHF-L counter 74 and a VHF-C counter 75 having binary counter outputs VL1-VL4 and VC1-VC6 for controlling inductive and capacitive relays KVL1-4, KVCl -6 which are connected to the respective outputs. Relay contacts SVL1-4 and SVCl-6 are activated in binary sequence to progressively increase the inductance value to advance the capacitance value by one step at the end of each inductance conversion.

The L counter 74 has a clock input connected to the VHF clock key

CK3 which supplies clock pulses at intervals To-T15 as illustrated in the timing diagram in Figure 4a. The VHF tuning sequence is relatively simple in view of the small number of reactive elements required to provide the desired match to the antenna load. The relay-controlled inductive bg capacitive elements are measured through their values in binary steps, that is, the L-counter 74 responds to each of the transmitted clock pulses from the source CK3.

The step binary value sequence inductive elements in various combinations provide 16 steps of inductive reactance value in the VHF tuning circuit for each step of capacitive reactance generation. Unless a tuned condition occurs before the last count of the L counter is reached, a terminal count output is produced which connects

to the input of the C counter to override any previous count,

for example, the first count introduces capacitive element VC1

by activating the relay KVCl at the setting input. As illustrated using the timing diagram in Figure 4a, the L counter responds to each clock pulse from clock source CK3 to step the counter through 16 counts and on the 16th count (interval T15) the terminal count output (CCV) is connected to the C counter to

provide the first step offset of the C counter.

In operation, the tuning cycle is initiated by operation of a tuning switch which provides an output indicated in Figure 4a by means of the bbl shape SW which is applied to the tuning power supply control relay located in the tuning power supply 76 shown and described in the detailed logic diagram below. It is also desirable to provide circuits to delay the start of counting until the circuits have stabilized after the tuning power supply of the applied power to the clock, counters and other circuits shown in Figure 4. One of these circuits is the count open- the flip-flop 77 which is set at a predetermined time interval after the detuning switch SW has operated, for example 10 milliseconds (ms) delay. The count open flip-flop output CE is applied to the L counter to open the counter to respond to clock

the pulses applied to the clock input. This open signal CE is also applied to the C counter to open the counter for the terminal count LTC at the end of each pass through of the L counter (time T15).

In response to the first clock pulse after the opening of the L counter, the first count output VL1 is raised to the high logic level to activate the relay KVL1 at the set input which in-

lines the lowest inductive element in the VHF matching network for the tuning circuit.

During the tuning cycle, the VSWR filter monitors the antenna load impedance and an output ratio of 1.5:1 or less will provide a high logic level signal at the input VT of logic gate 78 to couple the clock pulse CK3 to provide a reset pulse at the input of the count open flip-flop to provide a low logic level output CE to halt the L and C counters. The reset pulse is also applied to the tuning power supply to remove tuning power from the tuning circuit. The output from gate 78 is connected through a non-or gate to provide the reset pulse. The non-OR gate also has an input connected to the AND gate 79 which has

. terminal count inputs LTC and CTC from L and C counters 74 and 75, respectively. Concurrent high logic level terminal counts indicate that all possible LC combinations have been exhausted without debuffing a tuned condition of 1.5:1 standing bblge ratio for voltage that would otherwise be provided by the VSWR debbeler which debuffs a tuned

state under reconciliation. The abnormal condition produces a high level output and is indicated to the operator by controlling the output of port 79 if necessary.

In continuing the description of the operation from the first count of the L-counter, it is assumed for the purpose of explaining the operation that no tuned state is reached on the first count, and that the L-counter responds to the second clock pulse to give a high logic level output on the counter output VL2 and the counter output VL1 is returned to a low logic level. The L counter will continue to respond to clock pulses supplied by clock CK3 to provide a binary

' count at the outputs of VL1, VL2, VL3 and VL4 until a tuned state is reached or all combinations of L and C are exhausted. Since corresponding inductive elements VL1, VL2, VL3 and VL4 advance in binary value, 16 steps of inductive reactance are provided from the inductive reactance value of the lowest inductive element VL1 to the sum of the inductive reactance of VL1 to VL4. on receipt of the last count, the L counter provides the terminal count LTC at its output, which is connected to the C counter to introduce

capacitive element VC1 by providing a high logic level on the corresponding counter output VCl. In this way, the L counter is effective in sequencing the inductive elements for each capacitive reactance provided by the capacitor elements which are sequentially fed from the tuner circuit by means of the C counter outputs VCl-VC6 which provide a binary count at the outputs. Since the six (6) capacitor elements are stepped in binary value, the binary counter outputs from the C counter will provide a range of capacitive reactance corresponding to

with the range of inductive reactance to achieve a tuned condition for the antenna selected from the plurality of antennas 64 as shown in Figure 3.

The use of multiple relays enables a greater number of reactance values to be inserted into the L matching network of the tuner circuit. In order to maintain operation within the specified low-power consumption limitations, latch-type relays have been provided which require power only during -a short activation time of 2 ms. These "relays KVL1-•KVL4 bg •K^G'l^iKVC6 'ef able to withstand high voltages on Iboov (RMS) and higher. The current-carrying capacity of the contacts ef •approximately '2 amp RF strbm. The locking relays are located inside a standard hermetically sealed package of a type referred to as a half crystal box configuration.

•approximately 1.5 picof arad (pi*).

In fig 5 ef :dig'itåi:é kbritfbii^krétséf f bf f orbéla s t ning L/T bg HF tuning shown by means of schematic block diagram. Details of the logic device are shown by means of the circuit diagrams in the figures

6-9 which have named circuits (surrounded by dashed lines) which correspond to the blocks in Figure 5. The operation sequence for the tuner cycle for high frequency transmission in the 2o-5o MHz range is initiated by manual start break command that sets or resets one latch in the block, start command, which has start outputs connected to preload command logic, power control switch, and Tmax timer block to initiate the prestart sequence for tuning cycles . The power control circuit applies power to the resistor control circuits in response to the starting circuit, which power is controlled after the completion of the tuning cycle by means of the stop logic circuit. The latter is possible for a 1.5:1 VSWR output signal. onen 'of fullfofels one of the tuning cycle, where the time fbfIbpet exceeds the maximum time interval ;(Tmax) or one "error in fbbbelastnihgs matching, that is - after all 32 choices of preload inductance éf have been counted and one preload hing -detector block not tfiar detected an inductive ($) loo ohm antenna impedance-able. The sequence stop logic can also respond to a Cmin condition of failure to match the high frequency L/C of the matching network. The logic circuits for these states are indicated in detail in figure 8 which also shows the schematic

diagram for the preload control circuits.

The preload clock generator provides the preload clock pulses TS1 and the clock signal selection pulses TS1JK provided by a J-K flip-flop in response to the clock pulses. The signal selection pulses TS1JK are available at half the clock speed and after the clock pulses (eg trailing edge) to control the logic gates for generating motor pulses MTRPLS to the preload pulse counter and the preload motor according to the states of the clock pulses TSI. The signal selection pulses TS1JK also control the output of the preload detector by alternating clock pulses TSI.

To satisfy the bias logic conditions, the bias L/T inductance must not only provide an inductive (ø) load of Jloo ohms, but the bias L/C rotary switch 74 (Figures 3 and 8a) must be located at the appropriate group of contact positions including group positions 1 to 5 designated for a tapped transformer for the 21-5o MHz frequency range and group positions 6-32 designated for individual inductors for the 2-2o MHz frequency range. The preload L/T switch position 32 is intended for the inductor group but does not actually include any inductor

for a minimum inductance position corresponding to the HF network shunt, where the relay Kl is activated to remove the bias L/C and the HF matching network and insert the VHF, L matching network

using connectors SKl-1 and SK1-2. In Figure 5, the HF position provides the frequency input with a high logic level indicating that the rotary contact for preload L/C switch 74 is placed in the correct group of contact positions for the selected frequency range in the high frequency band, that is say as shown in Figure 8a, group 6 to 32 for 2-2o MHz or group 1 to 5 for 21-5o MHz. The movable contact 8o is positioned automatically with frequency selection connecting ground to the opposite group, of contacts, for example, contact 8o connects ground to contact group 1-5 to provide a high logic level to contact group 6-32 for tuning in frequency range of 2 to 2o MHz, as shown.

The bias detector responds to high logic levels including 0 sensitivity, Ibo ohms and HF position frequency (output), when the correct bias L/T inductance is selected, to control the bias clock TSI and. the signal selection clock TSlJK. through a non-AND gate to reset a flip-flop in the preload command logic block (Figures 5 and 8) to provide the preload complete output, U to the L-C preset logic device to perform high-frequency L-C impedance matching the adaptation network (figure 3) by means of parallel sequential arrangement of binary indicated inductors and capacitors which are inserted and removed by means of locking relays which. is connected to the outputs.' of respective L- and C-counter rev Hbyfrequency-L-C-impedance-matching.the network is actively introduced into the antenna tuning circuit by. resetting the relay K2 (figure 3); which is shown in a simplified manner in Figure 3 as activated by inversion of the input EL. As shown in Figure 8, the "tune in" and "tune out" drive outputs are provided in one. alternating device: for reset and. setting inputs respectively for the relay K2.

As illustrated in Figure 5, the L-C upside-down logic control operates the L-counter and the C-counter in parallel, shifting the counters by steps to match the antenna impedance to a real antenna impedance of 50 ohms, for example. To this end, logic inputs 5o ohm and 0 are provided to the logic control block to control the step shift of the L and C counters and generally to decrease the capacitance which is first reset by STOS to maximum capacitance (Cmax), and increase the inductance, which is reset using STOS to minimum inductance (Lmin).

As shown in the logic diagram in figure 9, the input <J> is pressed

on port 9o together with clock pulses TS2 from the L-C clock generator (Figure 5). The output from the gate 9o is inverted and connected to the J-K inputs of the flip-flop 92 which is set (master to slave) by means of the clock signal selection pulses JKCP which follow each of the TS2 clock pulses. A capacitive state of the antenna impedance provides a high level input (J> from the phase eliminator (Figure 1a) to provide a high level output from the Q output of the flip-flop 92 to the non-AND gate 94 which has its output connected to the countdown input CCD of the C counter (Figure 5).The other input of gate 94 is provided by controlled clock pulses TS2 which are passed by means of the non-and gate 95 of the L-C counter open circuit which is provided only after the preload sequence is completed, that is, in response to the outputs U and also the motor pulse stop output MTRST (YY) An inductive state of the antenna impedance provides a low-level 0 input to

providing a high-level Q output from flip-flop 92 to gate 96 which passes clock pulses to the count input CCU of the C counter. Gate 96 has three inputs and is stopped by a low level Cmax input, ie open when the C counter is not at a maximum count. The C counter control logic device allows for either counting up or counting down at each clock pulse TS2 except when counting is prevented by a maximum capacitance. The non-AND gates and inputs therefore to provide Cmax and also the gates for Cmin and Lmin are shown in Figure 7. The C counts in response to controlled clock pulses TS2 at the counter inputs CCD or CCU, that is Q (TS2) for countdown and Q (TS2) Cmax for countdown.

The L counter control logic is responsive to the 50 ohm output of the load eliminator (Figure 1b), which output is connected to input port 98 to control the state of flip-flop 99 to provide a fast logic level at output Q or Q for count-up LCU or count-down LCD respectively, for the L-counter to arrive at an afblt inductive impedance of 5o ohms. A common blocking line to ports loo and loi blocks counting of the L counter under preload described earlier in connection with the control of the C counter. After the preload sequence is complete, the clock pulses TS2 are passed to the inputs of gates loo, loi to provide a

clocked pulsed output to either the up or down count input of the L counter.

At the beginning of the L-C tuning intervals, the L-C counters provide maximum capacitance and minimum inductance to approach antenna impedance matching. This method avoids false resonance conditions which occur at certain frequencies for many antennas when the adaptation is initiated by means of minimal capacitance. The present invention provides a sequence to overcome load-shedding indications of low impedance at maximum capacitance by enabling blocking of the inductance at maximum capacitance (Cmax) and minimum inductance (Lmin), that is, by blocking the count-down output at the gate loo by blocking the input to this from the non-or port lo2 which has.an Lmin input. The other input to gate lo2 is from the Q output of flip-flop 97 which blocks the output for an L count at minimum inductance (Lmin) and maximum capacitance (Cmax), which is connected to flip-flop 97's reset input from the non-and port lo3. On

JL oUU OU

at the same time Cmax, Lmin-(hbyt level) the output of the gate lo3 which is connected to reset the input of the flip-flop 97 provides an hby level Q output which opens a non-and gate lo4 to pass clock pulses TS2 to the non-OR gate lo5 to provide another source of count pulses for the L-counter to overcome a possible low-impedance cut-off condition which tends to cause the L-counter to count down at the beginning of the L-C sequence of the tuning cycle . The pulse output on port lo4 is connected to the counting input LCU which will increase the inductance to quickly overcome this condition. As soon as the capacitance is reduced from maximum by the countdown of the C counter, in response to a -0 exceeding capacitance condition, a true impedance condition will be detected by the load shunt and this maximum capacitance auxiliary control logic device is no longer needed in the strbm reconciliation cycle. In the absence of the auxiliary control logic device for the L-counter, repeated countdown inputs to the L-counter are produced by means of the port loo which causes unwanted operation of the relay KLI

which is shown in Figure 6 to be connected to the L-counter binary output LI.

As shown in Figures 5 and 6, the L counter outputs Li-Ln are connected to relays KLl-KLn, and the C counter outputs are connected to relays KCl-KCn to provide parallel sequential arrangement of fixed inductive and capacitive elements having values arranged in binary sequence to increase the inductance and decrease the capacitance of the antenna impedance matching network with the sum of the L and C counters. The individual digital control slbyfs for the counters are in parallel and respond to respective phase, 0 and load deffblers to control the up or down count of the L and C counters respectively until the inductance and capacitance of the impedance matching network exhibits the correct antenna impedance for the transmission at any chosen frequency in the hby frequency range, for example 2 to 5o MHz.

The condition of zero (o) phase angle and 5o ohm impedance as shown

will result in a standing wave-turn-ratio (VSWR) output of 1.5:1, indicating a system tuned condition that will provide a high logic level VT input to the sequence-stop logic device (Figure 8) to open its and- gate to pass clock pulses TS2 to provide output VTI and operate the "one-shot" via the not-or gate. The "one-shot<u>output is connected to the reset winding of the power control switch to disconnect the tuner power to complete the tuning cycle.

The output VTI is connected to the set input of the flip-flop 1 L-C counter open device (Figure 9) to provide a system-tuned output for 11 system-tuned "indicators" of the combined transceiver and to block up or down counts. -the outputs of the L and C counters by blocking the non-AND gate which has other inputs J, TS2 and MTRST.

The preferred embodiment of the system tuning device includes many features resulting from the operation of the tuner over wide bands of frequencies with antennas of the following types: 4.57m, 2.74m and 1.83m rod antennas, 91.4m wire antenna and half-wave dipole antenna. The relay-controlled reactances are also arranged in binary values and selected using the binary outputs given for the maximum number of possible combinations of reactances achievable in a minimum time interval and with a minimum of control circuits. Furthermore, the system arrangement provides separate antenna impedance matching networks for high frequency (eg 2 to 5o MHz) and very high frequency (eg 5o to 8o MHz) ranges to reduce tuning time for very high frequencies while providing biasing reactance , selection and tuning required for high frequencies, and the bias reactance associated with the antenna reduces the standing wave ratio for the

the relay-controlled reactive elements, i.e. to have a sufficient tuning range to tune at high frequencies.

At high frequencies, the tuning time is kept as short as possible by using automatic attenuation of the antenna parameter and preload requirements. In practice, it has been found that the maximum preload cycle time, when required, is approx. 1.5 seconds and the average time is 0.5 seconds. After the preload sequence, the maximum time required to provide HF L-C tuning is 1.5 seconds and the average tuning time is 6.8 seconds. At higher frequencies, the total tuning time is less than 1 second, and the average total tuning time is b.3 seconds. The tuning of the system is primarily limited by relay activation time, and as solid-state devices become available, the replacement with solid-state switches capable of switching and carrying the power requirements will further reduce the tuning cycle time. When tuning at high frequencies with relays, the effect of strb shunt capacity may limit the tuning range and isolation is provided to reduce any strb capacity. The provision of broadband de-embedding circuits is important to enable monitoring of antenna reactances continuously while also providing fast flat response over the entire frequency range for close tuning to a standing bblge ratio of less than 1.5:1. Independent and simultaneous de-embedding and switching the real and reactive antenna components further reduces the tuning time by about 5o%. This is done as shown by having two identical logic control circuit breakers, one controlling the inductive and the other controlling the capacitive tuning elements. The inputs to these circuits are obtained from two independent phase and impedance rectifiers.

The reconciliation cycle is therefore only initiated if the standing bblage ratio, such as offset, is outside the acceptable limits, for example 3:1. Upon determining that the standing wave ratio is greater than 3:1, the preload switch assembly, indicated by the reference numeral 74 in Figure 3, is cycled by the preload motor 66 controlled by the preload control circuit 74 and stopped at the first position at which a loo ohm impedance crossover occurs and where the phase angle appears inductively +0. After the preload sequence, the HF control logic device 68 cycles the relay-controlled inductive and capacitive elements through their values in binary steps simultaneously as controlled by the phase and impedance eliminators. The HF control circuits require a zero (o) phase angle and an antenna impedance of 5o ohms. As the phase and impedance approaches in the L-C combinations, providing a standing bblge ratio of less than 1.5:1 yields the VSWR output of 1.5:1 to terminate the tuning cycle, disconnect the tuning power, and provide an output for reducing the transmission power to a high level.

The basic tuning algorithm discussed includes many improvements as discussed in the preferred embodiment, and the relay-control matrix and decouplers can be simplified or combined in any configuration as needed for the particular tuning requirements of the system in question.

Thus, the system automatically switches to high-power transmission without tuning if the standing bblge ratio is. within the specified limits at the time when the reconciliation cycle is initiated. If, on the other hand, the standing bblge ratio being determined is outside the limits, the reconciliation cycle is initiated. Normally, the combined transceiver is equipped with a tuning switch, such as the microphone cable, and tuning is completed at the time the operator starts talking because of the short time interval of less than 3 seconds required for the tuning cycle. In the event that a tuned condition cannot be achieved that satisfies the limits of the standing bubble ratio, the cycle is terminated and an indication is provided to the operator that the system has not been tuned. Also during supervised transmission, if the standing beam ratio exceeds the permissible limits, a command line is energized to signal to the operator.

In the light of the above-mentioned teaching about the preferred embodiment which is discussed, various modifications and variations of the present invention are also included, which will be obvious to those skilled in the art without deviating from the idea and scope of the invention. Many of these variations have been discussed and it was noted that the particular application of the present invention to very particular applications often determines the arrangement for simplifying the cycle of operations.

Claims (26)

1. Antenna tuner for transforming the impedance of an antenna (64) into the load resistance required to transfer power to the antenna over a range of transmission frequencies, characterized in that said antenna tuner consists of: an impedance matching network (HF, VHF, figure 3) which includes a plurality of reactance elements (LI—, Cl—) stepped in value to provide reactive steps for selective adaptation of the antenna impedance over the range of transmission frequencies, switching means (SL, SC, SVL, SVC) to selectively connect the reactive elements to the antenna to transform the impedance of the antenna to the desired load resistance for transferring power to the antenna during transmission, digital control means (Figure 3) to provide a control circuit including impedance attenuation means (Earth-rectifier, load-rectifier, figure 3) to detect the impedance of the antenna including the reactance elements connected to the antenna to form said adaptation gs network to provide a digital output, and where said control means further include logic control circuit means (68, 7o) which are connected to said switching means and which react to the digital output to thereby activate said switching means to selectively connect the reactance elements to form the impedance matching network from a combination of reactances which provide the desired load resistance for transferring power to the antenna at a selected frequency over the range of transmission frequencies. 2. Antenna tuner as specified in claim 1, characterized in that said reactance elements are changed in value in binary steps to enable selection of a combination of reactance values for matching antenna impedance to the desired load resistance for power transmission to the antenna. 3. Antenna tuner as stated in claim 1, characterized in that said digital control means includes decision circuit means (VSWR, Figure 3) for automatic tuning cycles including means for detecting the tuning of the antenna impedance to provide a control output for controlling the initiation and duration of a tuning cycle according to a desired impedance match to the antenna. 4. Antenna tuner as stated in claim 3, characterized in that a transmitter power amplifier (6o) is connected to said tuner and said control input is connected to said power amplifier to control the level of the power transmission to provide low transmission power during the tuning cycle. 5. Antenna tuner as stated in claim 3, characterized in that said determining circuit means includes a standing wave ratio detector (VSWR, figures 1, 3) connected to the tuner to detect the ratio between forward and reflected standing waves over the area of transmission frequencies. 6. Antenna tuner as specified in claim 5, characterized in that said range of frequencies includes a wide band of frequencies from approx. 2 MHz to 8o MHz. 7. Antenna tuner as stated in claim 3, charac- characterized in that said alignment includes a power source (6o, Figure 3) for said alignment and that said determination circuit means is connected to the tuning power source to control the power supply to the tuning tuner for the duration of any tuning cycle. 8. Antenna tuner as set forth in claim characterized in that it further includes a plurality of antennas (64) which include antennas having different antenna impedances adapted to be selectively connected to said impedance matching network. 9. Antenna tuner as stated in claim 1, characterized in that said majority of reactive elements in said impedance matching network comprises respective groups (HF, VHF) of reactance elements and said control means comprises circuit pins (68, 70, 72) which are individual to said groups of reactance elements for selectively connecting the respective groups of reactance elements to form the impedance matching network from a combination of reactances from respective groups. 10. Antenna tuner as stated in claim 9, characterized in that said control means includes individual closed slbyfe control circuits (figure 3) for controlling the respective groups of reactance elements in a tuning cycle. 11. Antenna tuner as stated in claim 10, characterized in that said detuning means includes phase detuning means (Figure 1a) which are responsible for the phase of the transmission of any selected frequency to provide an output to said logic control circuit means (68, 72, Figure 3) for controlling the reactance of the matching network to thereby provide a phase angle of approx. o°, and load shedding means (figure 1b) which are responsible for the impedance of the network of the transmission to provide an output to said logic control circuit means for simultaneously controlling the reactance of the matching network to provide a predetermined load impedance with a phase angle of approx. o°. 12. Antenna tuner as stated in claim 11, characterized in that said impedance matching network comprises a group of capacitive reactance elements (Cl-Cn) and a group of inductance-reactance elements (LI-Ln), and that said control -means include the individual closed slbyfe control circuits from said phase shedding means and load shedding means to respective capacitive and inductive element groups for automatically controlling the phase and impedance of said impedance matching network. 13. Antenna tuner as stated in claim 12, characterized in that said group of inductive elements are connected in series and said group of capacitive elements are connected in shunt in said antenna impedance matching network. 14. Antenna tuner as stated in claim 12, characterized in that said groups of elements are binary stepped in value and said logic control circuit means includes means for selecting elements in a binary sequence to control the reactance of the respective group. 15. Antenna tuner as stated in claim 14, characterized in that the group of reactive elements in impedance silent the matching network is reset at the start of the tuning cycles to include predetermined reactance in the network. 16. Antenna tuner as set forth in claim 9, characterized in that said control means includes determination circuit means (VSWR, figures 1,3) which have means for defiling predetermined combinations of reactance in response to transmission at the selected frequency in order to control the initiation and duration of the antenna tuning cycle. 17. Antenna tuner as stated in claim 1, characterized in that it further includes a bias-reactance network (74) which includes a plurality of bias-reactance elements and switching means for sequentially selecting said elements, and where said control means includes means for automatically detuning the range of antenna impedance for selection of a desired bias reactance in a bias tuning sequence. 18. Antenna tuner as specified in claim 17, character! cert. in that said control means further includes switching means (K2, SK2-1, SK2-2) to isolate the biasing reactance network from the impedance matching network to independently select a biasing reactance for tuning in combination with the impedance matching network which includes the selected bias reactance. 19. Antenna tuner as stated in claim 18, characterized in that the control means includes means (72, Figure 3, Figure 8) for automatically terminating the preload sequence by de-energizing a preload impedance which gives an antenna impedance in tuning -range of the desired antenna impedance using the impedance matching network. 20. Antenna tuner as stated in claim 1, characterized in that it further includes a transmission line (lo) for connecting a transmitter (6o) to said impedance matching network, and ratio loss means (VSWR, figure 3) connected to said transmission line for detecting the standing wave ratio for the transmission, said ratio derating means including threshold means (14, Figure 1) which is sensitive to a predetermined standing wave ratio for the transmission to provide an output to said logic control circuit means for terminating x tuning - the cycle. 21. Antenna tuner as stated in claim 2o, characterized in that the aforementioned f includes upper threshold means (12, Figure 1) responsive to a predetermined upper standing bblge ratio to provide an output to indicate the degree of antenna tuning. 22. Antenna tuner as set forth in claim 1, characterized in that said logic control circuit means includes means (Tmax, figure 5) which react to predetermined states of tuning for ending an antenna tuning cycle prior to the completion of antenna impedance matching for transmission via said antenna. 23. Antenna tuner as stated in claim 22, characterized in that said network includes a variable preload reactance (L/T) which varies said preload reactance in a preload sequence and that said logic control circuit means includes means ( figure 5) for timing said preload sequence in an antenna tuning cycle for terminating the antenna tuning cycle after a predetermined maximum time period on said sequence. 24. Antenna tuner as set forth in claim 5, characterized in that said standing wave ratio detector provides wide-band suppression of standing wave ratio of signal transmission, where said detector comprises: circuit means (12, 14) for combining said voltage sampling of forward and reflected signals, comprising a dual operational amplifier (12, 14), wherein individual amplifiers of said dual amplifier include circuit means for providing adjustable threshold levels (27, 28), wherein the level of one of said amplifiers is adjusted to give a logic level output signal for a high standing wave ratio and where another of said amplifiers is adjusted to give a logic level output signal for the opposite low standing wave ratio. 25. Antenna tuner as stated in claim 1, characterized in that said impedance decoupling means includes a phase decoupling circuit (figure la) to detect the phase of the signal transmission, where said phase decoupling circuit comprises: circuit means (31, 32) to sample undetected voltage and current of said signal transmission having a capacitive or inductive phase angle, a reference circuit (33, 35) comprising at least one logic gate circuit (34) for receiving one of said probes to provide a pulse output and a delay circuit (35) in including a plurality of logic gate circuits for receiving the other of said samples to provide a pulse output, a summing logic gate circuit (38) which carried inputs (G, F) to receive and combine therein the pulse outputs from said reference and delay circuits to provide a pulsed or constant output that changes with the phase shift from capacitive to inductive load defined by the reference and delayed signals at the inputs of the summing circuit, and output circuit means (44, 46) for receiving the measurement of the summing circuit and having an adjustable threshold, said output circuit being adjusted to provide a threshold corresponding to the transition between capacitive and inductive phase angles to provide logical levels for respective phase angles of the signal transmission. 26. Antenna tuner as stated in claim 1, characterized in that said impedance-debugger includes a load-impedance-debugger (figure 1b) for broadband signal transmission, where said load-impedance-debugger includes: circuit means (31, 32, Figure 1a) for individual sampling of voltage and current of a modulated carrier signal which is transmitted, combining circuit means (52, Figure 1b) comprising comprises means for detecting and combining detected voltage and strbm probes, and a dual operational amplifier (56, 57) comprising individual amplifiers having adjustable threshold levels, one of said amplifiers (57) being adjusted in threshold level to provide logic level signals for a predetermined high-impedance load condition and another amplifier (56) which is threshold-level adjusted to provide logic level signals for a predetermined low-impedance load condition.