NO125997B - - Google Patents

Description

Integrated semiconductor circuit board.

The invention relates to an integrated semiconductor circuit wafer with regions of monocrystalline semiconductor material separated from each other by polycrystalline regions, which wafer has a monocrystalline semiconductor substrate with one type of conductivity, growth site regions for polycrystalline development located in selected regions on one side of the substrate, at least one region with the opposite type of conductivity on the said side of the substrate and in one of the areas not covered by the growth site areas, and a vaporized, continuous layer of semiconductor material deposited on the said side of the substrate, which forms the areas of polycrystalline material at the growth sites, and which form the monocrystalline areas in the areas on the aforementioned side of the substrate which are not covered by the growth sites.

In integrated semiconductor circuits, adjacent components must be isolated from each other, as is well known in the art. This isolation has previously taken place by means of p-n junction insulation, dielectric insulation, air insulation, "beam lead" or by means of similar methods. When the insulation takes place by means of p-n junctions, insulation areas are formed by means of diffusion techniques, which requires a significant time for diffusion, and the diffused insulation areas between neighboring components further constitute a limitation with respect to the density of the components. This leads to a difficulty in the high frequency characteristic as a result of parasitic capacitances caused by connections, electrodes and insulation transitions.

The purpose of the invention is to provide an integrated semiconductor circuit that utilizes polycrystalline areas for insulation of circuit components. More specifically, monocrystalline and polycrystalline areas are formed using vapor deposition techniques on a monocrystalline substrate, the contaminant concentration being chosen to lie below a particular value in order to increase the specific resistance of the polycrystalline areas significantly above the specific resistance of the monocrystalline areas, and nearby circuit components are isolated from each other by means of such highly resistive polycrystalline areas.

According to the invention, a semiconductor circuit board of the type indicated at the outset is provided, which is characterized by the fact that the semiconductor material of the continuous layer has a conductivity-determining type of impurity in a concentration of o 10 12 -10 17 atoms/cm 3 , so that the polycrystalline areas have a higher specific resistance than the monocrystalline regions.

The invention will be described in more detail below with reference to the drawings, where fig. 1 shows a curve for explaining the invention where the specific resistance for polycrystalline and monocrystalline semiconductors is shown as a function of the contaminant concentration, fig. 2A - 2E show greatly enlarged side views of a number of steps which are included in the production of an integrated semiconductor circuit according to the invention, fig. 2F is an equivalent circuit diagram for that of FIG. 2A - 2E showed integrated circuits, fig. 3A - 3F show steps in the manufacture of a modified embodiment of the invention and fig. 4 is an electrical connection diagram for the one in fig. 3 showed semiconductor integrated circuits; fig. 5 is an equivalent circuit diagram with respect to insulation, FIG. 6A - 6F and fig. 7A - 71 show manufacturing

step by other modifications of it. present invention, fig.

8 is an electrical connection diagram for the one in fig. 7 showed integrated semiconductor circuits, and fig. 9A - 9F show steps in the manufacture of a further modified embodiment of the invention.

The invention is based on the discovery of a new property in monocrystalline and polycrystalline semiconductors, which property will be described in detail in the following.

So far, different properties of monocrystalline

and polycrystalline semiconductors have been clarified, but in the work that forms the basis of the present invention, it has been discovered that monocrystalline and polycrystalline semiconductors, when doped with an impurity, exhibit very varying properties with respect to specific resistance, depending on its pollution concentration, as can be seen from fig. 1.

In fig. 1, the abscissa represents the concentration of the doping impurity or just the impurity concentration in atoms/C cm 3 , and the ordinate represents the specific resistance in ohm-cm. Curves A and B show the specific resistance as a function of the contaminant concentration for polycrystalline and monocrystalline semiconductors that have been doped with arsenic. The vertical lines that intersect the curve A show the range of dispersion of experimental values and the curve A<1> shows the lower limit of the dispersion. The contaminant concentration at which the specific resistance of the polycrystalline and the monocrystalline semiconductors is the same is referred to here as the critical concentration Cc. With respect to the spread of the specific resistance in the polycrystalline semiconductor, in this case the contaminant concentration at the intersection of the curves A' and B is designated as the critical concentration. The characteristic curves shown in the figure were obtained using the following procedure. Monocrystalline silicon semiconductor substrates, containing arsenic in different concentrations in the form of contamination, were produced and polished to a mirror finish using a known method, and then rinsed. A polycrystalline silicon layer was then formed, containing an amorphous layer, to a thickness of approx. 1 u on one side of each substrate at a temperature of 550°C using evaporation. The polycrystalline layer was to serve as a growth site for polycrystalline development in the subsequent production of monocrystalline and polycrystalline areas by means of the evaporation method. To form the polycrystalline layer, silicon tetrachloride was packed in the chamber of a known evaporation device together with arsenic trichloride in the necessary amount to make the contaminant concentration in the polycrystalline layer equal to the monocrystalline semiconductor substrate's contaminant concentration. Then the polycrystalline layer that had formed on a surface of the semiconductor substrate, removed in a selected area to expose a portion of the monocrystalline semiconductor substrate surface. Then, silicon tetrachloride with the above-mentioned necessary amount of arsenic trichloride, was quickly over the semiconductor substrate with a carrier gas, e.g. hydrogen, to form a vaporized silicon layer with approx. 20 [in thickness on the uncovered substrate and on the aforementioned polycrystalline layer, which served as growth sites at a temperature of 1150° C. At this point, the evaporated silicon layer consisted of a monocrystalline silicon semiconductor region, i.e. a monocrystalline layer formed on the uncovered monocrystalline semiconductor substrate , and a polycrystalline area, i.e. a polycrystalline layer formed at the polycrystalline growth site. The dependence of the specific resistance on the impurity concentration for the monocrystalline and polycrystalline vaporized regions formed in this way was then, as shown in fig. 1. The growth site for polycrystalline development is not limited in particular to the above, but can be formed by evaporation of silicon which essentially contains no contamination, or a silicon oxide layer with a thickness of approx. 500 Å. In this case, the oxide film with a thickness of approx. 500 Å bladders, e.g. so-called pinpricks, so that the silicon is formed as a polycrystalline area on the oxide film by means of the evaporation method. With the evaporation method, the same result was obtained, also when monosilane or phosphorus oxide chloride or phosphorus pentachloride was used as a contaminant,

or when the temperature for vaporization was in the range 1050 - 1250° C

for normal vaporization.

Also, when the impurity concentration of the polycrystalline semiconductor region is equal to the impurity concentration of the monocrystalline semiconductor region, the specific resistance of the polycrystalline region is assumed to exceed the specific resistance of the monocrystalline region for the following reasons (which, however, have not yet been fully clarified) when the impurity concentration of the polycrystalline region is lower than the critical concentration Cc on fig. 1. (i) The impurity is extracted at the surfaces of the small single crystals that form the polycrystalline material (at their grain boundaries). (ii) Charge carriers are trapped at the grain boundaries so that the charge-carrier concentration's contribution to the conduction is reduced. (iii) In the polycrystalline layer, the free mean path length of the charge carriers is short and their mobility is small.

By utilizing the properties described above, the invention thus provides an integrated semiconductor circuit in which nearby monocrystalline semiconductor regions are isolated from each other by means of polycrystalline semiconductor regions with a lower contaminant concentration than the critical concentration Cc and consequently with high specific resistance.

The invention shall be described in detail in the following by means of examples.

Fig. 2A - 2E show an embodiment of the invention and fig. 2F is a connection diagram for a semiconductor device which is manufactured according to those in fig. 2A - 2E showed method steps, where the designations and D£ indicate diodes.

The manufacture of the above semiconductor device begins with the manufacture of a monocrystalline silicon semiconductor substrate (a monocrystalline semiconductor wafer) 51 as shown in fig. 2A, which substrate is heavily doped with an n-type impurity, e.g. phosphorus. Growth sites 62 for polycrystalline development are then deposited in selected areas on a surface of the semiconductor substrate 51, e.g. silicon dioxide or trisilicon tetranitride which has a masking effect against subsequent contamination diffusion. In this case, it is appropriate to form a silicon layer on the silicon dioxide or tri-silicon tetrachloride layer by means of evaporation or the like, if necessary. The growth sites 52 are arranged in the form of a network to surround monocrystalline semiconductor regions to be formed in the following, as shown in fig. 2B. Subsequently, silicon doped with an impurity of a lower concentration than the critical concentration Cc is formed to a thickness of approx. 8 u on the monocrystalline semiconductor substrate 51 with the growth sites 52, by means of evaporation in the same way as described previously in connection with fig. 2. This leads to the formation of polycrystalline semiconductor regions (polycrystalline layers) 53 at the growth sites 52, and a layer 54 consisting of monocrystalline semiconductor layers 54' and 54" on the monocrystalline semiconductor substrate 51, as shown in Fig. 2C. Subsequently, a silicon oxide or silicon dioxide film 55 by thermal oxidation on the deposited layer consisting of the polycrystalline and monocrystalline layers 53 and 54, and the film 55 is removed at selected locations for

to form windows through which boron, which is a p-type impurity, diffuses into the vaporized layer to a depth of 3 - 5 (i, so that

anode areas 56 with diode transitions J , and J ^ appear for the diodes D1 and D2, as in fig. 2D. Aluminum or a similar metal is then deposited on the anode areas 56 of the diodes in such a way that ohmic contact is made with them to form electrodes 57, and gold is deposited on the underside of the monocrystalline semiconductor substrate 51 to form a cathode electrode 58, so that it is provided a finished semiconductor device as shown in fig. 2E.

With the preceding method, the specific resistance of the polycrystalline layer 53 becomes greater than that of the monocrystalline layer 54, as the former's contaminant concentration is lower than the critical concentration Cc, so that there is a high resistance between the mud-like areas formed by the monocrystalline layers 54' ° 9 54" to prevent a parasitic element from forming. In the foregoing, the vaporized layer's contaminant concentration is lower than the critical concentration Cc, but it is advantageous to define the lower limit value for the vaporized layer's contaminant concentration.

In the preceding example, the contaminant concentration for the evaporated layer, i.e. for the polycrystalline and monocrystalline layers 53 and 54, is chosen to be higher than 10 12 atoms/cm 3 in the course of fig. 2C. In the event that vaporization of a contaminant with a concentration lower than 10 12 atoms/cm 3 takes place, the specific resistance of the vaporized layer, especially for the monocrystalline layer 54, is not kept constant, even if silicon tetrachloride, monosilane or other silanes are used, or if such contamination such as phosphorus oxide chloride is used for the doping of phosphorus, or if arsenic trichloride is used for the doping of arsenic or if antimony is used as a contaminant, The reasons for the instability of the specific resistance have not been clarified, but are assumed to be due to the following: (i) Small temperature variations in the furnace during the vaporization process. (ii) Diffusion of the contamination from the monocrystalline semiconductor substrate. (iii) Self-doping of the impurity from the monocrystalline semiconductor substrate into the deposited layer. (iv) Changes in the properties of the crystals as a result of a small amount of oxygen in the carrier gas (even if it is theoretically equal to zero).

It has been established that the change in specific resistance quickly becomes significant when the contaminant concentration is below 10 <12> atoms/cm 3.

The use of a monocrystalline layer with a strong change in the specific resistance causes variations of the junctions, the breakdown voltages and of the depth of the junctions in the anode regions 56 of the diodes, which are formed by the diffusion of a contaminant such as in the sequence according to fig. 2D, and this thus entails an irregularity in the properties of the finished semiconductor devices. If the contaminant concentration of the monocrystalline layer 54 is lower than 10 atoms/cm, the depth of the transitions varies by o due to the fact that the contamination existing in the monocrystalline silicon semiconductor substrate 51 during the evaporation process diffuses up into the area of the upper surface of the monocrystalline layer 54 (where the transitions and J „ <d>others), and changes these areas' pollution concentration. Although the thickness of the vaporized layer 54 increases, the time for the vaporization becomes longer, so that the monocrystalline semiconductor substrate 51's contamination diffuses further and the aforementioned disadvantages cannot be avoided.

With reference to fig. 3, a detailed description of another embodiment of the invention shall be given.

The production begins with the production of a monocrystalline semiconductor substrate 11, e.g. of p-type, as shown in fig. 3A. An oxide film 12, e.g. silicon dioxide, which will act as a diffusion mask and as a growth site for polycrystalline development, is deposited over the entire upper surface of the monocrystalline semiconductor substrate 11, and the oxide film 12 is selectively removed by means of photoetching or the like, in such a way that the film 12 is, for example, left in the form of a network. A p-type impurity is then diffused into the monocrystalline semiconductor substrate 11, the oxide film 12 being used as a mask, so that a number of submerged layers 13 and 13' of the n<+-> type with a high impurity concentration are provided, as shown in fig. 3B. Then, an oxide film which has been formed on the n<+>-type semiconductor regions 13 and 13' is removed by the diffusion of the n-type impurity at selected locations. Afterwards, semiconductor areas 15 and 15" are formed by evaporation of the substrate 11, which areas have a lower impurity concentration than the critical concentration, e.g. less than 10 18 atoms/cm 3 and preferably more than 10 12 atoms/cm 3,

and which have the opposite type of conductivity in relation to the substrate 11, e.g. n-type, as previously described in connection with fig. 1.

The resulting vaporized layer consists of polycrystalline layers 14 which have been developed on the growth sites 12, and monocrystalline layers 15 and 15' which have been developed on the semiconductor regions 13 and 13' of n<+> type. As will be apparent from the following description, these monocrystalline layers 15 and 15' become isolated, moon-like areas and serve as collector areas in transistors which are to be formed, for example, in these moon-like areas. In this case, it is appropriate that the thickness of the oxide film 12 is approx. 2000 Å, that the evaporation temperature is 1050 - 1250° C, and that the thickness of the monocrystalline layers is approx. 5 u. Although the n-type impurity diffuses from the n<+->-type semiconductor regions 13 and 13' into the polycrystalline layer 14, as indicated by arrows in fig. 3C, the resistance of the polycrystalline layer 14 can be greatly and effectively increased by increasing the width of the polycrystalline layer 14 (the distance between two monocrystalline semiconductor regions 15 and 15') as much as possible.

This step is followed by an n-type semiconductor elements are formed in the monocrystalline layers 15 and 15'. As shown in fig. 3D, a p-type contaminant is diffused, e.g. boron, into the monocrystalline layers 15 and 15' through a diffusion mask formed by an oxide film 16 to provide p-type semiconductor regions 17 and 17', which will eventually serve as the base regions of the transistors. An n-type impurity is then diffused into the p-type semiconductor regions 17 and 17' through the oxide film 16 serving as a mask to form semiconductor regions 18 and 18' with high impurity concentration, i.e. of n<+-> type. These areas will eventually form the emitter areas of the transistors, as shown in fig.

3E. Thus, the semiconductor elements (transistors) are formed in the monocrystalline layers 15 and 15'. Furthermore, a thin film element is formed, e.g. a thin film resistor 19, on the polycrystalline layer 14 at a place through the oxide film 16, by means of metal vapor deposition or the like, as shown in fig. 3F. Then, for example, aluminum is evaporated through a predetermined mask to provide predetermined electrodes 20 for the semiconductor elements formed in the monocrystalline layers 15 and 15', as well as conductors 21 which connect predetermined electrodes and a selected electrode to the thin film element 19. In fig. 4 shows the electrical connections for the thus formed integrated semiconductor circuit.

The foregoing construction provides an improved isolation between the semiconductor elements formed in the monocrystalline layers 15 and 15' and between the semiconductor elements and the thin film element 19 to provide complete isolation of the elements formed on the same substrate. This ensures that interference between the elements is avoided, so that they can be considered as if they were formed on separate sub-

strater to give the integrated circuit improved characteristics.

In fig. 5 is a circuit equivalent to the semiconductor integrated circuit shown for such a construction with respect to isolation. In the figure, the reference numbers 15 and 15' correspond to the monocrystalline layers 15 and 15, respectively. 15' of n-type, and the reference numbers 11

and 19 correspond to the p-type monocrystalline semiconductor substrate, respectively. the thin film element of fig. 3.

The designation D indicates a diode with a p-n junction which

is formed between the p-type semiconductor substrate 11 and the n<+->-type semiconductor region 13 under the n-type monocrystalline layer 15, and D ? denotes a diode with a p-n junction formed between the p-type semiconductor substrate 11 and the n+-type semiconductor region 13' under the n-type monocrystalline layer 15'. The designation R denotes a transverse resistance of the polycrystalline layer 14 between the two monocrystalline layers 15 and 15', and Rp denotes a transverse resistance of the polycrystalline layer 14 under the thin film element 19. The designation C. denotes a capacitor formed by the one between the polycrystalline layer 14 and the thin film element 19 incorporated oxide film 16, and C£ denotes a capacitor formed by the polycrystalline layer 14. In this case, the polycrystalline layer 14 has a high resistance and can be regarded as a dielectric, as described later, so that it is disregarded its longitudinal resistance and only its capacity are shown. The designation C indicates a capacitor which is formed by the oxide film 12 inserted between the polycrystalline layer 14 and the semiconductor substrate 11.

As can be seen from fig. 5, the monocrystalline layer 15 is completely isolated from the substrate 11 by means of the p-n junction of the diode and at the same time from the monocrystalline layer 15' of the polycrystalline layer 14. In accordance with the invention, the impurity concentration in the semiconductor material is selected for vaporization of the monocrystalline layers 15 and 15 ' as well as in the polycrystalline layer 14 lower than approx. 10 17 atoms/cm 3 , as previously described. It has been found that the polycrystalline layer 14 has a sufficiently high specific resistance to isolate the circuit components in conventional integrated semiconductor circuits.

As can be seen from the curve in fig. 1, which shows the connection between the polycrystalline layer's contaminant concentration and its specific resistance, the polycrystalline semiconductor's specific resistance is approx. 100 times as high as the monocrystalline semiconductor's specific resistance, when the contaminant concentration is approx. 10 17 atoms/cm 3. A monocrystalline semiconductor with an impurity concentration of approx. 10 17 atoms/cm 3 otherwise exhibits the same type of conductivity as the contaminant and its specific resistance is approx.

0.1 ohm-cm, while a polycrystalline semiconductor with such an impurity concentration has a specific resistance as high as more than 10 ohm-cm. When the impurity concentration was less than 10"^ atoms/cm 3 , the insulation of the polycrystalline layer was so high that its specific resistance could not be measured by the quadrupole method.

The reason why the impurity concentration in the semiconductor material for vapor deposition of the monocrystalline layers 15 and 15'

and the polycrystalline layer 14 is chosen higher than 10 12 atoms/

cm 3, it is more likely that the semiconductor elements, i.e. the polycrystalline areas that form the transitions, with a lower concentration of contamination do not always exhibit a desired type of conductivity and are thus unstable, and that the rectification properties of the transitions are likely to deteriorate. If, for example, the pollution concentrations in the surface parts of the earlier in connection with fig. 3 described n<+>-type semiconductor regions 13 and 13' are unstable, and the impurity concentrations in the upper part of the monocrystalline layers 15 and 15' are also unstable, their specific resistance is very difficult to maintain at a predetermined value below a subsequent heat treatment for diffusion, etc. When a p-type impurity is diffused into such mud-like regions 15 and 15' to provide base regions therein, the diffusion depth cannot be controlled to a predetermined value,

and consequently the characteristics of the finished transistors are unstable.

In the thus produced integrated semiconductor circuit according to the invention, the monocrystalline layer 15 is completely isolated from the substrate 11 due to the diode D2 p-n transition and is completely isolated from the thin film element 19 by the polycrystalline layer 14 and the capacitor, as described above. Consequently, the semiconductor elements formed in the monocrystalline layers 15 and 15' are completely isolated from each other as if they were formed on separate substrates, so that interference between the semiconductor elements is avoided.

Furthermore, the thin film element 19 is completely isolated from the substrate 11 and from the monocrystalline layer 15' by the capacitors C1, C2 and also the resistor R1. Consequently, the semiconductor elements formed in the monocrystalline layers 15 and 15' and the thin film element formed on the oxide film 16 are isolated from each other under very good isolation conditions in order to eliminate disturbances between them. The invention thus causes no deterioration of the elements' properties, and it is consequently particularly advantageous when it is used in integrated circuits or the like, in which a large number of elements are formed on one and the same substrate.

As, moreover, the capacitors C1, C2 and are included in a series connection between the thin film element 19 and the substrate 11, their overall capacity is small and consequently the parasitic capacity effect is the least possible. The surface of the polycrystalline layer 14 further has irregularities with a size of approx. 0.5 - 2 µm, so that the oxide film 16 above the layer 14 becomes uneven. The surface of the oxide film is therefore increased to increase the efficiency of the thin film element, e.g. the thin film resistance or capacity per unit area, and the unevenness improves the adhesion of the thin film element to the oxide film 16. If the passive element is formed by a thin film, it is possible to form this on the semiconductor substrate, which element can have values within a large range, have a small temperature coefficient and a value with high accuracy together -likened to a thin film element formed by diffusion.

In fig. 6 shows a series of greatly enlarged cross-sections of successive steps in the production of an integrated semiconductor circuit in accordance with another embodiment of the invention. The manufacture begins with the manufacture of a monocrystalline semiconductor substrate 31 with a predetermined type of conductivity, e.g. of p+<->type, as shown in fig. 6A. An oxide film 32 is deposited on the upper surface of the monocrystalline semiconductor substrate 31, e.g. of silicon dioxide, which film is removed at selected locations by etching or a similar process to form a window. Then, an n-type impurity diffuses through the window into the semiconductor substrate 31 to form an n<+>-type semiconductor region 33 as shown in fig. 6b. Next, the oxide film is etched over the n<+>-type semiconductor region 33 and the substrate 31 is selectively etched away to provide growth sites 32 for polycrystalline growth, as shown in fig. 6c. In this case, it is convenient to form the growth sites by vapor deposition of silicon on the remaining oxide film 32 at a temperature as low as approx. 550° C to facilitate the formation of polycrystalline layers. The same applies to that in fig. 3 showed example. The next step consists in vaporizing a semiconductor material with a contaminant concentration that is higher than the above-mentioned lower limit value of 10 12 atoms/cm 3 , but lower than the critical concentration Cc, i.e. 10 17 atoms/cm 3 . The resulting evaporated layer consists of polycrystalline layers 34 grown on the oxide film 32, and monocrystalline layers 35 and 36 on the n<+>-type semiconductor region 33 and on the substrate 31, as shown in fig. 6D. During the vapor deposition process, the existing n-type contamination in the semiconductor region 33 of n<+-> type diffuses into the overlying monocrystalline layer 35, but it has been shown that the surface portion's contamination concentration does not change significantly with the subsequent formation of, for example, a base region, by choosing the semiconductor material's contaminant concentration greater than the previously mentioned lower limit value. During the evaporation process, the p-type impurity in the p+<->type substrate 31 further diffuses into the overlying monocrystalline layer 36 to give this a p-type conductivity, but the substrate 31 impurity concentration can be controlled with great accuracy, so that no special problems arise. The formation of the deposited layer is followed by the production of a semiconductor element in the n-type monocrystalline layer 35. More specifically, a p-type impurity diffuses into the monocrystalline layer 35 through a window formed in an oxide film 37 for providing a semiconductor area 38

of p-type in layer 35, as shown in fig. 6E. An n-type impurity is then diffused into the p-type semiconductor region 38 through the oxide film 37 serving as a diffusion mask to form an n-type semiconductor region 39 in the region 38, as shown in fig. 6F. In this case, the n-type impurity simultaneously diffuses into the p-type monocrystalline layer 36 to form a semiconductor region 40

of n-type in this, so that a diffused resistance thus arises in the monocrystalline layer 36 of p-type. Thus, the semiconductor element and the diffused resistance are formed in the monocrystalline layers 35 and 35 respectively. 36. Thin-film element, connection conductors, electrodes, etc. are then formed, as in the case of the integrated semiconductor circuit according to fig. 3.

In an integrated semiconductor circuit of such a construction, the semiconductor elements formed in the monocrystalline layers 35 and 36 are well isolated from each other, and the elements formed on the same substrate can be isolated from each other, which is clear from the above. Consequently, the present example gives the same result as in the previous examples.

Fig. 7 shows manufacturing steps in a further modified embodiment of the invention. The first step is to produce a monocrystalline semiconductor substrate 4l with a predetermined type of conductivity, e.g. of p-type, as shown in fig. 7A. An oxide film 42, e.g. of silicon dioxide, which is then removed within selected areas by etching or a similar method to form windows in the film. Then, for example, an n-type impurity is diffused through the windows of the oxide film 42 into the substrate 41 to form semiconductor regions 43A and 43B of n<+-> type therein, as shown in fig. 7B. The semiconductor region 43A of n<+->type will eventually serve as an isolated region in a transistor of p-n-p type, which will be apparent from the following description. In the next step, a p-type impurity diffuses into the n<+->-type region 43A through the oxide film 42 serving as a mask to form a p+<->-type semiconductor region 44. The oxide film is then removed over the semiconductor region 44 of p+<->type and the semiconductor region 43B of n<+->type within selected areas, after which a vaporized layer of, for example, an n-type semiconductor material with, as in the previous example, a contaminant concentration of 10 12 - 10 17 atoms/cm 3 , are deposited as shown on o fig. 7D. The resulting deposited layer consists of polycrystalline layers 45 grown on the oxide film 42, and of monocrystalline layers 46 and 47 on the p+-type semiconductor region 44 and the n+-type semiconductor region 43B. During the evaporation process, the p-type impurity in the p+<->type semiconductor region 44 diffuses into the overlying monocrystalline layer 46 and gives this a p-type conductivity. In this case, it is also possible to remove the oxide film 42 in such a way that the outer edge of the window in the film 42 is set on the semiconductor region 43A of n<+> type, as shown in fig. 7D'. The formation of the evaporated layer is followed by the production of semiconductor elements in the monocrystalline layers 4° and 47 of p- or n type. More specifically, an n-type impurity diffuses into the p-type monocrystalline layer 46 through an oxide film 48 serving as a mask to form an n-type semiconductor region 49, as shown in fig. 7E. Furthermore, a p-type impurity diffuses into the monocrystalline layer

47 of n-type through the oxide film 48 to produce a semiconductor region 150 of p-type, as shown in fig. 7F. A p-type impurity then diffuses through the oxide film 48 into the p-type monocrystalline layer 46 and the n-type semiconductor region 49, so that semiconductor regions 151 and 152 of the p+<-> type are formed, as shown in fig. 7C. IN

in this case, the semiconductor region 150 of p-type and the semiconductor regions 151 and 152 of p+<->type can be formed by simultaneous diffusion. Furthermore, an n-type impurity diffuses into the n-type monocrystalline layer 47 and the p-type semiconductor region 150 to form n<+>-type semiconductor regions 153 and 154, as shown in fig. 7H. In this way, p-n-p and n-p-n type transistors are formed in the monocrystalline layer 46

respectively 47v A thin film element is then formed, e.g. a thin film resistor 155, by metal vapor deposition or similar on the polycrystalline layer 45 in a. area through the oxide film 48, as shown in fig. 71. The next step consists in vapor deposition of e.g. aluminum through a predetermined mask for the production of predetermined electrodes 156 on the semiconductor elements formed in the monocrystalline layers 46 and 47, conductors connecting predetermined electrodes, and conductors 157 which. connects a predetermined electrode <p>g the thin film element 155- Fig. 8 shows an electrical connection diagram for the integrated semiconductor circuit thus produced. In the figure, a resistor R is formed by the thin film resistor 155, while a resistor R^. is not shown in fig. 71.

With reference to fig. 9, a further example of the invention shall be described in the following, together with a method for producing the same. The production begins with the production of a monocrystalline silicon semiconductor substrate 6l, as shown in fig. 9A, which contains a p-type impurity, eg boron. A contamination diffusion mask 62 is deposited on one surface of the substrate 6l, e.g. a silicon oxide film or the like, in which windows are formed at predetermined locations, through which windows phosphorus diffuses as an n-type impurity into the substrate 6l to produce submerged layers Bu, as shown in fig. 9B. The contaminant concentrations Bu of the immersed layers are chosen so that those in the layers

'lo .3

surface parts are approx. 10 atoms/cm . Each of the layers forms a part of its own collector area in, for example, transistors that will be formed in the following, thereby providing for reduced collector resistances in the event of a saturated collector.

After the production of the immersed layers Bu, for example, silicon is evaporated to a thickness of approx. 1 (i) to form a growth site for polycrystalline development in the form of a network surrounding the submerged layers Bu in the same manner as previously described in connection with Fig. 1, as shown in Fig. 9C.

After this, a gas mixture containing silicon tetrachloride and arsenic trichloride is passed over the semiconductor substrate 6l together with hydrogen as a carrier gas at a temperature of 1150° C, so that a vaporized silicon layer 63 is formed with an impurity concen-

o 17,300 tration of approx. 10 atoms/cm and with a thickness of approx. 10 u on the semiconductor substrate 6l, as shown in fig. 9D. The evaporated layer 63 consists of a polycrystalline semiconductor region 63 that has grown on the growth site S, and monocrystalline semiconductor regions 64 on the immersed

layer Bu as well as on the exposed, monocrystalline areas of the semiconductor substrate 6l. The polycrystalline semiconductor region 63 and the monocrystalline semiconductor regions 64 are formed simultaneously by vapor deposition, as in fig. 1, so that the contaminant concentrations in their surface parts are equal. However, it has been shown that the specific resistance of the polycrystalline semiconductor region 63 is at least 30 times higher than the specific resistance of the monocrystalline semiconductor region 64. The glass-like regions I, each consisting of the submerged layer Bu and the monocrystalline semiconductor region 64, are thus isolated from each other by means of transitions J formed between the submerged layers Bu and the monocrystalline semiconductor substrate 6l, as well as by the polycrystalline semiconductor region 63 with higher specific resistance than the monocrystalline semiconductor regions 64. The contaminant concentration of the polycrystalline semiconductor region 63 formed by the deposition method is not particularly limited to the above-mentioned value 10 17 atoms/cm 3. With a contaminant concentration below the critical concentration Cc, the specific resistance of the polycrystalline semiconductor region can be greatly increased and the moon-like regions can be well insulated from each other.

The monocrystalline semiconductor substrate 6l and the polycrystalline semiconductor region 63 have different types of conductivity, so that, where the contaminant concentration of the former exceeds that of the latter, a transition J is formed in the boundary plane between the region 63 and the substrate 6l, as indicated by the dashed line in fig. . 9D, and so that, where the contaminant concentration of the monocrystalline semiconductor substrate 6l is equal to the contaminant concentration of the polycrystalline semiconductor region 63, a transition J2 is formed between them, as also indicated by means of the dashed line in the same figure. If the contaminant concentration of the substrate 6l is lower than that of the area 63, a transition is formed in the substrate 6l. In the latter case, an n-type region is formed in each moon-like region I in the surface part of the monocrystalline semiconductor substrate (in the lower part of the polycrystalline semiconductor region 63), and the moon-like regions I are connected to each other through the n-type region, but as this n-type region is formed by diffusion of the impurity in the polycrystalline semiconductor region with high resistance, the impurity concentration in the diffused n-type region is very small and the resistance value between the two moon-like regions I is not reduced.

In the event that the contamination concentration of the monocrystalline semiconductor substrate 6l is less than the contamination concentration of the polycrystalline semiconductor region 63 if the growth site S is formed by vapor deposition of, for example, silicon on a layer of silicon oxide, trisilicon tetrachloride or the like, which layer is preferably formed with a thickness greater than 1000 Å using for example thermal oxidation and used as a contamination diffusion mask in the course of fig. 9C, the transition J^ is not formed. A silicon oxide film 65 is formed by thermal oxidation on the monocrystalline semiconductor regions 65, in which the moon-like regions I

is formed, and on the polycrystalline semiconductor region 63, and the silicon oxide film 65 is selectively removed to form windows through which a p-type impurity, e.g. boron, diffuses into the monocrystalline semiconductor regions 64 to provide base regions b therein, as shown in fig. 9E. In this case, it is possible that the oxide film 65 is removed to form a window on the polycrystalline semiconductor region 63, through which window boron simultaneously diffuses into the polycrystalline region. The window for this diffusion into the polycrystalline area is located/at the center of the area in the form of a network. When boron diffuses through the window into the polycrystalline region, it has a high diffusion rate and reaches the monocrystalline semiconductor substrate 6l in a short time. In this case, the width L of the polycrystalline semiconductor region 63 is chosen so that it is much larger than the width t for the board diffusion, so that the moon-like regions I are isolated from each other by the transition J and the transition J formed in the polycrystalline semiconductor region 63. The transition J formed in the polycrystalline semiconductor region is connected to a polycrystalline semiconductor region 631 with a lower contaminant concentration than the critical concentration on the side of the mud-like regions I, so that the transition J has a noticeably high breakdown voltage. Although breakdown occurs in the junction J p , a leakage current is limited by the polycrystalline semiconductor region 631 with high resistance, by means of which the leakage current can be kept substantially equal to or less than the leakage current in a conventional isolation by means of a junction.

The oxide film 65 is further removed in selected areas to form windows, through which an impurity diffuses into the monocrystalline areas 64 to form electrode portions Ce therein, which are connected to emitter and collector areas e and c. Then, electrodes are formed through windows in the oxide film 65 for providing connecting conductors and completing the integrated semiconductor circuit, but this process is not directly affected by the invention and will therefore not be described.

In the above example, the moon-like areas I which consist of the monocrystalline semiconductor areas 64 are surrounded by the polycrystalline semiconductor areas 63 with high specific resistance. With a conventional p-n junction isolation method, the monocrystalline semiconductor regions 64 are surrounded by an isolation region formed by the diffusion of a contaminant, but the contaminant diffuses not only in the thickness direction of the semiconductor substrate, but also in its side direction, so that an outer region of 10 - 15 H- is formed around the monocrystalline areas 64. In the invention, however, the polycrystalline area 63 selectively formed by the vapor deposition method with high resistance is used to insulate the glass-like areas I, and consequently the width L of the area 63 can be kept smaller than 5 M-■ Consequently, the necessary surface is reduced for each element down to approx. 70%, so that an increased element density is obtained. Furthermore, since the invention does not require the diffused insulation area, the parasitic capacity is reduced and the integrated semiconductor circuit has improved high-frequency characteristics.

Claims (6)

1. Semiconductor integrated circuit wafer with regions of monocrystalline semiconductor material separated from each other by polycrystalline regions, which wafer has a monocrystalline semiconductor substrate with one type of conductivity, growth site regions for polycrystalline development located in selected regions on one side of the substrate, at least one region of the opposite type of conductivity on the said side of the substrate and in one of the areas not covered by the growth areas, and an evaporated, continuous layer of semiconductor material deposited on the said side of the substrate, forming the areas of polycrystalline material on the growth areas, and which form the monocrystalline areas in the areas on the aforementioned side of the substrate that are not covered by the growth sites, characterized in that the semiconductor material of the continuous layer has a conductivity-determining type of impurity in a concentration of 10 12 -10 17 atoms/cm 3, so that the polycrystalline areas ha r higher specific resistance than the monocrystalline areas. 2. Disc according to claim 1, characterized in that the monocrystalline semiconductor substrate and the evaporated layer have the same type of conductivity, and that the monocrystalline areas are isolated from each other by the polycrystalline areas. 3. Disc according to claim 1, characterized in that p-n junctions are formed between the monocrystalline areas and the substrate. 4. Disc according to claim 1, characterized in that a number of areas with high contaminant concentrations are formed in the substrate, and which are continuous with the monocrystalline areas and have the opposite type of conductivity in relation to the substrate. 5. Disc according to claim 1, characterized in that a number of areas with a high contaminant concentration are formed in the substrate and which are continuous with the monocrystalline areas and have the same type of conductivity as the substrate. 6. Disc according to claim 1, characterized in that at least one of the monocrystalline areas contains a separate area with the opposite type of conductivity in relation to the monocrystalline areas.