NO125806B - - Google Patents

Description

Switching circuit with magnetic cores.

This invention relates to magnetically controlled circuits for performing number processing and more particularly to new circuit arrangements that use magnetic cores which can successively perform logical manipulations of data as the number processing progresses.

Logical functions such as can be defined by Boolean's method of designation, mechanized in number computing devices using basic circuits and equipment that in some designs use electron tubes and diodes either individually or in combination. Such aids have various disadvantages. If it e.g. applies to electronic

pipes, limited lifetime, high power consumption and complicated circuits are taken into account here. If it concerns dio-

there, the introduction of a clause as an additional condition to a logical function which all

nest is mechanized, require an additional diode. Furthermore, as the diode circuits become complicated, as with multi-level arrays, the construction of sources that can supply working voltages to drive these net-

works, also become more complicated. In addition to this, it has been found that the electrical characteristics of diodes change when they are used for a longer period of time.

It is therefore desirable to switch to

dre constructions that are better in any case in these respects, and to circuits that are arranged in such a way that a logical function can be produced synthetically.

A fundamental component whose importance is constantly increasing approaches the ideal for this purpose. This component is the magnetic core which has an approximate

met rectangular hysteresis loop. The magnetic core, which, in addition to having many special properties that overcome the above-mentioned shortcomings of electron tubes and diodes, is exceptionally long-lived and has electrical properties that persist over a long period of use.

The person skilled in the art knows the fact that magnetic cores to be used in this way must be driven, i.e. arranged so that they are coupled to one or the other state of remanent magnetism by means of currents flowing in windings which are inductively coupled to the core construction. A known system provides driving power to the cores from other cores and is thereby enabled to arrange cores to synthetically produce logical functions. However, cores are not considered to be good driving forces in this regard, as they do not represent constant current or voltage sources in that their output is a function of the number of other cores that the load includes. Furthermore, required for each logical link, like this

as described using the Boolean equation

ger, to be mechanized in a circuit that uses the technique where core drives core, the incorporation of one or more additional cores. Moreover, if the cores are to have the same size, the conductor must be connected to the driving core by means of a multiple winding. If one therefore wants to mechanize complex functions in accordance with the known technique,

will the number of cores required,

become large and the winding becomes difficult in that it involves a significant increase of

the accompanying construction difficulties.

It will be understood that magnetic cores are not a good drive source for other cores, as the current produced by an output winding on the core is a function of the load which, in the case of a compound switching circuit, varies as the number of the cores forming the load varies. Expressed in other words, magnetic cores are not a good source of drive for other cores, as they represent neither a source of constant voltage nor a source of constant current.

The invention aims to avoid the above-mentioned disadvantages.

More specifically, the invention relates to a switching circuit with magnetic cores comprising a magnetic control core which is arranged to receive drive currents which are supplied to drive windings on the core during selected periods of a cycle of core drive currents or to receive drive currents and data signals which are supplied to one or more data windings on the core and a magnetic storage core equipped with drive windings adapted to receive drive currents during selected periods of said cycle or to receive drive currents and data signals on a data winding connected with an output line on the control core in such a way that at the end of the cycle data is stored in the storage core in dependence on data previously stored in the control core. with the above-mentioned purpose in mind, the invention mainly consists in that one or more arresting lines are arranged on the control core intended to always be supplied with stopping currents when a driving current that works to drive the control core to a remanent state should render the ear inactive, and that where a transmission circuit is arranged between the control and storage cores whose input is connected to the control core's output line and whose output is connected to a stop line on the storage core in such a way that whenever the control core is switched from one to the other remanent state by means of the drive current, the transfer circuit responds to the output signal on the output line in such a way that it supplies a stop signal to the storage core stop line, so that a drive current is rendered inactive with respect to switching the storage core.

According to the present invention, an apparatus is provided for performing a logical calculation operation, characterized by a first storage magnetic core which can appear in one of two remanent magnetic states designated respectively as the "true" and the

"fake", nuclear propellants to produce

currents that can connect said core first to the false and then to the true state, a control or stop winding for the storage core, another control magnet core that can also appear in one of two remanent magnetic states, true or false and initially in a false state, a sense winding which is inductively coupled to the control core, core drive means for producing currents capable of switching the control core first to a true and then to a false position, a stop winding or windings for the control core and each of which can be supplied with a control signal or a signal indicating the complement of an individual term in the logical calculation operation, each of the aforementioned control signals acting in a direction so as to allow or stop true switching of the control core depending on whether the calculation operation is respectively true or false and a circuit arrangement which has an output connected to the storage core's stop winding and therefore reacts to the state of the control core as it is fixed in the presence or absence of a signal on the sense winding in case of false connection of the control core to allow or respectively stop the true connection of the storage core and thereby establish the correct value for the logic arithmetic operation true or false in the storage core.

In order to better understand the invention, we will now describe various embodiments of it with reference to the accompanying drawings. Fig. 1 is a block diagram of a series addition device constructed in accordance with the technique of the present invention. Fig. 2 is a diagram for the series addition device shown in fig. 1. Fig. 3 shows a hysteresis loop for the magnetic material used in the core coupler. Fig. 4 shows a group of waveforms used for serialization of the effect on the addition circuits shown in Fig. 2. Fig. 5 shows an alternative group of waveforms, other than those in fig. 4. Fig. 6 shows a group of waveforms representing the core flux pattern and the induced voltage in the core's sensing conductor produced by the application of a magnetomotive force with coupling amplitude. Fig. 7 is a block diagram of the recording device's transmission circuit. Fig. 7a is a set of curves illustrating the operation of the transmission circuit. Fig. 8 shows the network provided to supply the periodic signals Wc and Ws used for controlling the transmission circuit. Fig. 9 is a diagram of the transmission circuit's input amplifier. Fig. 10 is a diagram of the transfer circuit's flip-flop. Fig. 10a is a diagram of the transfer circuit's flip-flop output amplifier. Fig. 11 is a diagram of the transmission circuit's drive amplifier. Fig. 12 is an example of addition of two binary numbers which is shown in the description of how the addition circuits for the present invention work. Fig. 13 is a graphical presentation of waveforms showing the voltage at various points in the adding device of fig. 2 during the execution of an addition. Fig. 14 is a true state table of the adder and shows the derivation of the logic equations that are mechanized by means of the circuits of the present invention. Fig. 14a shows how the K register's control cores generate the terms in the Boolean equation for mental digits. Fig. 15 is a schematic representation of an arithmetic register used to illustrate the mechanization of the various basic logical operations in accordance with the circuit arrangements of the present invention and

fig. 16 gives a table of the operations which are carried out by means of the circuit of fig. 15 and shows how the E register control cores for performing these operations are selected using the program control.

The present invention refers to the use of magnetic cores in the logic circuit system which comprises the central drive device for a digital calculating machine. The invention includes e.g. in a computing device which mainly comprises three registers. Each register comprises two sets of magnetic cores, one set being used for storing the binary coded digits to be processed, and the other set being used to carry out the manipulation of these digits. Each register also includes a transfer circuit which is described below, and which functions to sequentially read information from the sets, delay this information and set it up as stop signals which can effect the switching of the cores in the sets. In the preferred embodiment which exemplifies the invention, using a circuit arrangement for adding four order binary numbers, the three registers are designated as E register, F register and K register. Using these registers controlled by externally supplied timing signals and the previously mentioned internally generated stop signals, the special circuit arrangement shows how a serial addition of four binary digits in the addend, as they are lined up in the four storage cores in the F register, can be transformed into the four binary digits in the first addend, as they are set up in the four storage cores in the E register and use the only storage core in the K register in which the only binary digit meant to be produced by a partial addition is set up. The timing signals for the preferred embodiment include a pair of clock signals and select signals for the storage cores. The latter defines the digit transfer cycles of equal duration and mainly serves to select in order the binary digits to be added, starting with the lowest digit.

The combination of clock signals with select signals for the storage cores establishes for the digit transfer cycle for each step of a data process such as a partial addition, a sequence of four equal time periods within each digit transfer cycle. These four periods are denoted symbolically as periods Rs, period Wt., period R,, and period Ws. During the periods Rs and R(:, queries, i.e. reading of the storage and control cores take place. During W,, and Ws periods, setting is carried out, i.e. writing into the control and storage cores takes place. More specifically, the operations in during the four periods of a digit transfer cycle arranged as follows. In the period Rs, the selected storage cores in the E and F registers and in the K register are polled, and the transfer circuits are set in accordance with the read digits. In the period Wc, the transfer circuits produce stop signals which correspond to their states, and the control cores of all registers not wound to be stopped by these signals are set. During period R0, the control cores of all registers are polled, and all transfer circuits are set in accordance with the read information. -pet of the period W, the transmission circuits produce stop signals corresponding to their states, and the selected storage cores for the E and F registers and the K register so m is not wound to be stopped by these respective signals, is set.

The above-mentioned operation applies to the general mechanization of arithmetic processes that can be given Boolean expressions. Special mechanization for processes with serial addition includes only the winding of the storage cores themselves to effect a stop of the setting with signals that are represented by the corresponding logical arithmetic operations in the derived equations in the adding device which will be easily understood by a simple truth table. The logic that controls the generation of these signals is contained in the winding arrangement for the control cores, and it is significant to note that the transfer circuit for each register is used by its respective storage and control cores jointly.

Thus, when the cores and their accessories in the registers have been set up for an arithmetic process such as addition, other arithmetic processes such as subtraction, multiplication etc. can also be mechanized using the same cores by simply providing stop signal windings which fits the Boolean equations that represent these other processes. It is this which is characteristic of the invention and which brings about an adaptation in the calculation technique not yet achieved.

We now refer to fig. 1 on the drawings. One sees a working core in block form for a serial addition device to which what has been learned from the present invention can be adapted. On this form, designations are also indicated for the elements that will later be shown performing the work in a preferred embodiment.

The shown adding device includes means for adding into an accumulator, the E register storage, the number order for the number order is a binary number which is set up as added into the F register storage, taking into account the supposed binary digits from the previous number order stored in the K register storage. We will consider four order binary numbers although it must be understood that the principles to be developed can now be adapted for binary numbers of any length within the working capacity of the number calculator of which the adding device forms a part. It will further be understood that in a calculator embodiment, the number of register cores and the number of conductors connected to the individual core may be greater than shown, if one wishes to consider different logic functions to be synthesized so that they can be performed in series for calculator operations, as shown by a working diagram. To illustrate the invention, the present presentation therefore includes extracts of the equipment suitable for carrying out addition operations.

For the sake of simplicity, we will assume that initially the storage cores for the E and K registers are empty and that the F register has been filled with digits from e.g. a calculator's memory circuit. The designations Pi, Ps, Ps and P4 denote signals representing "digit transfer cycles". These signals define successive cycle timing periods during each of which one of the number orders 2°, 2<1>, 2<2>, 2<3> in the addition takes place. Thus, the first series of operations occurring during the first digit transfer cycle for which the signal Pi is effective is the addition using the control circuits 10 of the lowest digit (2° order) of the addend stored in the core lFs, to the lowest digit (2° order ) in the first addend stored in the core lEs to form the lowest digit (2° order) in the sum. The sequence of core "questions" and "settings" within the digit transfer cycle is determined, as previously stated, by clock signals Cs and C, the first shown being introduced into all storage cores and the last shown being introduced into the control circuit 10. The clock signals Ca and C(. are combined each with the digit selector signal Pi which last signal passes through both the storage and control cores to cause the operations to be performed during each digit transfer cycle to follow each other correctly.The sum digit is set in the core lEs and any subsequent inter- order meaning is stored in the core lKs. The digit that was previously stored in the core lFs in the F register is set again there, which will also be done during higher-order additions. That means that the F register information in the present embodiment is circulated again and stored again, i.e. that information that has been read out by, for example, the core lFs above line 17, is reset there above line 18. This does not necessarily is to characterize other embodiments in which it may be desired to release the F register (set all storage cores in it to false) or introduce other information into the F register during the addition operation.

The rest of the four-place addition is processed by control circuits lo one after the other as determined by digit selector signals P2, Ps and P4 to make the final sum in the accumulator (E register storage cores lEs to 4Es) and ments in storage core lKs in K register and the former addend in storage cores lFs to 4Fs in the F register.

We next refer to fig. 2. There is schematically shown a serial addition operation in accordance with the scheme in fig. 1 and comprising the principles of the invention.

The three registers comprising the adding device denoted by E, F and K registers, and all connected to period signal generator 16 and drive signal generators 38, 39 and 40. All these generators are driven from a common plus source 15. E, F and G registers comprise each several magnetic cores and a transfer circuit 22, 23 or 24. As shown, the magnetic cores arranged in each of the E, F and K registers can be considered as forming two sections, a storage section 25, 26 and 27 and a control section 28, 29 and 30. It will be noted that the number of cores is different for different sections, thus the storage section 27 (K register) and the control section 29 (F register) comprise only a single core each, the control section 30 (K register) comprises three cores and the remaining sections each comprise four cores. It will be shown later that the number of cores required for a storage section corresponds to the number of binary digits to be stored in the register, while the number of cores required for a control section corresponds to the number of sum terms in the complex logic equation that describes the operation of the register which the steering section is part of.

Several conductors pass through the cores of the registers. The conductors 35, 36 and 37 supply pulse type signals to the cores from the clock control signal generator 38, the digit selection signal generator 39 and the generator 40 for clock signals to be stored. It will be seen that the conductor 35 is impressed with clock signal Cs for storage and that the four conductors, designated 36 for the sake of simplicity, are each impressed with one of the digit selection signals Pi, P2, p;! and P4. Sense conductors 47, 48 and 49 each pass through all cores in only one register and carry the pulse type signals from the cores to the transfer circuits 22, 23 and 24. Conductors 41 to 46 inclusive return pulse type signals from the transfer circuits 22, 23 and 24 to the cores on all registers.

When going through the core sets

for a register, the aforementioned conductors can be inductively coupled with a core or it can completely bypass a core. The connection with a core is carried out by means of a single winding around the core material in such a direction that in the case of the conductors delivering signals to the cores, that signal acting on the conductor will participate in changing the state of the core in a prescribed direction, and in in the event that the sensing conductors carry signals out of the core, a change in the core state will induce a signal in the conductor. It must be noted that the well-known device with reverse phase winding for the sense conductors in successive cores can be used to increase to the maximum the looping of reciprocating voltages induced by means of half-selected currents affecting the not fully selected cores.

The magnetic material from which the cores are made is preferably characterized in that it has a rectangular main hysteresis loop, i.e. B-H curve as shown in fig. 3. The doubly stable states mentioned before will continue after core-saturation, and are the two polarities of core-remanent magnetization here termed "true" and "false", which will characterize the core indefinitely if no further pressure is applied Energy.

The impact HM required to drive a nucleus from a saturation state e.g. — B,, to the other e.g. -|- BM is critical, and the application of less than this critical application will, although it nominally causes an effect, not significantly change the prevailing saturation polarity. When applying a pressure which is at least equal to the critical value in one direction, to cause the core to adopt a saturation polarity which is opposite to the previously applied end, the saturation polarity will suddenly "switch over", e.g. from the true state to the false state along the path of the downward arrow or from the false state to the true state along the path of the ascending arrow.

We refer again to fig. 2. In the present system, each of the conductors that deliver signals to the registers is connected to circuits that can generate a "half current" of energy, i.e. half the pressure required to change the state of the core or no pressure, i.e. zero current at a specific time. Such conductors which pass through and connect a core in the same electrical direction so that currents in it are cumulative in their effects on the core polarity are so indicated by diagonal marks across the cores in the same direction as diagonals 50 and 51. Such conductors which are opposite in polarity to these are indicated by diagonal marks with an opposite slope such as the diagonal 52.

Switching is therefore carried out by simultaneous application of half currents from two sources. As previously stated, these sources are a clock signal Cs or Cc and a digit selection signal Pi, P2, Ps or P+. Further core coupling can be prevented by at the same time applying a half current from one of several other sources, e.g. a "stop" signal from transmission circuits 22, 23 or 24.

A core, if in the false state, will be switched over to the true state by means of half currents in the same direction from left to right in fig. 2, on one of the conductor 36 and on the conductor 35 or the conductor 37. A core will, if in the true state, be switched over to false by the coincidence of half currents from right to left. If you count currents from left to right as positive and those from right to left as negative, you will see that e.g. for core lEs, only a positive half-current on each of the conductors carrying the signals Pi and Ca and flowing simultaneously can switch the core from false to true state, and vice versa only a negative half-current on each of these two conductors and flowing at the same time, can switch the core from true to false state. It will further be understood that when a core is polled, it is supplied with a full negative current that does not occur in it, so that its resulting state is the false state. When a core is to be tuned, it is supplied with a non-occurring full positive current so that the resulting state becomes the true state. It thus follows that a negative half-current which is simultaneously sent from the generator 40 for the storage clock signal and from the generator 39 for the digit selector signals can "interrogate" the storage cores, while a positive half-current which is simultaneously sent from these generators can set the storage cores. In a similar way, a positive half-current that is sent out simultaneously from the generator 38 for the control clock signals and from the generator 39 for the digit selection signals can set the control cores, while a negative half-current that is simultaneously sent from these generators can query the control cores.

As we refer further to the terminology to be used here, one will also notice that a core in true state will be considered as storing a binary digit "one" and that this state for e.g. core lEs will be symbolically denoted by 1ES, while a core in the false state will be considered as storing a binary digit "zero" and that this state for e.g. core lEs will be symbolized by the designation 1ES'. When the signal is defined in Boolean terminology, i.e. in terms of the outputs of the transfer circuits, the signal required to set this core to the true state will be designated as read, while the signal required to query this core and transfer it to false state which in the present embodiment occurs at the end of each W,, and W, period will be drawn as 0les.

Fig. 2 further indicates that the signals generated by the digit selector signal generator 39, the control clock signal generator 38 and the storage clock signal generator 40 are synchronized over a common pulse source 15 which can be a multivibrator or similar which can work with a repetition rate of

400 kp/s. Such sources are well known and will not be described in detail here.

In addition to this, it is noted that the "or" gate 20 is supplied with signals W,, and Ws by means of the period signal generator 16. Generator 16 comprises a network whose output voltages are square wave signals with amplitude from 0 to -10 volts synchronized to act on the respective lines during the periods W,, and Ws. This type of arrangement is also well known and will not be described further.

We refer to fig. 4. Here is shown the group of waveforms for timing current which waveforms, when generated synchronously, can one after the other query and set cores through which the conductors carrying these signals pass. Each signal is a square-wave shaped current having maximum values, which at regions 54 and 55 for signal Cs the wave is equal to the positive or negative half current. These maximum values exist for each case for a period of time slightly above the switching time required by the core material and the phase position of the currents with a negative half-current for signal CB or C(. with a negative half-current for signal Pi, Pi>, Ps or P-t and is set to the coincidence of positive half-current or signal Cs or Cc with a positive half-current of signal Pi, P2, Ps or P4. Both coincidences occur twice in the course of the digit transfer cycle, the periods for the occurrence of the former are denoted Rs (affecting a storage core) and R,, (affecting a control core) and the periods of occurrence of the latter are denoted Wc (affecting a control core) and Ws (affecting a storage core).

Fig. 5 shows an alternative set of waveforms that will complete the same sequence of questions and setting cores. In this figure, for the sake of simplicity, the signals Pi, P2, Ps or P+ are generally denoted as the signal P. With this arrangement, however, one must note that the direction of the windings through the control cores will be required to be opposite to that direction

as required by the waveforms of fig. 4. In other words, a coincidence of negative half-currents can set a control core while a coincidence of positive half-currents can query a control core.

Fig. 6 shows a group of waveforms which illustrate the effect on a core condition by application of the magnetomotive force with switching amplitude, i.e. a full current flowing through the core windings. Line I shows the total current applied to a storage core such as the cores lEs (Fig. 2) during a digit transfer cycle

(fig. 4) assuming that there are no stop currents present. It is seen that a negative full current amplitude 56 exists during the period Rs and a positive full current amplitude 57 exists during the period W„ and zero current amplitude 58 exists during the periods W,, and R,.. The resulting flux pattern for a previously true state of the core is shown in line II. It is clear that flux current variations such as the fall 62 and the rise 63 occur along the hysteresis loop (Fig. 3) in accordance with the change in current amplitude. Line III is a graphical representation of the voltage induced on the conductor 47 for the core lEs (fig. 2) as a result of the change in flux pattern. It will be noted that the phasing gene is arranged so that a negative full-current amplitude 56 (line I) polls a core and transfers it to the false state and causes the induction of negative voltage pulse 73, while a positive full-current amplitude 57 by setting a core to another condition causes the induction of positive voltage pulse 70. On line III, low-level induced voltages, such as pulse 69, are also produced when the core magnetism changes from saturation BM to remanence BK. Lines IV, V and VI show similar curves for a control core such as the core lEc (fig. 2).

Those skilled in the art are well acquainted with the art of generating square wave signals with current such as signals Cs, C(. and Pi to P.i inclusive. It should therefore be sufficient to emphasize that each of these is an inverting square wave form with tapers of half current amplitude , when they appear on their respective lines. It must further be noted that the waveforms of Fig. 4 will be used for illustration. It must be further noted that signal C(. is identical to signal Cs, but is shifted by two periods in relation to this, and that each of these signals is at zero current level for half of the digit transfer cycle.Furthermore, it is noted that the signals Pi, P2, Ps and P+ act successively on their respective conductors, but whichever acts effectively is synchronized with the generation of signals Cs and C. , as shown. It thus follows that each of these P signals appears only during every fourth digit transfer cycle, but it is also effective to establish by combination with C„ and C,. , the four closing periods R., W,, R. andWs.

It has been stated in connection with fig. 2 that the pulse voltages induced on the sense conductors 47, 48 and 49 as a result of a change in the core state comprise the inputs to the transmission circuits

22, 23 and 24 and that the transmission circuits are identical. These circuits will now be described with reference to the E register transfer circuit 22 which is shown in fig. 7.

The voltage pulses carried by conductor 47 provide an input to amplifier 60. The phase of each of these pulses is negative due to the direction of conductor 47 entering through the core. Amplifier 60 is gated to pass a signal on line 47 using of another input signal W(. + Ws from the "or" gate 20. This signal has the ability to block the line in the amplifier 60 during the periods W,, and W., and thus only signals appear on line 47 that occur during of the periods Rs and R|; in amplified form on line 61. Line 61 is connected as one input to flip-flop El denoted as input ei. Flip-flop El is constructed in accordance with the usual arrangement which allows triggering from one of its bistable states to the other by only negative voltage pulses applied alternatively to a pair of inputs. The input ei thus has the ability to set this flip-flop to the true state. The flip-flop El is set to the false state by means of an input oei re represented by the logical sum W(. + W... The triggering in question occurs as a result of the negative pulse produced by the fall of these waveforms, ie at the end of one of the periods W,, or Wf. The flip-flop El can thus be triggered in the periods R. and Rr as a result of a change in the state of one of the E register cores. If this occurs, this condition will persist until the end of the periods W(. and Ws.

The flip-flop El is characterized by two outputs. One output El on line 74 is only high when the flip-flop is in the true state, and the other output Ei' on line 66 is only high when the flip-flop is in the false state. Both outputs are amplified and reversed by identical amplifiers, the first by amplifier 72 and the last by amplifier 71. If we consider amplifier 71 as an example, it can be seen that its input is also gate controlled by signal W,. + Ws. However, due to the circuit arrangement of the amplifier 71, a signal on line 66 passes only during the periods W,, and Ws, and the line is broken during the periods Rs and R,.. The output of the amplifier 71, also designated as output Ei, is used as input on line 65 for the drive amplifier 68. The drive amplifier 68 provides current output on line 42 in phase with its output, this current having half the value corresponding to the switching amplitude in /2 and also designated as Ei. The driver amplifier 67 is identical to the driver amplifier 68 and provides a current output i/2 on line 41, when supplied with an input, i.e. when the flip-flop E1 is in the false state during the periods W(, and Ws. One of the transmission circuits output half-current Ei' and Ei on conductors 41 and 42 can thus only occur during the periods W(. and W,. Conductors 41 and 42 pass through register cores (Fig. 2) which are connected to vague cores as that these signals can stop the setting of the cores. Fig. 7a includes curves further illustrating the operation of the transfer circuit 22 for two representative transfer cycles. The successful query of the E register cores will be assumed to occur during two successive query periods Rc and R „ and which results in the negative pulses 80 and 82 shown for one wave on line 61 (Fig. 7). Amplifier 60 (Fig. 7) is active during these periods and thus the pulses 80 and 82 will provide true trigger pulses 84 and 86 for flip-flop El. At the end of each setting delay period, i.e. at the fall of the pulses W„ and W, such as 87, 88 and 89, false trigger pulses such as pulses 90, 91 and 92 will however be produced which reset flip-flop E1 to false state. The output Ei on line 74 becomes high when it coincides with pulses 84 and 86 and becomes low when it coincides with pulses 91 and 92. Since the amplifiers 71 and 72 are blocked during the interrogation periods, i.e. during the period W„ for the first digit transfer cycle and period W„ for the second digit transfer cycle that the output Ei on line 65 is high and the output Ei, on line 65a is low. It follows from this that output Ei on line 42 is also high, and output Ei' on line 41 is also low only during these periods. As a result of a change of state and of an E register control core during the period R,, for the first digit transfer cycle, e.g. a stop signal half current 93 (Ei) at the output of the E register transfer circuit during the next period Ws. However, if there is no change in the state of an E register core as during the period R„ of the second digit transfer cycle, a half-current stop signal 94 (Ei') is applied to the output of the E register transfer circuit during the next period , Ws. Fig. 8 shows the "or" entry 20 which generates the logical sum W„ + W, fed as input to the transfer circuits 22, 23 and 24. The inputs W,, and W„ to the "or" gate

20 will be sent to include square wave signals clamped between the potentials 0 and

-10 volts. This circuit is well known to ar-

both so that the output signal W,. + Ws is at the —10 volt level unless one or both inputs Wf. or Ws is at the 0 volt level, in which case the output signal W(. + Ws will also be 0 volts. The generation of inputs to these networks occurs by combining the outputs of a pair of flip-flops whose inputs are triggered in synchronism with the signal Cs. Since the circuits for generating such inputs are known to those skilled in the art, they will not be further discussed, and the symbols R3, W1, R(., and Ws will serve to denote the periods of the digit transfer cycle.

The details of the circuits comprising the transmission circuits 22, 23 and 24 will next be described with reference to the E register transmission circuit 22 in fig. 7.

The amplifier 60 is shown schematically in fig. 9.

It is a single stage amplifier with two inputs. An input is arranged for the conductor 47 on which a negative voltage pulse occurs every time a core for the E register changes state. This input is connected to the base of the transistor 59 in accordance with the indicated polarity by means of a transformer 64. The other input from the "or" gate 20 is connected to the emitter of the transistor 59 and drives transistor 59 to block when the emitter has positive voltage in relative to base, i.e. during the periods W, or Wc at which times this input has zero voltage. A pulse on line 47 produced by a change in the state of an E register core is thus passed through the amplifier 60 only during periods Rq or R(. and is reproduced on line 61 as input ei to the flip-flop E1. The amplification through the amplifier 60 is such that an output pulse from amplifier 60 with an amplitude of 10 volts will appear on line 61, and it comprises a negative reproduction of any negative input pulse of sufficient amplitude.As is known, transistor 59 has the characteristic of separating out weak induced voltages such as pulses 69 or 73 from line III of Fig. 6 and which are produced by a core state changing from a saturation state to a state of remanent magnetization It is desired that only pulses such as pulse 70 on line III and which are produced by core coupling, must go through the amplifier 60.

One can thus see that the true input ei on the flip-flop El includes negative pulses that can only occur in the periods Rs or R(..

Flip-flop El which is shown schematically in fig. 10, is seen to be of conventional design and has a pair of cross-connected transistors to maintain one mode of conduction until triggered by a negative pulse applied to the base electrode of the conducting transistor at a time when the other mode of conduction persists. To illustrate this, if flip-flop El is false, i.e. the output on line 74 is at 8 volts and the output El' on line 66 is at + 2 volts, a negative pulse ei on line 61 will cause the output E to suddenly rises in voltage to the — 2 volt level and at the same time the output Ei' will fall to the 8 volt level. Flip-flop El is thus triggered to the true state and will remain in this state until it is triggered to the false state by a negative pulse „ei which will appear at the end of the periods W(, or Ws.

The outputs Ei and Ei' of flip-flop El are both amplified and reversed in amplifiers 72 and 71. These amplifiers are similar and for illustration the latter is shown in fig. 10a.

Amplifier 71 is seen to provide one-stage amplification for input on line 66 which is gated to only drop forward, when the emitter of transistor 75 is at the 0 volt level ie only during the periods W,, or We. The output on line 65 is held at -10 volts during the periods Rq or Rr. and will rise to 0 volts during the periods W(. or Ws, but only if flip-flop El is false.

Fig. 11 shows the drive amplifier 68, a conventional two-stage amplifier which serves as the source of the relatively high half-currents required to stop the switching of the cores. The input is on line 65 from amplifier 71, fig. 10a) and the output in phase with this is also designated as signal Ei and appears on conductor 42 which is threaded through the registers (fig. 2). The drive amplifier 67 in fig. 7 is in all respects similar to the drive amplifier 68 and supplies the stop signal output denoted by El' on conductor 41.

By summing this up, it is obtained that the transmission circuits 22, 23 and 24 (Fig. 2) supply half-current stop signals to the E, F and K registers in accordance with a prescribed scheme in the following manner. If a core changes state during an interrogation period (period R, or R,.), a stop signal appears during the following set period (period W(1 or WJ) on the true transfer circuit's output leads 42, 44 and 46 in that register containing the core. If no cores change state in 1 open of an interrogation period, a stop signal will appear during the following set period on output conductors 42, 43, and 45 of the dummy transfer circuit's output. Finally, any change in state of a core during the setting period be inactive in that they are prevented from entering the transmission circuit.

An examination of the arrangement of the wiring for the cores in the registers of fig. 2 will show that the cores can be affected by various transfer circuit stop signals generated during the setup periods W(, and Ws of a digit transfer cycle. The following tables Ia, Ib and Ic give the cores for each of the registers and indicate the stop signal outputs for the transmission circuits with which the core is wound.The table also shows the periods during which the said inherent stop signals are able to tune the cores.

It must be noted that the control cores for a register always remain in a "zero" state before the period Wc and can be set to a "one" state at each W(. period if none of the stop signals with which they are effected become effective, i.e. have high potential under W,..

It must also be noted that the selected storage cores in the register are all in a "zero" state before the period Ws, as the ones stored in them have been read in the previous Rs period and thus each of these cores can be in a "one » condition during a P selected W's period, if none of the stop signals with which they are provided become effective, i.e. have high potential during

The periods for a transfer cycle occur as described earlier in the following order: Rs, Wc, R(, and Ws. For clarification, one must thus, with reference to the E register cores shown in tablell la, first notice that the core lEs will become true, i.e. store a "one" at period PiWs unless stop signal Et' is generated at period PiWs Signal Ei' will not be 'generated at period Ws if at least one of the cores lEc to 4Ec inclusive was polled successfully, i.e. . that a digit one was read at the previous period PiRc. One of these control cores must therefore be set at period PiWc, in order for core lEs to be able to possibly set true in the period PiWs.

This procedure applies to each of the cores 2Es, 3Es and 4Es and realizes that these cores are selected one at a time by means of signals P2, P3 and P4 to be influenced in turn together with all the control cores lEc to 4Ec inclusive and comprehensive E register logic.

The sequential influence of the circuit elements in fig. 2 will now be analyzed in general for the first digit transmission cycle of an addition Pi in which the final state of the kernel lEs (subsum) will be shown to be a function of the initial state of the kernels lEs (first addend), lFs (addend) and lKs (mente), as shown in Table IA. It will be noted that a core in true state is considered as storing a "one" and a core in false state is considered as storing "zero".

In order for core lEc to be set at period We, stop signals Ei', Fi' or Kt' (table la) must not be generated. Therefore, it will only be if all three cores

lEs, 1FS and 1K3 are true by period

Rs, that core 1ES will be true at the end of the digit transfer cycle: read =

lEs 1FS1KS only if all three kernels lEs, lFs and lKs are true at period Rs. With

in other words, it is only if the cores are lEs,

lFs and lKs all initially store "ones" that the core lEs will eventually store a "one".

In order for core 2Ec to be set in the period We, stop signals Ei', Fi or Ki must not be generated. It is therefore only if core lEs is true and cores lFs and lKs are false at period Rs that core lEs will be true at the end of the digit transfer cycle: les = lEslFs'lKs'. In other words, if core lEs initially stores a "one" and the cores lFs and lKs to

to begin with stores "zeros" that kernel

lEs will eventually store a "one".

In order for core lEc to be set at period Wc, stop signals Ei, Pi' or Ki must not be generated. Therefore, it is only if lFs is true and cores lEs and lKs are false at period Rs that core lEs will become true at the end of the digit transfer cycle: les = 1Es'1Fs1Ks'. In other words, if core lFs tii initially stores a "one" and cores lEs and lKs initially store "zeros", then core lEs will eventually store a "one". In order for core 4Ec to be set at period Wc, stop signals Ei, Fi and Ki' must not be generated. Therefore, only if core lKs is true and cores lEs and lFs are false at period Rs that core lEs will become true at the end of the digit transfer cycle: les =

1Es'1Fs'1Ks. In other words, if the core lKs

initially stores a "one" and cores lEs and lFs initially store "zeros" then core lEs will eventually store a "one".

The four subtotals can be combined so that they form the complete expression of the conditions under which a digit that finally appears in one of the cores lEs to 4Es will become a "one".

le, =1E6 1FS1K8 + 1ES1FB' IK/ + 1ES' 1FS1KS'+ 1ES'1FS 1KS.

This overall expression is interpreted to mean that core lEs will eventually store a one if all three cores lEs, lFs and lKs already store a one, or if any of them already stores a one.

It should be clear that the same derivation will also describe the state of the other numerical orders for the final sum, since in a register all control cores cooperate to determine the state of each storage core in turn. If, therefore, the general symbols Es, Fs and Ks are used to denote E, F and K, storage cores associated with any number order are registered, the above expression becomes: e = EsFsK, + ESFS' KB' + E,' FSK8' +

E ' F ' K .

s s "p

Fig. 14 shows the truth table of the generalized adder, and it is noted that the arrangement of the control cores and stop windings in Fig. 2 is in accordance with the adder's expression which is derived from the table and which is shown in connection with it.

The logical addition function will then be specifically described with reference to fig. 12 and 13 which give examples of the operation of the elements in fig. 2. Fig. 12 shows an example of addition of the binary number 1011 which is the addend stored in the F register to the binary number 0110 which is the first addend stored in the E register. The incoming meant 0 is stored in the K register. The four lower order digits for the sum 10001 will appear in the E register, the addendum 1011 will be reintroduced in the F register and the outgoing 1 will be listed in the K register. The intermediate order items that are generated by partial additions for the number orders 2, 2<1> and 2<2> will also temporarily be listed in the K register as the addition progresses. Fig. 13 contains curves for the waveforms that describe the operation of the circuit elements in fig. 2, when they perform the addition of fig. 12.

As already stated, four digit transfer cycles are required for the addition of the four-order binary addend into the accumulator, the digits of the order 2„ being added in the cycle Pi, the digits of the order 2<1> being added in the cycle P^, etc. The digits for each number order are stored in separate storage cores, with the digits for the number order 2n being stored in the cores lEs and lFs, the digits for the order 2<1> being stored in the cores 2Es and 2Fs, etc. In the cycle Pi, the digit in the core lFs is then added to the digit in core lEs, the total number is placed in core lEs , intermediate-order meaning is established in core lKs and the original digit in core lFs is recreated there.

If we therefore refer to period Rs in the cycle Pi in the graphic representation in fig. 13, the waveforms show that in this Rs period a digit 0 is read out by core lEs, and a digit 1 is read out by core lFs, and a digit 0 is read out by core lKs. As a result of the readings of these digits, the El', Fi' and Kl' stop outputs of the transfer circuits 22, 23 and 24 will each be at a high potential, as shown during the period Wc. The control cores for the registers shown in fig. 2, is wound so that for this combination of effective stop signals, core 3Ec in the E register and core lFc in the F register are not stopped, and therefore they are set to 1 state in the period W,.. The reading of these control cores in the period Rc will therefore result in the El, Fi and Ki' stop outputs of the respective transmission circuits becoming high with respect to potential during the period Ws. These effective stop signals therefore function to set in the period Ws a 1 representation for the sum digit (2n) in core lEs for the E register to set a 1 that was read out of core lFs for the F register back to this core and to leave core lKs in a 0 state representing a 0 mental digit.

The operation of the circuits during the cycle Pi during which the digit in core 2Fs is added to the digit in core 2Es, when taking into account the incoming mental digit in core 1Ks, can likewise be followed in the representation of fig. 13. If we thus refer to the waveform for the cycle Po in fig. 13, the waveform indicates that in period R, for this cycle, a 1 digit is read out from core 2Es, a 1 digit is read out from core 2Fs and a 0 digit is read out from core 1Ks. As a result of the reading of these digits, each of the Ei, Fi and Ki' stop outputs of the transfer circuits 22, 23 and 24 become high with respect to potential, as shown in the period W,.. The control cores for the registers become as shown in fig. 2, wound so that for this combination of effective stop signals, core lFc and core lKc are not stopped and are therefore set to a 1 state. The reading of these control cores in the period R(. therefore results in the Ei', Fi and Ki stop outputs for the respective transmission circuits getting a high potential in the period Ws. These effective stop signals function to set a zero representing the sum figure (2<1 >) in core 2Es in the E register to set a 1 that was read out from the core 2Fs in the F register back to this core and to set core IKs to a 1 state representing a mental digit.

The operation of the circuits for adding higher order digits can be explained in a similar way by reference to the waveforms in the graphic representation of fig. 13 for the Pa and Pt cycles.

With reference to the re-establishment of the information in the F register as an example of which is given by the circuit in fig. 2, it should now be clear that the system for the present invention is in no way limited to this type of work. To illustrate this, we will assume that it is desired that the F register be filled with "zeros" (the cores 1Fs to 4Fs false) at the completion of the addition. To achieve this, it is only necessary that the stop signal Fi' is allowed to affect only the cores 1Fs to 4Fs, the control core 1Fc not being required at all. With this circuit arrangement, regardless of the initial state of the cores 1Fs to 4Fs, these cores when the addition is complete will be false (ie filled with "zeros").

Furthermore, since in the binary number system "ones" complements only require replacing "ones" with "zeros" and "zeros" with "ones", the original stored addend in the F register can easily be modified to its "ones" complement during the addition, if e.g. a subsequent arithmetic operation includes a subtraction. This is carried out simply by using the opposite outputs Fi and Fi' of the transfer circuit 23 as stop signals, one for the storage cores 1Fs and 4Fs and the other for the control core 1Fc. With this arrangement, regardless of the initial state of a storage core, its state at the end of its corresponding digit transfer cycle

become the opposite.

It will be noted from these examples that both outputs of a transmission circuit are equally effective in providing stop signals as long as the already mentioned transmission operating specifications are maintained. It is thus clear that a large variety of choices of stop signals is permitted, and a circuit for mechanizing a logical expression can be arranged, when one uses the most appropriate choice of stop signals.

In general, the system of the present invention allows the mechanization of any Boolean equation. To illustrate this, attention is drawn to fig. 14a which is the logic circuit for the control of the K register. With special reference to the mechanization of e.g. ks the equation given in fig. 14:

ks = ESFS + ESKS + FsKs

The equation is seen to include the sum of three product terms and can logically be brought into the equivalent form:

ks<=> (<E>S' <+><F>ST+ (E/ + <K>9T +

(F/ + KST

Core lKc in fig. 2 is then seen to mechanize the sum (Es' + Fs'), as the false outputs of the E and F register transfer circuits 22 and 23 are stop wound on this core. Similarly, core 2Kc mechanizes the sum (E/ + K/) and core 3Kc mechanizes the sum (Fs' + Ks'). The first parts of these sums are mechanized by the stop type of windings in which currents act to cancel the action of currents in clock and digit selectors, the signal windings 35 and 36 and the formation of the final sum is carried out by means of the common sense winding 49. We will therefore consider the output arithmetic operations of the transfer circuit which are effective in the K register's control cores in e.g. period W,, in the cycle P2 (fig. 13). Here the stop output Ki' is shown to be impressed with a positive square wave signal, and it is shown that the stop outputs Ei' and Fi' have no current signals in the period W,.. This one stop signal waveform Ki' is sufficient to prevent the cores 2Kc and 3Kc from being driven to a true state by P and C(. waveforms with positive current. However, since the Ki' stop output is not wound around the 1Kc core, this core will be driven to a true state. It follows that the input to The transfer circuit of the K register in the following R1 period, which functions to cause the output Ki from it to go high as a result of the switching of the core 1Kc back to the zero state, will go high.

It must be noted that all functions of a calculator can be defined using Boolean equations in the form of a series of sums of products. The circuits of the present invention can therefore easily mechanize the processes of a complicated calculator on a large scale by simply threading threads through a core corresponding to all terms of a product and threading the common sense line through all the cores to be summed, to form the function.

Will we now consider the serial storage part for the four binary digits which storage part comprises lEs to 4Es for the E register in fig. 2 drawn out and shown with control core logic in fig. 15 as incorporated into a digit calculator. With regard to the use for

to perform an arithmetic process, the logic for the sign digit must be different from the logic for manipulating the other digits. If the same register in addition to this, e.g. shall carry out the recirculation operations, the transfer, complement

the formation and the census, will need some funds

program management be necessary. It will be noted in fig. 15 that a double diagonal 95

is used to symbolize that the signal C(.

is connected twice through the cores

lEc, 2Ec and 3Ec. This is to indicate that a

half current passing through two loops with

conductors 35 (fig. 2) around each of these

cores will be sufficient to connect

these cores. This corresponds to linking all

time digit signal (P) conductors 36 to the cores

with the same polarity. By construction in accordance with the governing

Equally, a core must be active in all of them

digit transfer cycles that perform the arithmetic work. Program management takes shape here

of program counter number outputs 0, 1, 2

and 3 which comprise combinations of stop-calculate operations Ni', Ni, Na' and N2 which

can be derived as outputs of flip-flop circuits or transfer circuits associated with a

program counter. These arithmetic operations define which of the above-mentioned four

operations are to be performed and serve to

choose the circuit arrangement to carry them out as set out in the table on

fig. 16. Thus, when the logic Ni'Nu' in fig.

15 is effective, only core lEc will be released

for connection. Then only the arithmetic operation E'

is connected to core lEc, it is seen that this core

provides for recirculation operations.

When the term NiNl>' is effective, one will see that

core 2Ec works to transfer information, digit by digit into the E register from

F register. When the joint Ni'Nu is effective,

provides core 3Ec "ener" complimenting

of the information in the E register. It will further be seen that if the K register is referred to

mental digits that are generated as a result of

an arithmetic operation, and the arithmetic operation Ki is true at the beginning of the cycle P- >, then after the character digit that

one understands is stored in the core lEs, be re-circulated unchanged by the core of 4Ec, the cores 5Ec and 6Ec provide for the addition of a

unit (under the control of the link N1N2) to

the number stored in the cores 2Es, 3Es

and 4Ec. This is of course the counting operation.

Claims (3)

1. Switching circuit with magnetic cores comprising a magnetic control core (Ec) which is adapted to receive drive currents supplied to drive windings on the core during selected periods of a cycle of core drive currents or to receive drive currents and data signals applied to one or more data windings on the core and a magnetic storage core (lEs) equipped with drive windings arranged to receive drive currents (39, 40) during selected periods of said cycle or to receive drive currents and data signals on a data winding which is connected with an output line on the control core in such a way that at the end of the cycle data is stored in the storage core in dependence on data that has previously been stored in the control core, characterized in that one or more stopping lines (e.g. 41, 43, 45) are arranged on the control core (lEc) designed to always be supplied with stopping currents when a driving current (Wc) which works to drive the control core to a remanent state, must be made inactive, and that there is arranged between the control and storage cores (lEc, lEs) a transmission circuit (22) whose input is connected to the output line of the control core (lEc) (47) and whose output is connected to a stop line (41) on the storage core (lEs) in such a way that whenever the control core is switched from one to the other remanent state by means of the drive current (Wc), o the transfer circuit (22) reacts to the output signal on the output line (47) in such a way that it supplies a stop signal (Ei') to the storage core stop line (41), so that a drive current (Ws) is rendered inactive with regard to connecting the storage core. 2. Connection circuit as stated in claim 1, characterized in that an output line (47) from the storage core is connected to the input of the transmission circuit and that the output from the transmission circuit (22) is connected to the stop wire (41) on the control core (lEc). 3. Connection circuit as specified in claim 1 or 2, and where a single magnetic storage core and a plurality of magnetic control cores are arranged in connection with the transmission circuit, characterized in that the control cores are equipped with different combinations of stop wires, and that the transmission circuit (22 ) comprises a flip-flop circuit (Fig. 7) which has an output connected to the stop winding on the magnetic storage core and that one trigger input of the flip-flop circuit is controlled by the drive signals (Wc, Ws) and that another trigger input is controlled by signals on the output line (47) in conjunction with drive signals (Wc, Ws) in such a way that data read from the control cores at one period (Rc) of the cycle is stored in the flip-flop and transmitted as a stop signal to the stop wire on the storage core during another period (Ws) of the cycle.