NL9500101A - Tuning circuit - Google Patents

Abstract

Circuit device for tuning to a television signal from a number of radio signals which can be received on a television receiver, connected to a display device, provided with a processing unit, and means for feeding coded input data to the processing unit. The processing unit has an internal memory device for retaining specific prior input data. The circuit device furthermore comprises an audible alarm device, and the processing unit has means to transmit signals to the audible alarm device to generate audible signals in order to signal to the user to check specific combinations of the input information and the information retained in the memory. <IMAGE>

Description

Tuning chain.

The invention relates to a circuit device for tuning a television signal from a number of radioelectric signals, which can be received on a television receiver, connected to a display device, provided with a processing unit, and means for supplying coded input data to the processing unit.

The tuning system commonly used in television receivers for tuning to the desired channels is the so-called frequency "synthesizer" system. With this system, a number of advantages can be achieved by using integrated circuits over the other known systems such as the conventional mechanical memory systems with potentiometer, which were common until not so long ago, and also compared to the more recent so-called voltage synthesizer. systems. The frequency build-up "synthesizer" system is fully electronic, allowing each channel to be queried directly by the user, who indicates the channel number on a keyboard or other operating means. The system usually consists of a quartz-controlled reference oscillator, a phase lock loop, a programmable divider, and a computer, which feeds the number to the programmable divider in response to the channel number set by the user.

The phase lock loop for each channel number set by the user maintains the frequency of the receiver's local oscillator so stably and precisely that the receiver is perfectly matched to the corresponding channel signal. For more detailed information on frequency building tuning systems, see the article "A frequency synthesizer for television receivers" by E.G. Breeze, published in November 1974 in "Transactions BTR magazine", and after L. Penner's article "Digital television tuner uses MOS LSI and non volatile memory", published April 1, 1976 in "Electronics".

The frequency build system lends itself well to a number of different television channel tuning modes: - direct dialing by specifying the required channel number (according to the European standard, the VHF band channels are numbered from 2 to 12 and the UHF band channels from 21 to 69, while according to the US standard the VHF channels from 2 to 13 and the UHF channels from 14 to 83); - memory selection: each of a certain group of keys corresponds to the given channel, which has been selected and previously stored in memory; - automatic scanning of all channels of a given standard or all channels, stored in the memory, or continuous scanning of all available frequency bands.

In the former case, a direct choice can be made of each of the channels of the respective standard (in Europe 60 and in America 82).

In the second case, one of a limited number of preferred channels can be detected more quickly.

In the third case, a quick simple way is provided for figuring out which standard channels can be received, which channels are stored in memory, while further checking whether other broadcasting stations are present at non-standard frequencies such as private broadcasting stations in Italy (of which there are currently more than 100 are employed).

Frequency building systems operating according to the above three options are known from German patent applications 26.45.833 and 26.52.185 and in particular from Italian patent application 69.950-A / 77, filed December 30, 1977 by the applicant.

All of these modes of operation, which are particularly useful in areas where a number of transmitting stations can be received, require a very complicated control device, which is difficult to operate for many users. This is especially true when, in addition to the necessary controls for setting the transmitter selection and the standard receiver (volume, brightness, color, etc.), provision is also made for additional associated functions such as a digital clock, which require additional adjustment controls. Furthermore, in the event of power interruptions, it should be possible to retain channel information stored in memory. This can be done in the known manner by using a permanent external memory (battery-powered low-power CMOS memory or permanent MNOS memory). Nevertheless, it has been found that some of the information in the memory can be lost during the transition state between power failure and power back.

The object of the invention is to provide a chain construction for a television receiver, with which the above-mentioned many functions can be performed in a simple and inexpensive manner with as few operating problems as possible for the user. In addition, the invention provides in particular a simple, effective alarm system, which, controlled by the processing unit, alerts the user in case incorrect tuning operations are likely to take place.

According to the invention, a tuning circuit is provided, as described in the preamble, characterized in that the processing unit has an internal memory device for storing certain, previous input data, that the chain device comprises a sound alarm device, and that the processing unit has means for connecting to the audio alarm device output signals for generating audio signals, to alert the user to checking certain combinations of the input information and the information stored in the memory.

The design can expediently be such that the sound alarm means consists of first means for supplying acoustic frequency signals, second means for combining the acoustic frequency signals with the low-frequency audio signals obtained from the received television signal, and that these second means are located downstream of compared to the manually operated volume control on the television.

The invention will be explained in more detail below with reference to the drawing, which shows by way of example a favorable embodiment of the chain construction according to the invention. Herein shows:

Fig. 1 is a block diagram of the relevant part of a television receiver according to the invention,

Fig. 5 in more detail the unit 16 of FIG. 1, and

Fig. 7 is a block diagram of a sophisticated embodiment of the circuit of FIG. 1, showing only its various aspects.

As shown in Fig. 1, a receiving antenna 1 is connected to a capacitance diode tuner 2, at the output of which a converted intermediate frequency signal is output.

The tuner is of the known type and consists essentially of a selective amplifier stage, a mixing circuit, and a local oscillator circuit.

One output of the local oscillator circuit is connected to a first frequency divider circuit 3, in which a division by a constant number value N1 is performed and the output of which is connected to the signal input of a second divider 4, in which a division is performed by a variable number value N with 12-bit programming, which means that this divisor can divide by any number 12 from 1 to 2

The output of the divider 4 is connected to a first input of a phase frequency comparator circuit 5, the second input of which receives a differential signal from a quartz generator 6 via a third frequency divider circuit 7. The output of the comparator circuit 5 is connected to the capacitance diode voltage control input of a tuner. amplifier and filter chain 8.

There is also a control unit 10, which consists of a keyboard, which, in addition to the control keys not shown in detail, such as for the on / off functions, volume, brightness, contrast and color adjustment, also contains ten number keys, which are marked with 0 to 9 (or letter keys, marked with A, B, C, D, E, F, G, Η, I, L), as well as seven auxiliary keys, marked with +, -, T, C, OR, M, CT (or +, -, R1, R2, R3, R4, CT).

This operating unit 10 is connected to a first group of eight input-output terminals of the processing circuit 11 and to the address inputs of the memory chain 12. The processing circuit further comprises a second group of eight input-output terminals, which are connected to the information input output contacts of the memory circuit 12 and the inputs of the character generator circuit 16. This in turn is connected to the display device 9 (which comprises the display tube on the receiver), while a third group of sixteen connection contacts is connected to: - twelve programming inputs of a 12-bit divider 4; - two band switching inputs (ü and BUI) of the tuner 2; - a control input of the character generator chain 16; - a first entry of the combining chain 14.

The memory circuit 12 further includes control input terminals connected to the output of the combining circuit 14, which receives a signal from the circuit 11 at a second input and a signal from an on-detector circuit 15 at a third input. The circuit 15 receives a signal from the power supply to which the television receiver is connected, and its output is connected to a reset input of the circuit 11.

The memory 12 and the low current-consuming CMOS combining circuit 14 are connected to a local battery power source 13.

The operation of the above-described chain construction will be explained in more detail below.

The circuits 3, 4, 5 and 8, together with the capacitance diode-driven local oscillator (VCO) in the tuner 2 form a phase lock loop, which is controlled by the reference signal supplied by the quartz generator 6 and divided in a known manner by the divider 7 .

The divider 3 serves to reduce the frequencies involved at more easily processable levels, while the programmable divider 4 can establish the interlock for a number of local oscillator frequencies, i.e. acts as a frequency build circuit.

After the division number N has been chosen for the divider circuit 4, the phase frequency comparator 5, the tuning circuit 2 is supplied via the amplifier 8 with a voltage to satisfy the state equations:

f2 = P.N. (2) where f2 is the oscillation frequency of the local oscillator chain in the tuner 2, f6 is the oscillation frequency of the reference oscillator circuit 6, N2, N ^ and N sub-ratios

. . NI

of divisors 3, 6 and 4 and P = f6, N2 * ', respectively, which indicate the system frequency degree of variation, i.e. the extent to which the local oscillation frequency varies with respect to variations of the numerical value N.

The receiver must be capable of being tuned to broadcast stations of a given transmission standard, for example CCIR / BG with a channel format as agreed at the European Radio Broadcasting Conference in Stockholm in 1961, i.e. broadcast stations at one-step intervals between adjacent channels of 7 MHz on the (VHF) bands I and III and channels of 8 MHz on the (UHF) bands IV and V at a video signal bandwidth of 5 MHz. These broadcasting stations fall within television channels 2 and 69 (video carrier frequencies of 48.25 and 855.25 MHz, respectively) at an intermediate frequency of 38.9 MHz. This means that the local oscillator of the tuner must be able to control frequency in the range of 87.15 to 894.15 MHz. When a frequency variation degree P = 0.25 MHz is selected, substitution of this value in the above equation (2) will yield the following values in the above channels:

By varying the numerical value N between this maximum and minimum, you can tune in to any television channel on the VHF and UHF bands with a maximum error of 125 KHz.

This frequency range cannot be used in its entirety, so that the tuner is provided with two band switch inputs U (UHF / VHF) and B (BIII / BI) to ensure that only active bands are covered.

Divider 3 is of the very fast emitter-coupled logic (ECL) type, which is divided by 64 (SP 8750). The divider 4 is of the programmable transistor transistor logic (TTL) type, which can operate up to frequencies of about 15 MHz (3 x SN74LS191). Chains 5, 6 and 7 consist of an integrated circuit SP8760 with a quartz crystal frequency of 250 KHz and a dividing ratio N2 = 64, so that comparator 5 operates at a frequency of 3906.25 Hz, which corresponds to a quarter of the line frequency . The amplifier and filter circuit 8 serves to adapt the output level of comparator 5 (maximum 5 V) to the modes of tuner 2 (maximum 30 V) and ensures the best possible filtering and closing speed.

The circuit 11, which consists of a microprocessor unit, serves, inter alia, to provide numerical values N and band switching signals for tuning to certain television broadcast stations based on information relating to the signals to be tuned as determined by the user from the operating keyboard 10. The circuit 11 can further supply or receive signals from memory 12 and output signals to the character generator 16.

The numerical value N is calculated with the relation: N = (K.F + C). 4 + S (3)

The operations shown are performed by a series of basic operations by the calculation logic unit (ALU) on the basis of commands contained in the permanent program memory, which is part of the operation chain 11, in this case using an F8- microprocessor. The constant correction C and the factor F depend on the chosen band. K is the channel number according to the said standard and the variable S can be changed by making fine tuning corrections.

If the channel number K is changed, only the frequencies corresponding to the standard channels are given a frequency change degree equal to F (8 MHz for the UHF band and 7 MHz for the VHF band), while a variation of one unit of S causes a frequency shift of 0.25 MHz.

With appropriate operation from the keyboard, various modes of tuning to a given broadcasting station are possible, making partial use of known methods.

Each time one of the keys is pressed, the processing unit 11 issues an ISO-encoded 48-character string to the character generator 16, which is usually displayed on the television screen as a three-line string of 16 characters each.

This series always contains a time indication (hours, minutes, seconds). The remainder of this sequence consists partly of fixed data from the permanent program memory (for example, "channel" and "key" shown in Fig. 1) and partly variable data depending on the operations accomplished by the user and the resulting state , which is stored in a memory buffer in the unit 11 (for example, the letter T in the mode of operation indicated in the upper right-hand corner of FIG. 1, the numbers 21-01, also shown in FIG. 1, following the "channel" - indicator, which shows the channel number and tuning correction).

The time display is automatically corrected every second, even if no key has been pressed in the meantime.

When one of the keys T, C, OR or M is pressed, the corresponding mode of operation is set and stored in the memory buffer of the processing unit 11. At the same time, one or more question marks are entered into the buffer at appropriate points to guide the user in the next operation. The contents of the buffer are then transferred to the character generator and displayed on the television screen.

Some examples are given below for clarification.

When the T key is pressed, the picture shows: 00: MM: SS T KEY?

In this way, the user is notified that he has selected the T (memory selection) mode of operation and that a number key is expected to be pressed (this is an emitter memory number key). In the example above, N.B .: 00: MM: SS represents the time indication (hours, minutes, seconds).

When the C key is pressed, the picture shows: 00: MM: SS C CHANNEL ??

In this way, the user is notified that he has selected the C mode (direct selection) and two keyboards are expected to be pressed (channel number required).

If the number indicated on these two keys corresponds to a channel in the standard, this number will be displayed instead of the two question marks next to the "CHANNEL" indication. Conversely, if the channel number does not correspond to one in the standard, the figure will show: 00: MM: SS C CHANNEL ?? 88

In this way, the user is informed that the operation setting (channel 88 not covered by the C.C.I.R.standard) has not been made and further instructions are awaited.

When the OR key is pressed, the figure shows:

??: ??: ?? T CHANNEL 21 + 01 KEY 0 OR

From this, the user can conclude that the television receiver is still set to the operating mode T, i.e., tuned to channel 21 with a tuning correction corresponding to one scale shift over 250 KHz, stored in memory with the key 0, and six number keys are expected to be pressed consecutively, corresponding to hours, minutes and seconds, to which the clock must be reset.

When said six keys are pressed, the corresponding number will be chipped in place of the OR designation and pairs of numbers will replace the symbol ??, which corresponds to hours, minutes and seconds, provided that the numbers are acceptable.

In essence, the device will check the group of numbers and if the hour number is above 23 or the number corresponding to tens of minutes or seconds is above 5, the two numbers (hours, minutes or seconds) are rejected and the two question marks remain displayed to notify the user that the device is waiting for another pair of acceptable numbers to be set. After the operation has taken place, the clock will start counting from the time set by the user.

The arrangement is such that, following a power supply interruption, a series of zeros is displayed for the hours, minutes and seconds and the clock remains in this state to notify the user that the power supply has been temporarily interrupted.

When the M key is pressed, the picture will show: 00: MM: SS T CHANNEL 21 + 01 KEY #? Μ

This informs the user that the television is still in operating mode T, that is, tuned to channel 21 with +01 tuning, and that it is waiting for a number key to be pressed to select the channel being tuned, to keep in memory. For example, if the 0 key is pressed, the image shown in Figure 1 will appear and the channel will be coupled with the 0 key for memory selection.

When the + key is pressed the display will show: 00: MM: SS T CHANNEL 21 + 02 KEY 0

This informs the user that the television is still set to the T mode and that additional tuning corrections are made, i.e. in the direction of the sound beam of the received video signal.

Obviously, due to the presence of the programmable divider chain cell, the chain 11, a suitably modified number N is issued and this tuning state is automatically associated with the key 0 in memory. Similar operation occurs when the button is pressed except for the directions of the tuning setting (in the video direction). Once nominal tuning has been reached, the "+" mark and the next number can be erased, while for more imperfect tuning states, the mark appears, followed by the number of moves performed. The system is designed to limit maximum variations to the range from -16 to +15. Of course, the tuning correction can be carried out in the same manner, even when the device is in the direct selection operating mode C. In this case, the operation is not accompanied by automatic memory storage. For the channel and the obtained tuning state to be stored in memory, press the M button followed by a number button.

When the key (keyboard switch) CT is pressed, the following image appears: 00: MM: SS * T *

CHANNEL 21 + 01 KEY O

The symbol indicates the working position display. This notifies the user that the device is set to perform a further set of functions corresponding to the second indication on each key. In this operation, the processing unit 11 will output to the drawing generator 16 a switching signal for switching the color of the inscription on the screen or the background color in order to make it more clear to the user that the operations available from this point on correspond to the second key instructions (this of course applies to color television receivers).

If one of the keys A to L is pressed, the picture will show: 00: MM: SS * C *

CHANNEL A

This informs the user that the television is set to the operating mode C, but in this case the channels can be selected directly according to the Italian standard by pressing a single key indicating the received channel.

When one of the keys R1, R2, R3 or R4 is pressed, the picture shows for example: 00: MM: SS * 1 * CHANNEL 21 + 01

KEY O RA

This informs the user that the device is performing an automatic scanning operation, for example of type 1, or that all channels in the memory are being scanned.

Scanning will continue automatically every two seconds with instructions from the keyboard and associated channel. At the same time, the processing circuit 11 supplies the relative N numbers for receiving the channel. Scanning is stopped when another key is pressed. If the "+" or button is pressed, the unit remains set to perform forward or reverse operation steps manually (each time the "+" button is pressed, the button number is increased and each time the button is pressed, the channel number decreased). When the CT key is pressed, the unit switches back to the first keyboard and waits for further commands, especially for tuning correction operations to memory storage. Similarly, if the R2 key is pressed after selecting the second keyboard using the CT key, a type 2 scan operation will be pressed to scan all standard channels (one switch per second). This can be terminated in the same way as the type 1 scanning operation.

When the R3 key is pressed, it initiates the continuous scanning of the frequency band in 1 MHz steps, i.e. four fine tuning switches per second, to detect the operation of a transmitter over non-standard frequencies. The same type of scanning operation, although at a reduced speed (one switch every 2 seconds) is initiated by pressing the R4 key.

The indication "KEY" is not cleared during the scanning operations of types 2, 3 and 4.

The display or omission of the fixed channel and key indications depends on whether the indication or blank sectors of the permanent memory are used. The circuit 11 further includes a timer 15 seconds after the last key is operated, outputting a switching signal (bit 6 port 1) to the character generator 16, which reduces the image by one line and also reduces the height of these characters (7 instead of 14 television lines) in order to reduce picture interference. This switching signal is of course not supplied during the automatic scanning or clock setting.

In order to prevent information stored in memory from being lost during a power interruption, a battery-powered external memory access device is provided. Whenever a memory operation is performed, the processing unit 11 will update the information in the immediately accessible memory. When the power supply is restored, the processing unit 11 will again request the information stored in the directly accessible memory.

The "ON RESET" circuit 15 and combining circuit 14 secure the information stored in the freely accessible memory 12 during transition states between power failure and recovery.

Fig. 5 is a block schematic, but in more detail, the drawing generator 16 of FIG. 1.

In Fig. 5, a character counter chain supplies addresses to the 48 x 6 character memory 61 for storing 48 characters, which are periodically output from the processing unit 11.

The six input / output terminals of the memory are connected to six output terminals of a port 71 of the information processing unit 11. Furthermore, they are connected to the six inputs of the permanent character memory 62.

For example, it may be of the Fairchild 3258 type for storing 64 characters, for each of which it provides an image consisting of a matrix of 5x7 points. Each character is separated vertically from the next by two blank lines (lines with empty places).

A built-in counter, which receives a clock signal with a horizontal scan frequency FH from the television chains and a countdown signal R1 from the circuit 60, scans the following dot lines of the matrix.

The five outputs of the permanent memory 62 are connected to a parallel / series converter circuit 64, which converts the five signals received from the five outputs into a series signal. Furthermore, this converter adds an appropriate number of empty spaces or spaces (e.g. 3) to the end of these five signals to separate the characters horizontally.

The circuit 63 receives a clock signal from the oscillator circuit 66, the frequency of which determines the width of each of the characters subtracted on the screen. Furthermore, it receives a LOAD signal L and every character (every 5 + 3 = 8 clock cycles in the given exemplary embodiment) from the divider circuit 67, which in turn receives the clock signal from the oscillator circuit 66. It thus receives it at the output of the converter 63 signal is applied to the combining circuit 64, which consists of known logic elements (e.g. three AND gates with two inputs, each of which the first input is connected to the output of the circuit 63, while the second input is connected to one of the outputs of the circuit 65), which combining circuit outputs the signal to one or more of its three outputs R, G and B in response to the same number of control signals supplied by the control circuit 65. The outputs R, G and B are in known manner connected to the amplifier circuits of the color signals, so that the signals supplied by the circuit 64 are added to the video signals of the received television signal.

Depending on the instructions received from the chain 65, it is possible to obtain the clues in one of the three primary color combinations.

In Fig. 5, the control circuit 65 receives a control signal from an output of the circuit 71, which corresponds to the gate 4 of the unit 11 of Fig. 1, so that the indications are displayed in green color when the system is set to the first keyboard and displayed in yellow color when set on the second keyboard.

Furthermore, three identical switching circuits 68, 69 and 79 are provided, which are controlled in parallel by a control signal DT provided by a bit of port 1 of the processing unit 11 of fig. 1. Depending on the signal DT, the three switching chains are supplied by the in Fig. 5 released to be set to input the information into the memory 61 when the signal DT is present (high logic level) and conversely set these circuits to output the information from the memory to the outputs R , G and B when the signal DT is absent (low logic level) or when the unit 11 does not output characters to the memory 61 (for updating the picture).

To this end, when the signal DT is absent, the switches 68, 69 and 70 are set to the positions A in FIG.

5. This will apply a reset pulse to the input terminals R2 and R3 of the counter circuit 70 and set the memory 61 to "input" by the same signal DT applied to the input / output terminal.

The counter circuit 60 receives a clock pulse DC from the output terminal of the processing circuit 11 of Figure 1 (gate 4) via the switching circuit 68. The same signal DC is also applied to the write-in control input W of the memory 61.

In this manner, for each clock clock received, addresses from 0 to 47 will be supplied by the counter 60 to the freely accessible memory 61. At the same time, 48 are supplied by the unit 11 (at the gate 4), which signals are received at the information input of the same memory so that they are stored in the corresponding memory cells as a result of the pulses W.

on the other hand, if the signal DT is absent (switches in position B), the character counter 60 receives clock signals from the circuit 66 via the divider 67, reset signals with the vertical scanning frequency FV at the connection contact R2, reset signals with the horizontal scanning frequency FH at the connection contact R3 and a format change signal comes from the processing unit 11. In this way, the memory 61 is provided with suitable addresses for arranging the 48 picture characters in three lines, each with 16 characters in case the signal F is present, while in the other in case the memory is provided with only the first 16 addresses for displaying a single row of 16 characters when the signal F is absent. Furthermore, a blocking signal is output from counter 60 to merge circuit 64 to disable it during the remaining television picture period. In this way, only a certain part of the screen is displayed, for example the top left corner. If necessary, the same blocking signal can be used to supply a blanking signal at an appropriate point in the television video amplifier circuit to suppress the background of the picture, making the characters more visible.

A further output of the circuit 71 (gate 4 of the unit 11) controls a switch 72 between a signal BIP (which can be taken from a suitable point of the circuit, for example at the output of the divider 7 in Fig. 1) and a first input of an addition circuit 73, a second input of which is the BF audio signal of the received television signal, which has been extracted beyond the manual volume control. The output of the addition chain is connected to the input of the B.F. amplifier 74, with which the loudspeaker 75 is controlled. In this way, under the given circumstances, the processing unit 11 can control the sound of an alarm signal to warn the user. These conditions can be: - When the memory button M is pressed. This alarm signal reminds the user that the key has been pressed to prevent the contents of the memory from being erroneously changed by the user.

- When an impracticable instruction has been given (e.g. the number of a nonexistent channel or time), etc.

- When the maximum allowable limits have been reached for certain settings such as tuning corrections.

Fig. 7 shows a possible variation of a certain part of the circuit of FIG. 1. In FIG. 7 only the parts which differ from those of FIG. 1 or which are connected differently are shown.

In addition to the keys already shown in Fig. 1, the operating key 120 shown in Fig. 7 contains six further keys indicated by "V +", "V-", "L +", "L-", "C +" and "C - ". The outputs of this keyboard are connected to a group of input-output terminals 5 of the processing unit 121, which substantially corresponds to the unit 11 of Fig. 1, from which it differs, inter alia, by the presence of a further group of output terminals (ports) 6.

Six terminal contacts of the group are connected to six inputs of a digital / analog converter 123 of the known type (which, for example, consists of a known network of resistors R / 2R). The analog output of this converter is fed to a switching circuit 124 with three outputs G, L and C, which are connected to three storage capacitors 125, 126 and 127 respectively. The switching unit 124 is provided with two control input contacts, which are connected to the other two output terminals 6 to the unit 121, which receive the respective control signals for further shaping analog signals to one of the capacitors 125, 126 and 127.

The terminal contacts of group 4 of the unit 121 are connected to eight input / output contacts and a directly accessible memory circuit 122, which replaces the memory 12 of Fig. 1 and which differs by the number of 8-bit cells (10 x 5 instead of 10 x 2). This memory each receives six address bits (instead of 5) from six output terminals of group 5 of unit 123.

The operation of the above circuit of FIG. 6 will be explained in more detail below.

When one of the above six keys is pressed (for example, the V + key), the unit 121 will output a combination of symbols to the character generator chain, which may include: vwvww .....

LLLLLL .......

CCCCCCCCCCC ...

The line of symbols corresponding to the key pressed (V, L, C) is shown in a different color from the rest. The number of characters per line is proportional to the corresponding analog signal level (V, L, C) at this time. Each time one of the + buttons is pressed, the corresponding analog level is increased by 1/64 of the maximum value. When an operation, which may include a memory operation, is performed (for example, each time the key mode is set or the key M is pressed), the processing unit 121 will output the relative information in digital form to the memory 122 and be stored therein. This means that the information to be stored in memory 122, which can be called up for each of the ten keys, consists of five types of data, namely those relating to the channel, tuning, sound volume, brightness and color. . To provide uniformity, the memory assumes 8-bit information, while for the analog add-ons, 6-bit (64 levels) is more than sufficient to ignore 2-bit.

Other means consist of displaying analog levels on the television screen using the character generator and the described circuit construction according to the invention. In addition to the above indications, one of the following indications may also appear on the screen: y ******* <or: VOLUME 40? BRIGHTNESS 30 COLOR 50 or: V +++++

L

C-

In the above indications, the number of asterisks is proportional to the relative analog signal level, while the indicated setting is indicated by the symbol. Furthermore, the level is indicated by the number on the first series notation side, while the setting made is indicated by the question mark. Finally, the number of + or - characters is proportional to the effected increase or decrease compared to preset nominal info. Obviously, the preselected, held levels are previously stored in the memory 122, even in the event of a power interruption, thanks to the precautions already mentioned, which also apply to the application case of Fig. 7.

It may prove useful to apply the audible alarm signal used in Figure 5 also for analog settings, for example when the maximum level is reached.

Although the above exemplary embodiments used a particular type of 8-bit microprocessor system with a separate central processing unit and permanent memory, it is also possible and sometimes advantageous to use other types of microprocessors and high numbers of internally accessible memory registers (for example 128) or to use a so-called monochip, which contains, in addition to permanent memory, an internally directly accessible memory and a timing chain, or a 16-bit microprocessor. It may also be useful to provide the receiver with a remote control. In this case, a keyboard, as described, is combined on a portable transmitter part or remote control system. In order to avoid a double design of the operating keyboard, a number of electrical contacts can also be arranged in the receiver housing for a connection to the transmitter part in order to operate the local control therewith.

It will be clear that the invention is in no way limited to the above-described embodiments, but that many modified embodiments can be developed without departing from the scope of the invention.

Claims (2)

Chain arrangement for tuning a television signal from a number of radioelectric signals which can be received on a television receiver, connected to a display device, provided with a processing unit, and means for supplying coded input data to the processing unit, characterized in that the processing unit has an internal memory device for storing certain previous input data, that the chain device comprises a sound alarm device, and that the processing unit has means for supplying signals to the audio alarm device for generating audio signals, in order to alert the user to checking of certain combinations of the input information and the information stored in memory. Chain device according to claim 1, characterized in that the sound alarm means consists of first means for supplying acoustic frequency signals, second means for combining the acoustic frequency signals with the low-frequency audio signals obtained from the received television signal and second means are located downstream of the manually operated volume control on the television.