NL8801704A - Clock signal generator for video recorder - extracts clock signal from multiple value analogue signal - Google Patents

Abstract

The input terminal (10) is connected in parallel to the inputs of three detection units (21, 22, 23), each of which detects one of the three possible signal stages. In the first detection unit (21) the input is compared (25) with a reference The output of the comparator (25) is fed via a delay unit (26) to the input of a monostable multivibrator (27). The mono output is gated (28) by the output of another comparator (24) before being fed to another monostable (29). The second detector unit (22) is a signal null detector. The third detector unit (23) is similar to the first except that the signal is inverted (46) between the delay (26') and first monostable (27') and that the cross-coupled signal from the other comparator (25) is also inverted (47). All three detector outputs are fed via a gate circuit (41) to phase lock loop circuit (44), which produces the clock signal (45).

Description

% * s PHN 12,618 1 N.V. Philips' Incandescent Lamp Factories in Eindhoven.

Device for deriving a clock signal from an n-valued signal.

The invention relates to a device for deriving a clock signal from an n-valued signal (n 23), wherein the signal can occupy a value corresponding to at least a first, a second and a third level, the second level between the first and third levels are situated. Such a device is used in, among other things, video recorders to derive the clock signal from the signal read from a magnetic record carrier during the reading of a video signal. Figure 1 shows an n-valued signal, where n = 3.

At the clock moments, in Figure 1 (a) with t ^ (where i ranges from 1 to m), the signal can take one of three values V ^, V2 and V3, respectively. The second value V2 has a level such that it lies between the other levels and V3. In general, with a trivalent signal V2 is equal to zero volts.

15 V-j is then a negative value and V3 a positive. In Figure 1 (b), the binary representation corresponding to the trivalent signal of Figure 1 (a) is shown.

If the signal has a value V2 at a clock moment, this corresponds to logic "zero". If the signal at a clock time t ^ has a value of V3, this corresponds to a logic "1".

In the known device, the signal is applied to a comparator in which the signal is compared with the voltage V2. At each intersection of the signal by the level V2, the comparator then supplies a control signal which is applied to a phase-locked loop. This phase locked loop then generates the clock signal from the signal supplied to the loop by the comparator.

The known device has the drawback that it is quite sensitive to disturbances, so that quite a few disturbances occur in the generated clock signal. The invention now aims to provide a device which is less susceptible to malfunction. To this end, the device according to the invention is characterized in that the device is adapted for the detection of the transitions in the signal from the first level, via the second to the third level, for the PHN 12.618 2. and is arranged to provide a control signal if, during such a transition, the signal crosses the second level.

The device may further be arranged for detecting the transitions in the signal from the third level, via the second, to the first level, and is arranged for supplying a control signal if during such a transition the signal cuts through the second level. .

The invention is based on the understanding that there is a high inaccuracy in the "zero crossings" at times t2 't6' * 7 '··' V-5 '* 111-4 This due to the intersymbol interference generally occurs in the signal of Figure 1 (a). The consequence of intersymbol interference is that the 15 zero crossings no longer fall exactly on the clock moments. This inaccuracy naturally has the most influence if the signal has a low level for a long time: that is, where in the digital signal two or more "zeros" follow one another immediately. In addition, the noise plays a major role at those times, which also leads to inaccuracies in the detected zero crossings. By now using only the 1-0-1 transitions in the digital signal for generating a clock signal, i.e. those transitions in which the signal transitions from the first level (V ^) for three consecutive clock moments via the second level {V2) r to the third level (V3), or vice versa, greater accuracy can be achieved. Thus, it is determined according to the invention that a 1-0-1 transition takes place in the digital signal. A control signal is then generated when the signal crosses the second level (V2). When the phase-locked loop is driven with this control signal 30, a clock signal is obtained which is less susceptible to interference.

The invention will be explained in more detail with reference to an exemplary embodiment in the figure description below. Figure 1 in figure 1 (a) shows an n (= 3) -value signal as a function of time, in figure 1 (b) the corresponding digital representation of this signal, and in figure 1 (c) the control signal which .8801704 «PHN 12.618 3 is applied to the phase-locked loop, FIG. 2 shows an embodiment of the device, FIGS. 3 and 4 show a number of signals as a function of time at a number of positions in the device of FIG. 2, and FIG. 5 show a second exemplary embodiment.

Figure 1 (c) shows the control signal applied to the phase-locked loop 44. Clearly visible are the pulses indicating the intersections by the signal of the V2 level during a 1-0-1 transition in the digital representation of the signal.

Figure 2 shows an exemplary embodiment of the device. The signal of Figure 1 (a) is applied to an input terminal 10. The signal is applied to an input of a first detection unit 21, a second detection unit 22 and a third detection unit 23. The first and the third detection unit have two comparators 24 and 25 in common. The input signal is applied to one input (+) of both comparators. The other input (-) of the comparator 24 is supplied with a reference voltage + Vrej, which lies between the levels V2 and V ^, see figure 20 1 (a). The other input (-) of the comparator (25) is supplied with a reference voltage vref, which lies between the levels V1 and V2, see figure 1 (a). The output of comparator 25 is coupled to a delay unit 26, which delays the output of comparator 25 by a time interval.

The output of the delay unit 26 is coupled to an input of a monostable multivibrator 27. The monostable multivibrator 27 generates a pulse at its output with a width of T2 on an ascending edge at its input. The output of the comparator 24 and the output of the multivibrator 27 are coupled to 30 inputs of an AND gate 28. The output of the AND gate 28 is coupled via a monostable multivibrator 29 to the output 30 of the first detection unit 21. The multivibrator 29 generates a pulse T3 on its output on an ascending edge at its input.

The first detection unit 21 detects a transition in the signal from the first level (V ^), via the second level (V2), to the third level (V3 at three successive clock moments. This will be explained with reference to Figure 3. Figure 3 shows such a .8801704 | Ί ΡΗΝ 12,618 4 transition.

The signal in Figure 3 (a) is about the time interval T. | delayed output from comparator 25, which is present at the output of delay line 26. At time t = tQ 5, the signal crosses the level -Vre £. The output of comparator 25 is going up at this time. This means that the output of the delay unit 26 at tQ + T1 goes up. This rising edge drives the monostable multivibrator 27, thereby providing a "high" output signal for a time T2.

The time intervals and T2 are chosen such that a cut of the signal by the + Vref level that should take place at time t2 falls within the time interval tQ +, tQ + T1 + T2, so that this cut can be detected.

At the instant t2, if the signal actually crosses the + Vref 15 level, the output of comparator 24 goes up, see figure 3 (c). This rising edge in the output of comparator 24 is now passed through AND gate 28 and drives the monostable multivibrator 29, which provides a high output during a time interval T3 after t2, see Figure 3 (d). In fact, this has detected that it is a 1-0-1 transition in the signal. The intersection of the zero level VQ is detected by means of the detection unit 22. The unit 22 includes a comparator 35 in which the input signal applied to the + input is compared with the zero level Vq (Vq = 0), which is the - entrance is offered. At the instant t ^ the output signal of the comparator 35 becomes "high", see figure 3 (e). The rising edge in this output signal drives the monostable multivibrator 36 which is coupled to the output of the comparator 35. During a time interval T5, the output of the multivibrator 36 is high, see Figure 3 (f), Via the OR gate 39, and the delay line 40, which realizes a delay over a time interval T4, the output of the multivibrator 36 is coupled with an input of an AND gate 43 belonging to a gate circuit 41. Thus, the input of the multivibrator 36 delayed output signal is applied to this input, see figure 3 (h). The time delay is chosen such that the pulse, which indicates the intersection through the level VQ, see figure 3 (f), falls within the time window determined by the output signal of the «8801704 *

J

PHN 12.61.8 5 multivibrator 29, see figure 3 (d) and 3 (h). The output of the multivibrator 29 is coupled for this purpose to an input of an OR gate 42 belonging to the gate circuit 41. The output of this OR gate 42 is coupled to another input of the AND gate 43. The pulse, see 5 Figure 3 (h), present at the output of the detector 22, is passed through the gate circuit 41, see Figure 3 {i), and applied to a phase-locked loop 44. The phase-locked loop 44 supplies the clock signal to the output terminal 45. The third detection unit 23 also includes a delay unit 26 ', a monostable multivibrator 27', an AND gate 28 'and a monostable multivibrator 29'.

An inverter 46 is connected between the output of the delay unit 26 'and the input of the multivibrator 27'. Furthermore, the output of comparator 25 is coupled via an inverter 47 to an input of AND gate 28 '.

Figure 4 shows the operation of the detection unit 23.

This detection unit detects the 1-0-1 transitions in the signal, namely those transitions in which the signal from the third level Vj passes through the second level V2 to the first level V1 at three successive clock moments. Figure 4 (j) shows the output signal of the inverter 46. Figure 4 (k) the output signal of the multivibrator 27 ', Figure 4 (1) the output signal of the inverter 47 and Figure 4 (m) the output signal of the multivibrator 29'. If the signal intersects the level at time tQ, then the output signal of inverter 46 goes up at time tQ +, see figure 4 (j). The monostable multivibrator 27 'generates a pulse T2 width on this rising edge, see figure 4 (3c). and T2 are again chosen such that a crossing of the signal by the level ~ Vref at time t2, see figure 4 (1), falls within the time interval tQ + T ^, tg + + T2. The rising edge in the output signal of the inverter 47 is transmitted through the AND gate 28 'and controls the multivibrator 29', so that a pulse of width T3, see figure 4 (m) is delivered. This pulse again indicates the time window within which the intersection of the signal by the zero level Vq can be detected. The detection unit 22 additionally comprises an inverter 38 and a monostable multivibrator 37 for this purpose.

The cut through the VQ level at time t2 lowers the output of comparator 35, see Figure 4 (e). By .8801704 PHN 12.618 6 inverter 38, a rising edge is now applied to the multivibrator 37, so that an impulse with width T5 is generated, see figure 4 (g). This pulse is delayed by a time interval, see Figure 4 (h), and applied to the gate circuit 41, which passes this pulse 5 to the phase-locked loop 44, see Figure 4 (i). In fact, the device of Figure 2 realizes an over-delayed detection of the 1-0-1 transitions and the associated intersection of the level V0. A correct phase relationship between the input signal and the control signal, as indicated by means of Figures 1 (a) and 1 (c), can be obtained by also delaying the input signal over T4. The phase locked loop 44 then produces a clock signal with a frequency fQ = 1 / TQ, where Tq is equal to the time difference between the clock moments in Figure 1a, or T0 = ti ~ ^ i-11 Figure 5 shows a second embodiment. The circuit is somewhat simpler than the circuit in figure 2.

The input terminal 10 is coupled to the input of a unit 22 'through a delay unit 55, which realizes a delay equal to T &. This unit 22 'looks practically the same as the unit 22 of Figure 2, except that the delay 40 is not included in the unit 22'. Thus, for each zero crossing of the signal applied to its input, unit 22 'delivers a pulse which is applied to first inputs of AND gates 58 and 59. Ta is equal to the time difference t ^ -t ^ _. J in figure 1.

The input signal is also applied to two comparators 50 and 51, and is applied to two comparators 52 and 53 via a time delay 54, which realizes a time delay equal to 2Ta.

The outputs of comparators 50 and 53 are coupled to the inputs of a NOR gate 57 and the outputs of comparators 51 and 52 are coupled to the inputs of a NOR gate 56. The output of this gate 56 is coupled to the second input of AND gate 58. The output of gate 57 is coupled to the second input of AND gate 59. The outputs of AND gates 58 and 59 are coupled to 35 inputs of an 0F gate, respectively 60, an output of which constitutes the output terminal 61 of the circuit, which can be coupled again with a phase-locked loop, not shown.

.8801704 *> PHN 12.618 7

The operation is as follows.

Comparators 50 and 53 determine a zero crossing during the situation as shown in Figure 3. The signal at the inverting input of comparator 50 is then higher than fear, so that comparator 5 delivers a low output signal (logic "0"). Likewise, the signal at the non-inverting input of comparator 53 is less than -Vref.

The output of this comparator 53 is therefore "low", so that the output of the NOR gate 57 is "high" and the pulse generated by the unit 22 'can be passed through the AND gate 59 to the OR gate 10 60 and thus to the output terminal 61.

Comparators 51 and 52 determine a zero crossing during the situation as shown in Figure 4. The signal applied to the non-inverting input of comparator 51 is less than -Vref / and the signal applied to the inverting input of comparator 52 is greater than + Vre £. The output signals of both comparators are thus "low". This means that the output of NOR gate 56 is high and the pulse generated by unit 22 can be applied to output terminal 61 via AND gate 58 and OR gate 60.

It should be noted that the invention is not limited to only the exemplary embodiment shown. The invention is equally applicable to those exemplary embodiments which differ from the exemplary embodiment shown in matters not relating to the invention. The design of the various detection units may possibly be different. Nor is the invention limited to deriving a clock signal from the signal of Figure 1a, which is known under the name of a duo binary signal. More generally, this involves deriving a clock signal from an n-worthy signal, where n 2 is 3.

.8801704

Claims (5)

An apparatus for deriving a clock signal from an n-valued signal (n> 3), wherein the signal can occupy a value corresponding to at least a first, a second and a third level, the second level between the first and is in the third level, characterized in that the device is adapted to detect the transitions in the signal from the first level, via the second, to the third level and is arranged to supply a control signal if during such transition cuts the signal through the second level. 2. A device as claimed in Claim 1, characterized in that the device is arranged for detecting the transitions in the signal from the third level, via the second, to the first level and is arranged for supplying a control signal if during a such transition cuts the signal through the second level. 3. Device as claimed in claim 1 or 2, with an input terminal for receiving the n-valued signal, characterized in that the input terminal is coupled to an input of a first detection unit for detecting a transition in the signal of the first level, via the second level, to the third level and for generating thereon a first detection signal at an output, the input terminal being coupled to a second detection unit for detecting a section through the signal of the second level and for generating a second detection signal at an output thereon, that the outputs of the first and the second detection unit 25 are coupled to respective inputs of a gate circuit, which gate circuit is arranged to pass the second detection signal to an output , in the presence of the first detection signal. 4. Device as claimed in claim 3, characterized in that the input terminal is coupled to a third detection unit, for detecting a transition in the signal from the third level, via the second level, to the first level and for 8801704 PHN 12.618 9 then generate a third detection signal at an output, said output is coupled to a third input of the gate circuit, and the gate circuit is further arranged to pass the second detection signal in the presence of the third detection signal. Device according to claim 3 or 4, characterized in that the output of the gate circuit is coupled to an input of a phase-locked loop. .8801704