NL8600606A - Signal processor for forward looking infrared surveillance system - processes outputs of multiple sensors and has temperature reference comparison cycle - Google Patents

Abstract

The Forward Looking Infra Red (FLIR) processing system (20) consists of an input processor (21), read signal converter (22) and output processor (23), all controlled by a common timing circuit (24) and a main processor (25). During each scanning cycle, the system first processes the data from the detected image and then the data from a reference temperature source.

Description

Short designation: Signal processor (processor).

The invention generally relates to signal processors for use in video data processing and the like, and more particularly to signal processors for use in multi-sensor imaging systems, such as forward-looking infrared imaging systems and the like, which provide electronically enhanced video images, slanted on a video monitor.

Conventional forward looking infrared (FLIR) sensor systems and the like are used as night vision systems in aircraft, tanks, ships and other military vehicles. For example, the conventional FLIR system includes a sensor system, a signal processor and a video display (display). The sensor contains a large number of detectors, the output signals of which are multiplexed (grouped in a common channel) and applied to the signal processor. The signal processor electronically de-multiplexes (separates the individual signals again), enhances and converts the sensor signals into video signals compatible with the video image display (display), and transfers the enhanced video signals to the display (display) by the operator of the vehicle or vessel to be viewed.

Although all FLIR systems have built-in signal processors, the unnecessary complexity and image enhancement options vary greatly from system to system. In known systems, for example, circuits are built in for equalization of the reaction power, for automatic strength control and for video compaction. However, these prior art systems have employed analog circuits to perform the gain control and video compaction functions, and have built-in hand-operated potentiometers for realizing the reaction power equalization function. The use of manually calibrated analog systems in known FLIR signal processors and the like has resulted in less than optimal behavior of these systems.

Although in a publication entitled "Reference-free nonuniformity compensation for IR imaging arays", SPIE, vol. 252, Smart Sensors II, 1980, biz. 10-17 generally refer to non-accommodating ("staring") focal plane detector arrays, discussing therein some problems related to conventional infrared signal processing, and describing a reference-free compensation scheme for accomplishing the automatic equalization of the reaction time. The compensation scheme described in this article uses scene statistics to develop signals suitable for realizing temperature compensation.

In order to overcome the limitations of known signal processing systems, the invention provides a signal processor which can be used in an image sensor system, such as a forward looking infrared (FLIR) system, etc. The FLIR system includes, for example, a number of sensors, or detectors, which are sweep across an image scene during a first portion of a scan cycle (the active portion), and swing over an internal reference temperature source during a second portion of the scan cycle (the idle or flyback portion). The signal processor according to the invention provides improved video output signals to a video display or monitor that are representative of the image scene.

The signal processor includes an input processor coupled to the image sensor system, which processes analog signals derived from each of the plurality of detectors. The input editor is arranged to normalize the analog signals relative to each other during the active portion of the scan cycle based on stored data from a predetermined calibration procedure on the sensor's response power. This normalization function ensures equalization of the gain factors associated with all channels of the sensor system. The input processor also processes the analog signals to reset the DC levels of each of the sensor channels to respective DC values related to the reference temperature source during the idle portion of the sensor. the scan cycle. This DC recoil function is performed during the calibration procedure and while the system is operating.

The input processor processes the normalized and DC reset signals to provide digitized first output signals thereof.

The signal processor also includes a scan converter coupled to the input processor, which stores the digitized first output signals in memory and processes the stored digitized signals to provide digitized second output signals that are compatible with the video monitor. The scan converter acts as a demultiplexer and interpolator for the signal processor. An output processor is coupled to the scan converter, which is used to process the digitized second output signals in a manner that allows an improvement of its software-controlled digitized image, and which converts the improved digitized second output signals to analog video output signals, that are compatible with the video monitor.

During operation, the FLIR system with built-in the signal processor according to the invention is first calibrated. For example, the FLIR system may contain 160 detector elements, the outputs of which are multiplexed before being applied to the signal processor. The detectors are typically vertically oriented and swung horizontally across an image scene. During the calibration procedure, the detectors are swept over an even temperature body that acts as a black body. Each of the detector elements has a different response power (amplification) factor, and each has different DC level errors during each scan cycle. The sensors are swept over the uniform temperature source during the active portion of the scan cycle, and then swept over an internal reference temperature source during a retrace portion of the cycle. The calibration procedure is performed for about 30 to 40 scan cycles.

Strength correction constants for all detector channels are automatically calculated during the calibration procedure. The strength correction constants are fixed for each. detector and do not change during normal operation. The strength correction constants are stored in a non-volatile memory in the input editor and are recovered when the system is turned on. The DC error correction factors are calculated during each scan cycle and applied to the sensor signals currently being processed. A microprocessor or the like. is used to calculate and check the signal processed in the input processor.

The signals corrected for strength and DC level are then digitized and stored in a scan converter memory.

The scan converter includes an interpolation section, which converts the digital data associated with each scan cycle into a field of data compatible with the video monitor. For example, the sensor system may have 160 video lines, due to the fact that it contains 160 vertically aligned detectors, which must be converted into 480 video lines processed by the video monitor.

The output processor includes a look-up table stored in a non-volatile memory. The look-up table contains a stored transfer curve, which realizes image enhancement functions. The lookup table is generated by applying statistics derived from a histogram and a histogram equalization algorithm realized in the microprocessor.

A software-controlled program, realized in the microprocessor, performs image enhancement functions, improving the image on the video monitor. Such functions as automatic volume control, automatic strength control, video compaction, image reversal and gamma correction can be realized. The output editor also includes an aperture correction circuit, which is arranged to improve the horizontal modulation transfer function (MTF) of the system in order to improve the system frequency response.

The software-driven digital image enhancement features of the present invention can be realized using a relatively small amount of standard integrated circuits. The system provides adaptive calibration by equalizing the gain factors of all sensor channels during the calibration procedure and storing the calibration factors indefinitely for use by the system. The temperature of the reference temperature source need not be known for the system to still operate properly. The DC levels of all detectors in the system are automatically reset to the DC reference temperature determined by the reference temperature source. No manual adjustments need to be made during calibration or operation.

Image enhancement functions are provided in a look-up table instead of calculated by analog circuits as in conventional signal processors. A wide dynamic range is obtained using a digital image processing circuit and techniques. Enlarged system frequency response is obtained through the aperture correction circuit. System flexibility and growth is possible and can be achieved through changes in software programs.

The invention will be explained in more detail below with reference to some exemplary embodiments shown in the figures in the accompanying drawings.

Figure 1 shows a block diagram of a signal processor in accordance with the principles of the present invention;

Figure 2 shows a block diagram of an embodiment of an input processor for use with the signal processor of Figure 1;

Figure 3 shows a block diagram of an embodiment of an output processor for use with the signal processor of Figure 1;

Figure 4 shows a block diagram of an embodiment of an amperage correction circuit for use with the output processor of Figure 3;

Figure 5 shows a functional block diagram of the signal processor of Figure 1; and a representative transfer frame realized by the output processor of the present invention.

Referring to Figure 1, there is shown a block diagram of a signal processor 20 according to the principles of the present invention. The signal processor 20 is arranged to receive analog input signals from a video signal source, and to supply the processed signals to a video monitor. The signal processor 20 will be described with reference to its use in conjunction with a forward looking infrared (FLIR) system. It will be understood, however, that other imaging sensors, such as synthetic aperture radar systems or standard video sensors, can also use the signal processor 20, and that the scope of the present invention is not limited to FLIR systems.

The signal processor 20 includes an input processor 21 which has inputs adapted to receive analog input signals from the FLIR sensor. The input processor 21 performs functions of automatic equalization of the reaction power and the DC reset, and converts analog signals into digital signals compatible with a digital scan converter 22 coupled to its output.

The digital scan converter 22 is arranged to demultiplex the applied signals and convert them into signals compatible with the video monitor. The scan converter 22 converts image data from a vertical detector array, which is swept horizontally, into data compatible with standard TV format, which is a horizontal arrangement, which is swung vertically. Thus, the scan converter 22 performs an orthogonal rotation of the image data timing and thus operates to reformat or resize the image scene data.

The scan converter 22 has an output coupled to an output processor 23. The output processor 23 is used to process the resized data in a manner that allows its software-controlled digitized image enhancement. In addition, the output editor 23 converts these amplified, resized signals into analog video output signals that are compatible with the video monitor.

A timing circuit 24 is used to control clocking of signals by the signal processor 20 and synchronizing the throughput of data from the FLIR signal source to the video monitor. A computer processor, such as a microprocessor 25 or the like, is coupled to the components of the signal processor 20 to control its data processing functions. The microprocessor 25 controls the processing of the analog input data to realize the strength equalizing function in the input processor 21, and controls the calculation of algorithms that generate the histogram and lookup table transfer function in the output processor 23. A more detailed understanding of the function of the microprocessor 25 will be obtained with reference to the detailed figures to be discussed below.

Referring to Figure 2, a detailed block diagram of a first embodiment of the input processor 21 is shown. This portion of the signal processor 20 includes an adder circuit 31, which receives as inputs the analog input signals from the FLIR signal source, as well as analog signals representative of the Auto Reactivation Equalization (ARE) correction constants and DC Reset (DCR) correction factors. The output of the adder circuit 31 is processed by a first analog-to-digital converter 32 and then supplied to the scan converter 22.

Concepts of automatic equalization of the reaction power and direct current reset are generally known in the art of signal processing. As an example of a circuit for automatic control of the reactive power, reference is made to US patent 4,345,148 entitled "Automatic responsivity control for a CCD imager". Accordingly, a detailed discussion of these concepts can be omitted.

The automatic reactive power equalization (ARE) and direct current reset (DCR) factors are generated by the following circuit.

A reference terminal voltage is generated by a DCR reference terminal circuit 33, which is coupled to the output of the digital-to-analog converter 32. The DCR reference terminal circuit is coupled to an up / down counter 34, the output of which is adapted to DC reset factors with increase or decrease steps. The microprocessor 25 is coupled to a RAM memory 35, a non-volatile memory 39, and automatic response power equalization and DC reset register circuits 36, respectively. 37. The DC reset circuit 37 is coupled through a first digital-to-analog converter 38 to the adder circuit 31, while the automatic response power equalization circuit 36 is coupled through a multiplier digital-to-analog converter 39 to the adder circuit 31.

The scan converter 22 of Figure 1 is not shown in detail in any figure. Digital scan converters are well known in the art, and the construction of this component of the signal processor 20 will not be discussed in detail herein. However, a representative sample of a scan converter, which could be adapted for use in the present invention, is described in U.S. Pat. No. 3,947,826 entitled "Scan Converter".

The interpolation section of the scan converter 22 includes an algorithm realized in hardware that converts, for example, FLIR scan line format (160 lines per whole picture) into TV video scan line format (240 lines per picture). The special realization employed in the present invention involves mapping four consecutive IR scan lines to six TV scan lines in a predetermined combinatorial manner.

The special algorithm maps four IR scan lines (A, B, C and D) to six TV scan lines (A, 1 / 2A + 1 / 2B, B, C, 1 / 2C + 1 / 2D, D).

Referring to Figure 3, there is shown a block diagram of an embodiment of an output processor 23 for use with the signal processor 20 of Figure 1. The output processor 23 includes a histogram generating circuit 41 including a window circuit 45, a gate circuit 42, a histogram circuit 43 and a step-by-step counter 44.

The histogram generating circuit 41 is arranged to process digitized output signals from the scan converter 22 and generate a histogram from the number of occurrences of signals at each infrared detector intensity level during each image time. The microprocessor 25 is coupled to the histogram generating circuit 41 to provide access to the histogram data.

Histogram equalization is generally well known to the signal processing technique and thus will not be discussed in detail here. Representative histogram equalization methods known in the art are described in U.S. Patent No. 3,979,555 entitled "Histogram Equalization System for Display Improvement", and U.S. Patent No. 3,983,320 entitled "Raster Display Histogram Equalization".

The microprocessor 25 uses the histogram data to generate a look-up table 46, which is physically stored in a RAM. The histogram data is used to convert the digitized, resized, unimproved signals from the scan converter 22 into improved image data under the control of the microprocessor 25. The look-up table 46 contains data representing the microprocessor 25 enable various image enhancement functions including auto volume or level correction, auto gain control, polarity reversal, and gamma correction.

The output processor 23 also includes a digital-to-analog converter 47, which accepts inputs from look-up table 46. The output of the digital-to-analog converter 47 contains video signals compatible with the intensity levels of the monitor. The output of the digital-to-analog converter is coupled via an aperture correction circuit 49 to an output amplifier 50, the output of which is coupled to the video monitor.

Figure 4 shows an embodiment of the aperture correction circuit 49 for use in the output processor 23. The aperture correction circuit 49 is arranged to enhance the frequency response of the system and thus improve the modulation transfer function (MTF) of the system.

The circuit 49 uses a time delay circuit 52 and a variable resistance network 53, which supplies signals to an adder circuit 54. This circuit functions as a cosine filter. The operation of combining time delayed signals with currently processed signals amplifies the gain above certain frequencies and improves the system's frequency response.

The operation of the signal processor 20 according to the invention will be explained with reference to Figure 5, which shows a functional block diagram of the signal processor 20. The system will be described with reference to its use in the FLIR scanning system. The FLIR sensor contains a number of detectors, 160, for the purpose of this discussion.

The outputs of the 160 channels are multiplexed in the FLIR sensor prior to their application in the signal processor 20.

The multiplexed FLIR input signals are applied to the adder circuit 31. The output of the adder circuit 31 is processed by the automatic reaction power equalizing circuit 36. Gain factors are read from the non-volatile memory 39 in the RAM memory 35. The stored values are then multiplied by the gain factors and added to the FLIR analog signals in the adder circuit 31. In addition, DC reset factors are determined and added to the FLIR signals in the adder circuit 31.

The output of the adder circuit 31 contains DC current reset and normalized signals. These signals are then converted into digital data in the analog-to-digital converter 32 and stored in the scan converter 23. The scan converter operates in a manner that resizes the digital data and interpolates it to number of scan lines to be set to a number compatible with the video monitor. The output of the scan converter 22 is then applied to the output processor 23.

The output processor 23 uses the histogram generating circuit 43 and the microprocessor 25 to generate a look-up table 46 in the RAM, which includes a transfer function which improves the processing digital video image. The lookup table includes multiplying factors which are applied to the digital video data to realize automatic gain control, automatic volume correction, polarity reversal and gamma correction. The signals emerging from the look-up table 46 include enhanced digital video signals which are converted to analog video signals in the digital to analog converters 47 and applied to the aperture correction circuit 49. The aperture correction circuit 49 makes the signal gain at predetermined frequencies stronger. The aperture correction compensates for the "roll-off" of the modulation transfer function caused by less than perfect optical elements, deteriorated resolution of the video monitor and detector sampling in the FLIR sensor.

Presented below is a general description of a signal processor constructed in accordance with the principles of the present invention and used as part of a forward-looking infrared (FLIR) system. The signal processor will not be described by referring to any specific figure. The signal processor processes eight parallel channels containing 20 multiplexed signals to realize image resizing and video editing to convert 160 parallel infrared detector outputs into standard 525 lines TV video output (480 lines of which are cut off).

The eight parallel multiplexed infrared video channel inputs contain 20 detectors per channel. The input signals from each of the 20 channels are DC-reset, response-corrected, and digitized to a 9-bit intensity level in eight input processor circuits. The digital infrared video signal is resized by an orthogonal translation and stored in the memory of the scan converter. The image is stored in TV coordinates containing 320 lines with 752 samples per line. The scan converter memory uses 64K RAM ICs and stores each image of the image in 36 ICs.

The stored image is read with four IR lines in parallel and interpolated to provide six TV lines on the video monitor.

The interpolated video signal is sampled in the histogram memory, which stores the frequency of occurrence of each of the 512 (9 bit) intensity levels. The histogram is edited to provide automatic volume and strength translation for the video display. The volume and strength control functions are realized in the RAM lookup table, each of which is IR

intensity level translates into a video monitor intensity level. Display gamma and image inversion correction factors are also stored in the lookup table. The look-up table output is converted to an analog signal, aperture corrected by the cosine filter technique, and then fed to the video monitor for viewing.

The main functions affecting the video output are Auto Reaction Equalization (ARE), DC Reset or Restore (DCR), Interpolation, Automatic Volume Correction (ALC), Automatic Strength Correction (AGC), Gamma Correction and Aperture Gain. The auto-response equalization and DC recovery functions are accomplished in parallel to each of the eight multiplexed infrared video channels. The RAM is filled with ARE values from a non-volatile memory when the system is turned on. DC recovery is performed continuously to provide automatic condensation for the thermal environment of each detector in the infrared sensor.

Automatic Reactor Equalization Values are generated and updated (updated) using the calibration procedure. Both the DC recovery and reaction power equalization calibration are based on the detector array, which scans an even thermal reference source during the inactive scan time (retrace time). The residence time at this source is relatively short (about 300 microseconds) but provides enough samples (32) to correct for any DC voltage drop and thermal change in the scene during the time period that an image field is scanned.

In the normal operating mode, each analog infrared detector input signal to the signal processor is compensated by adding a DC recovery term and multiplying by a reactivity correction term to provide a voltage to the analog-to-digital converter. The equation defining this relationship is: eQ = (2.5 + e ^ - DCR) / (1 + ARE).

The 2.5 volt constant centers the output signal, which is applied to the analog-to-digital converter.

The equation e ± = GK T + L, where G = the channel gain factor, K = the reagent power factor, T = the temperature difference seen by a detector, and L = a level offset introduced by the electronic components, implies that if ARE are set equal to Kl, then each detector output is normalized. These ARE values are calculated in the initial calibration procedure and stored in a non-volatile memory. Other relevant equations include: ARE = K - 1, DCR = V- + GK T + L. - V '(1 + ARE), and 0 s. DCR 'and = V _ + G (t's + T,).

0 DCR s. 1 Λ

The DCR values are updated with each scanning of the image plane ("field"). When the detector array is swept over the reference thermal source, the analog-to-digital converter output is compared to 1.5 volts, which corresponds to an expected reference source temperature of 20 ° C above the ambient temperature and a sensitivity of 0.075 V / ° C. Since each detector is multiplexed to the input processor, the corresponding DCR correction term is read from memory and added to the detector voltage. The DCR term is also used to pre-set the up / down counter. The voltage comparator gauges the counter either "up" or "down" depending on the input signal to the analog-to-digital converter.

If the FLIR detector input plus the old DCR correction term is low, the counter is tilted to count "up" until the input plus DCR correction equals (normalized) 1.5 volts. If the FLIR detector input plus the old term is high, the counter is tilted to count "down" until the input has normalized. By providing several samples of the input to the counter, the noise is averaged to + 1 least significant bit (LSB) of the DCR term. The DCR correction is ± 2 volts with 8 bit quantization, resulting in a DCR correction to ±. 16 millivolts or ± 0.3 percent of the dynamic input range from the analog-to-digital converter. The new DCR correction is stored in memory and used to correct the next active image plane scan of the FLIR.

The initial calibration of the ARE values is performed during the calibration mode. In this mode, the scanning FLIR array looks at a target plate of uniform temperature. Thus, the FLIR senses an even source temperature during the active scan time of the image plane (field) and senses the thermal reference source during the inactive (flyback) portion of the scan of the image plane. When all detectors are looking at the same temperature difference between the active field of view and the thermal reference, the only differences in the output signal are caused by differences in response power between the detectors.

Initially, the ARE values are set to zero, and the OCR offsets required for a steady output are generated. The mean calibration scene temperature is then calculated from eight successive histograms. This average scene temperature is used as the comparator reference voltage for determining ARE values. This self-adjusting comparator reference allows calibration of the detector array with different calibration scene inputs, such as air, ground or test image and the like. The ARE values are generated in a manner similar to the DCR terms by using the comparator to gauge the up / down counter to correct the ARE values. The generation of ARE and DCR values is an iteration process. The new ARE values shift the DCR values, which in turn set the ARE values. This process is convergent, and after several frames ("fields"), the ARE and DCR terms are stable.

To further reduce the noise sensitivity of the ARE terms, the actually stored ARE values represent the average of 32 consecutive ARE corrections. Since the DCR and ARE calibration is a closed loop system around the analog-to-digital converter, any operation differences from channel to channel are also compensated automatically by providing the same digital output for each detector by the same delta temperature -Entrance. The ARE compensation provides a range of a 1 ± 0.5 multiplier with 3 bit quantization for +0.21 percent accuracy at the analog-to-digital converter input.

Interpolation of the IR scan lines to TV lines is required to map 320 IR lines to a 525 line TV picture, 480 of which are used. The interpolation algorithm maps four consecutive IR scan lines on sex TV lines. The interpolation is performed on an IR / TV image field basis to eliminate collapse of the image that would result if the entire IR / TV frame (two image fields) were interpolated. This single field interpolation, which eliminates image collapse caused by image or sensor motion, does introduce some deterioration in the vertical dimension. However, in the vicinity of the dynamic scene when flying at low altitudes, for example, the resulting image quality is better with this form of field interpolation.

Automatic strength and volume adjustment is obtained by collecting a histogram of the scene intensities, determining both the minimum and maximum intensity from a 7.5 by 10 degree window in the lower center of the field of view, or from the total scene. The field of view is selected through the use of gate circuits.

The strength and volume are then adjusted to display only the video intensities representing terrain features.

The software algorithm realized in the microprocessor acts as a low-pass filter with respect to the maxima and minima from frame to frame using the following relationship: M. = K (IM.,) + M., 1 ï-1 ï-1 where I = the maximum or minimum detected, M = the maximum or minimum usage for subsequent calculation, M = maximum or minimum from the previous grid, and K = a weighting factor.

Using the maximum and minimum values after filtering, the strength and volume values can be calculated from the following relations: G = 2N / (Max + Min) L = (Max + Min) / 2 where G = the gain, L = the volume, and N = the number of bits for a full dynamic range of the image

The output transformation can be calculated from the following relations: X (I) = G (IL) + (2N / 2 - 1) X (I) <0, X (I) = 0 X (I)> 2N - 1, X (I) = 2N - 1 where X (I) = the output value for an input I,

M

I = the input for 0 to 2 - 1, and M = the number of input bits.

The digital video from the interpolator is ported to the histogram memory. Either the total field of view or the small window is sampled on alternative TV fields. Each intensity level increases the count-ling stored in the memory for the special intensity. At the end of one IR image field time, the histogram is read from the microprocessor:> m allow calculation of the strength and volume settings.

The microprocessor also performs a low-pass filter operation to integrate various data frames. Then the strength and volume adjustments are calculated from the filtered data.

The strength and volume transfer function is provided in the look-up table, which is populated in RAM by the microprocessor. The lookup table is used to convert every 9 bit digital FLIR intensity into an 8 bit image video intensity. The required gamma correction factors for the image and image polarity factors are also stored in the look-up table. Aperture gain is obtained after digital-to-analog conversion of the video signals to compensate for MTF "roll-off" caused by the optical elements, image resolving power and detector sampling. The aperture correction provides a gain of 6 dB at the Nyquist sampling frequency (0.54 cycle / mrad, T + 0.66 microseconds).

Thus, a new and useful signal processor has been described herein which can be used to provide an electronically enhanced video image maker. Software-driven digital image enhancement measures of the present invention can be realized using a relatively small amount of standard integrated circuits. The system provides custom calibration and the calibration factors are stored indefinitely for use by the system. The temperature of the reference temperature source used to calibrate the system does not need to be known for the system to function properly. The DC levels of all detectors in the system are automatically reset to the DC reference temperature determined by the reference temperature source. No manual adjustments need to be made during calibration or operation.

Image enhancement functions are provided in a look-up table instead of having to be calculated by analog circuits as in conventional signal processors. A wide dynamic range is obtained using digital image processing circuits and techniques. An increased system frequency response is obtained by means of the aperture correction circuit. System flexibility and growth is possible and can be achieved through changes in software programs.

It will be understood that the above-described embodiment is merely illustrative of one of many specific embodiments illustrating applications of the principles upon which the present invention is based. It is clear that numerous and varied other arrangements can be designed by one skilled in the art without departing from the scope of the present invention.

Claims (8)

A signal processor (processor) for use with an image sensor system containing a plurality of detectors that are swept across an image scene during a first portion of a scan cycle and swept over a reference temperature source during a second portion of the scan cycle, which signal processor a video monitor provides video output signals representative of the image scene, comprising: an input processor coupled to the image sensor system for processing analog signals derived from each of the plurality of detectors to equalize the gain of the analog signals during each other the first portion of the scan cycle based on stored gain correction signals derived from a predetermined sensor response power calibration procedure, for processing the analog signals to restore the DC levels of signals derived from each of these detectors to DC values related to the reference temperature source during the second portion of the scan cycle, and to process the equalized and DC recovered signals to provide digitized first output signals from the input processor means; a scan converter means coupled to the input processor means for storing the digitized first output signals and processing the stored digitized signals to provide digitized second output signals compatible with the video monitor, and an output processor means coupled with the scan converter means for processing second digitized output signals in a manner that allows software-controlled digitized image enhancement thereof, and for converting the improved second digitized output signals into analog video outputs compatible with the video monitor. Signal processor according to claim 1, wherein the input processor means comprises: an analog-to-digital converter means for converting applied analog signals into the digitized first output signals, - an adder for combining the analog signals, the DC recovery signals and the strength correction signals, wherein the combined signals are applied to the analog-to-digital converter; and a computer processor coupled to the analog-to-digital converter means and the adder for calculating the DC level correction signals and for controlling the combination of the analog signals, strength correction signals and DC level correction signals in a predetermined manner to obtain signals digitized by the analog-to-digital converter means. The signal processor of claim 2, wherein the computer processor means includes: a non-volatile memory for storing strength correction constants derived from the calibration procedure; a first memory means coupled to the adder for storing the DC recovery signals prior to their supply to the adder; a second memory means coupled to the adder for storing the strength correction signals before supplying them to the adder; a computer processor coupled to the non-volatile memory, the first and second memory devices, and the analog-to-digital converter for calculating the DC recovery signals and storing them in the first memory device, for filling the second memory device with strength correction signals from the non-volatile memory, and for controlling the processing of the analog signals, and the strength correction signals to combine the signals in the analog-to-digital converter. The signal processor of claim 3, wherein the first memory means includes: a clamp voltage reference circuit coupled to the analog-to-digital converter for processing the derived output signals to provide fixed voltage reference signals for calculating the DC recovery signals; and a counting circuit for processing the voltage reference signals to provide increasing and decreasing signals to the first memory means, which sets and normalizes the DC recovery signals relative to the fixed voltage reference during each scan cycle. The signal processor of claim 4, wherein the first and second memory means further include: first and second random access memories; first and second digital-to-analog converters switched between the first and second random access memories for converting digital signals stored in these memories into analog signals which travel with the analog-to-digital converter. Signal processor according to any one of the preceding claims, characterized in that the scan converter comprises: a scan converter for storing the digitized first output signals; and an interpolator coupled to the scan converter to convert the digitized first outputs into the digitized second outputs compatible with the video monitor. Signal processor according to claim 6, characterized in that the output processor comprises: a search-on-table generating means for calculating and storing a look-up table containing image correction correction signals; a digital-to-analog converter means coupled to the look-up table generator for converting signals obtained from the scan converter into analog video outputs compatible with the video monitor; an aperture correction means coupled to the digital-to-analog converter for processing the enhanced signals derived from the look-up table generator to improve the modulation transfer function of the system; and a computer processor coupled to the look-up table generating means for calculating the signals containing this look-up table. The signal processor of claim 7, wherein the look-up table generating means comprises: a histogram generating means for generating a histogram of the number of occurrences of the first output signals at each intensity level associated with the sensor; a look-up table memory for storing the image enhancement signals; wherein the computer processor means the image correction correction signals calculated using the histogram and storing the calculated signals in the look-up table memory.