NL8503461A - METHOD FOR GENERATING LINES. - Google Patents

Abstract

A method of generating a line part of thickness D on a homoge­nenous raster, the raster points of which are arranged in a number of parallel lines, and in which the bit representation of the line part (250) is stored in a word-oriented bit-map memory in the form of a large number of image points or pixels, by- determination of the envelope of the line part and the imaging of said envelope on the raster points,- determination of the length of the section through the line part for the successive raster lines, and- placing of the bit representation of said lengths in the bit-map memory at corresponding locations, the direction of the determined lengths corresponding to the word direction of the bit-map memory.

Description

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Inventor: C, P. Schuerman

Océ-Nederland B.V., in Venlo

Method for generating parts

The invention relates to a method for generating line segments according to the preamble of claim 1.

Such a method can be applied in an electronic printing system, in which data about the line segment to be formed can be entered using, for example, a connected workstation and via a front-end system containing a word-oriented bit-map memory at a raster output. scanner can be fed.

Such raster output scanners are arranged to print a full page line by line using serially presented data.

A typical representative of this type of raster output scanners is a laser printer, in which a light beam is modulated image-wise and this modulated light beam is bent in a line by means of a polygon mirror over a photosensitive surface, such as a zinc oxide ambush which is applied on a flexible belt. . In a known manner, a latent image can be written on this with the aid of the modulated light beam. This latent image can be developed and transferred in a known manner to a receiving material such as a sheet of paper.

The workstation can also be used to enter text that must also be printed on a page. In the front-end, this (encoded) input text is expanded with font data stored in a memory, and the expanded text is also stored in the 25-bit map memory. In addition, graphic data obtained from a scanner, for example, an original can be supplied to the workstation and bit-map memory.

The workstation is equipped with a display that allows the page to be printed to be assembled. The layout of the page can be varied as desired via the workstation. With special commands that are entered via the workstation, the front-end can create all kinds of curves such as straight segments, circles or arcs, 8503431 v.

t »-2- r · etc. and place them in the bitmap memory.

The increasing resolution of raster output scanners makes them increasingly suitable for printing graphic information. The graphic information (line segments, etc.) must be displayed on the grid of this 5-grid output scanner. The mapping process consists of determining the collection of grid points to activate. The activated grid points are thus written in a word-oriented bit-map memory. Due to the large number of grid points to be generated, rapid processing is necessary.

Therefore, the object of the invention is to provide a line generation method which is in accordance with the high printing speed at a high resolution of the printer.

This object is achieved according to the invention with a method according to the preamble by the characterizing part of claim 1.

This achieves that line segment generations can be realized with simple and thus fast algorithms and that the number of required memory access cycles is minimal.

These and other advantages will be made clear from the description below and with the aid of figures, of which:

Fig. 1 is a schematic representation of a front-end system,

Fig. 2 shows the processes that can be performed by the raster image processor, FIG. 3 is a schematic representation of a raster image processor,

Fig. 4 is a schematic representation of a VME bus interface,

Fig. 5 is a schematic representation of a laser scan module interface,

Fig. 6 is a schematic representation of a 16-bit processor system of the raster image processor, FIG. 7 is a schematic representation of a raster image bus interface,

Fig. 8 is a schematic representation of a VME master interface of the VME bus interface,

Fig. 9 represents the placement of a character in the bitmap memory, FIG. 10 shows the results of a number of possible operations in the bit-35 map memory, and

Fig. 11 is a schematic representation of a raster image memory.

Fig. 12 represents a segment with round ends, 8503461 -3-

Fig. 13 represents a line through points P1 and P2,

Fig. 14 is a detail sketch illustrating the determination of the intersection of the line with a circle around the starting point of that line, FIG. 15 is a flow diagram of a method for determining the intersection point S *,

Fig. 16 represents a line segment depicted on grid points,

Fig. 17 a, b and c represent a flow diagram of a method for line generation of a segment with round ends, and FIG. 18 represents a straight-ended line segment.

Fig. 1 is a schematic representation of a front-end system. Herein a front-end controller 10 (FEC) is connected to an operating console 19 and also to the operating system of a printer 20. Printer 20 is a raster output scanner, in which a light beam 15 is modulated imagewise and linewise over the surface of a photosensitive element is deflected. The photosensitive element is moved perpendicular to the deflection direction of the light beam in order to write an overall image in raster form. An example of a raster output scanner is a laser printer, in which a modulated laser beam is advanced over the surface of a charged photoconductor using a rotating multi-surface mirror. The photoconductor is hereby image-wise exposed, and the resulting charge image can be developed in known manner with toner, then transferred to a receiving sheet and heat-set. The front-end controller 10 includes a 16-bit microprocessor system with a Motorola 68000 microprocessor and acts in conjunction with local ROM and part of a random access memory 12 (RAM) as the operating system for the front-end. The bit patterns of a number of fonts are stored in a font reading memory 13. The front-end 30 can be connected to a disk memory, workstation, computer and / or cluster controller via a 1/0 processor 11, which also includes a 16-bit microprocessor system with a Motorola 68000 microprocessor. The FEC 10, 1/0 processor 11, RAM 12 and font memory 13 are interconnected via a standard VME bus 14. The font-35 memory 13 can also be run as RAM or be part of SS Ö 3 4 S tr * * -4- RAM12. The bit patterns of the fonts are then loaded into this RAM from a disk memory or floppy disk memory.

A raster image processor 15 (RIP) is also connected to the VME bus 14. In addition, the raster image processor 15 is connected via a raster 5 image bus 17 (RI bus) to a page-large bit-turnip memory 16, also called raster image memory (RIM). The RIP 15 serves to image-fill the bit-map memory 16 (RIM) with characters retrieved from the font memory 13 and stored in the correct location in the bit-map memory 16. In addition, the RIP 15 10 can retrieve graphic information from memory 12 and also store it at the desired locations in the bitmap memory 16. If the bit-map memory 16 is filled, it can be read again via the RIP 15, the read data being fed as a serial pixel-bit stream via line 18 to the modulator of the laser printer.

15 The image written on the photoconductor is made up of pixels of 0.05 x 0.05 mm, so that approximately 4000 x 6000 pixels are required to print an A4 size black and white image. As a result, bitmap memory 16 is approximately 24 Megabit or 3 Megabyte in size. When reading the bit-map memory 16, the pixel-bit-20 rate to the modulator of the laser printer via line 18 is approximately 25

Megapixels / sec., So that a page of A4 size in about 1 sec. can be printed.

All data about a page to be printed is stored in the RAM 12 via the 1/0 processor 11 from, for example, a workstation and under the control 25 of the FEC 10.

Various options are available for this.

For example, assuming an A4 page to be printed in "portrait mode", approximately 4000 partial tables are created, corresponding to the approximately 4000 scan lines required to write a page. Each partial table stores letter codes of those characters or graphic characters. that have their starting point on a particular scan line Each letter code also contains information about the X position the character occupies on the scan line, information about the font type as well as information about the height and width of a particular character. letter code data about a base address in the font memory 13, where the bit representation of this character is stored in 16-bit words The set of lists 8503 461 -5- * '* f thus formed is called the list of primitives .

If the data about a page to be printed is thus stored in the HAM 12, the bitmap memory 16 can be started for this purpose. To that end, the letter codes from the RAM 12 are retrieved one by 5 by the RIP 15, and with the corresponding bit representation expanded from the font memory 13 and stored in the correct X and Y position in the bit map memory 16. Similarly, all characters are finished one by one until the bitmap memory 16 is completely filled with the pixel representation of the page to be printed.

It is not necessary to form these partial lists. The data about a page to be printed can also be stored in RAM 12 in any order. When filling the bitmap memory 16, the RAM 12 in which the primitives are arranged in any order is read sequentially, expanded and placed at the corresponding locations in the bitmap memory 16. According to yet another possibility, all characters appearing on a page are stored only once and provided with information about the different positions each character occupies on the page.

For example, information about a common character, such as the letter e, is only stored once in RAM12 and all positions that this letter occupies on the page are added in a separate table.

Usually, the graphic characters stored in the RAM12 or 25 font memory 13 are first put into the bit-map memory 16 and only then the characters.

The Raster Image Processor

In FIG. 2 shows the processes that can be performed by the RIP 15. After system startup (3tap 24), the 30 RIP 15 is initialized (step 25) (INIT command) by a system reset or an INIT command from the front-end controller 10, after which the "self-test" process (step 26 This "self test" includes testing various RIP functions and bitmap memory (RIM) functions. The RIP 15 should not have access to the VME bus 14 during the 35 self test procedure, because the FEC 10 has the VME bus 14 required for testing the RAM 12 and font memory 13 · When the RIP 15 has successfully executed the "self-test" program, an interrupt 35Ö34S1 •% -6 signal is passed to the FEC 10, and the RIP 15 goes on hold (step 27). When the self-test program has detected an error, the RIP 15 also goes on hold (position 27), but no interrupt is generated to the FEC 10. In this way, the front-end 5 controller 10 that an error has been detected in the RIP 15 "self test." An error is also detected by the lighting of an LED signaled to the operator.

On a "RIP diagnosis" command from the FEC 10 to the RIP 15 »the RIP diagnosis process starts. The RIP 15 performs a number of internal 10 tests as well as some tests on the RIM 16. The results of these tests are stored in the RAM 12 and can be passed on to and displayed on the control console 19. The RIP diagnosis process test also the VME interfaces. The RIP diagnosis process is more extensive, while the self-test process performs a more functional hardware test. After finishing the RIP diagnosis process, the RIP 15 stores status information in RAM 12, generates an interrupt to FEC 10 and releases VME bus 14.

After the RIP 15 receives a "fill bitmap" command from the FEC 10, the RIP 15 checks the data transport on the VME bus 14. The RIP 15 20 thus accesses the RAM 12, which contains the primitives of the page being printed must be.

The RIP 15 expands the primitives list using the pixel representations of the fonts and stores it in the bit-map memory 16 (RIM). The RIP 15 has access to the RIM 16 via the RI-25 bus 17. The RIM 16 also includes modification logic, which supports the RIP 15 in performing various arithmetic operations on data for the bit-map memory 16, such as AND , 0R and INVERT operations. After filling the bit map (step 28), the RIP 15 stores status information in the RAM 12, generates an interrupt to the FEC 10 and releases the VME bus 14.

The FEC 10 then generates a "read bitmap" command and the RIP 15 will wait for a page synchronization signal from the laser printer via a control interface. After this page synchronization, the RIP 15 starts reading the RIM 16 (step 35-29) and generates a serial pixel bit stream which is supplied via a video interface to the modulator of the laser printer. After finishing the bitmap reading process (step 29), the RIP 15 850 3 46 1 "t * -7- again stores status data in the RAM 12, generates an interrupt to the FEC 10 and then returns the VME bus 14 free.

The RIP 15 (Fig. 3) is built around an internal bus system, the raster image processor bus 46 (RIP bus), which is a synchronous bus 5 and arranged to transport only 16-bit words. The RIP bus 46 contains data lines 47, address and control lines 48 and connection lines 49 · The RIP bus is connected to the VME bus 14 via a VME bus interface 41 and via a RI bus interface 45 to the RI -bus 17.

This RI bus 17 includes data and address lines 58, a busy-10 line 57, an RI bus address-available line 56, a clock line 54, and modification lines. In addition, the RIP bus 46 is connected to a laser scan module interface 44 (LSM interface) and the actual Central Processing Unit 43 (CPU) of the RIP 15. The laser scan module LSM interface 44 is connected to lines originating from the printer, such as 15 a "start or scan *" line 52 (SOS), over which a synchronization signal is applied to indicate the beginning of a line to be printed, a burst line 53, over which a signal corresponding to the desired pixel frequency is applied and a video line 18, over which the serial pixel bit stream is applied to the modulator of the laser printer when the bitmap memory 16 is read. The address control lines 48 and the condition lines 49 are also connected to a page synchronization interface 42. About line 50. a "page-available" signal (PAV) is applied to the printer controller indicating that a page in the bit-map 25 memory 16 has been completely formatted and that the RIP 15 has a "start-of-page" (SOP ) the reading of the bit-map memory 16 can commence via line 51, originating from the control device of the printer.

VME bus interface 30 In Fig. 4, the VME bus interface 41 is schematically illustrated. A master interface 100, a slave interface 101 and an interruptor 102 are connected to the VME bus 14. The data lines 47 of the RIP bus 46 are connected to the master interface 100. The address control lines 48, as well as the condition lines 49 of the RIP bus 35 46 are connected to the master interface 100, the slave interface 101 and the interruptor 102. The VME bus interface 41 has the task of terminating the RIP 15 asynchronous VME bus screens 14. The VME- 8503461-8 master interface 100 (VME-MI) includes an internal operating system that controls the buffers and registers present and allows access cycles on the VME bus 14 are performed. Programmable logic is applied in the controller. The slave-5 interface 101 and the interruptor 102 are also provided with programmable logic for controlling.

The VME-MI 100 (Fig. 8) also includes data transfer functions such as database master (DTB master) and database requestor (DTB requestor). In order to achieve the desired speed in the data transport, some additional functions have been added in this 10 VME-MI 100. '

The first function is an address up / down counter, formed by an address-high counter 132 and address-low counter 133 * When loading the RIM 16 with the bit representations of the different characters or graphic characters, each with consecutive addresses stored in font memory 13 or RAM 12, counters 132 and 133 for each character are preset with the base address of that character in, for example, RAM 12. Via buffer 134 and VME address bus 141 of VME bus 14 this base address is supplied to the RAM 12, and the first 16-bit word on that particular memory location is supplied through the VME data bus 142 of the VME bus 14 to a bi-directional buffer 135 and then in the correct location in the RIM 16 installed. The next address for the RAM 12 is generated by incrementing the counter 133 by one and the second 16-bit word is supplied to the RIM 16 through the VME-MI 100. Correspondingly, all addresses associated with a particular character are generated until the character is completely written in the RIM 16.

In this way it is achieved that the CPU 43 only has to generate a base address once per character, so that during loading other functions can be performed, for instance pixel operations, RIM address determination, etc.

After a character is completed, a new base address for a subsequent character is supplied to counters 132 and 133 and the above-described cycle is repeated.

The second function, the mirror function, is performed with a mirror circuit 136, which is constructed with programmable logic, such as FPLA1s or PALs, and which can be used when characters 1800 are to be rotated in the RIM 16. The mirror circuitry 8503461 * 9 changes 136 from a 16-bit word bit-0 with bit-15, bit-1 with bit-14, bit-2 with bit-13, etc.

The CPU 43 now does not generate the base address, but calculates from data about length and width and the base address of a character the 5 most common address for that particular character in RAM 12. This highest address is loaded in counters 132 and 133 while the counters are also converted to down-counters by VME-MI controller 130. After each memory access of RAM 12, the contents of the counter 133 are decreased by one and the 16-bit words from RAM 12 are mirrored in mirror circuit 136 and placed in the RIM 16 via the data-in register 137. These cycles continue until the character's original base address is reached.

In the VME-MI 100, a data-out register 138 is also connected to the RIP bus 46 via data lines 47, so as to feed data to, for example, the FEC 15 or to RAM 12.

The VME-MI controller 130 is connected to the RIP bus 46 via control lines 48 and condition lines 49 and, in addition, via a buffer 131 of the address, data, and control lines 139 and bus arbitration lines 140 of the VME bus 14.

The CPU 43 can call various states in the VME-MI 100, such as "release bus", "multiple access", "single access" and "change". Before the VME-MI 100 can transition to the single- or multiple-access state, the following data must first be specified: read or write, normal or mirrored, the desired address and the data to be processed. These specifications can only be changed during the "release-bus" state and during the "change" state. However, the data to be processed can always be changed. This is also indicated by a "CHANGE ACKNOWLEDGE" line. The register containing the read data from VME bus 14 can be read whenever a "REGISTER FULL" line is active.

After calling a "release bus" state, the VME-MI 100 will release the VME bus 14. This means that the VME bus drivers are disabled and a BBSY signal from the VME bus is disabled. The release of the VME bus 14 can only take place when the last access cycle has been completely completed. A "CHANGE ACKN0WLEDGE" signal indicates that the "release bus" state has entered. In this state of the interface, access to the 8503461 »4 -10 VME bus 14 cannot take place. After a "change" application, the VME-MI 100 is instructed to take possession of VME bus 14, if not already. This is accomplished with the bus arbitration lines 140. The "CHANGE ACKNOWLEDGE" line indicates that the "change" state has been reached. An access to the VME bus 14 can then take place. The contents of the address and data registers can also be changed during the "change" situation. Change provides an option to temporarily stop accesses on the VME bus without releasing the VME bus. A single access on the VME bus can be started by calling a "single cycle" state. When the previous state was a "release bus" state, the VME bus is only taken over via a corresponding active signal from the arbitration logic. After this, a word access can only be performed on the VME bus.

15 A read / write indicator decides whether to perform a read or write cycle.

A read cycle means that data from the VME bus 14 is clocked into the data-in register 137 via the mirror circuit 136, the latter of which can be activated using a normal / mirrored indicator. When data is clocked into the data-in register 137, a REGISTER-FULL flag is set to signal to CPU 43 that the data transfer has ended and that the data has entered the said register. The REGISTER-FULL flag is set when the data in the data-in register 137 is read and after this access the content of the address counter is increased by one. In the case of an enabled mirroring function, the content of the address counter is decreased by one. When the REGISTER-FULL flag is still activated and data is being read from the VME bus, the normal VME cycle is extended until the data-in register 137 is fully read and new data is entered in the data-in register 137 read in.

A write cycle is basically the same as a read cycle. The only difference is the direction of the data flow. In a write cycle, the data contained in the data-out register 138 is transported to the VME bus 14. The mirror circuit 136 does not change the written data. The data-in register 137 must already have been read in order to clear the REGISTER-FULL flag.

The "multiple access" state is very similar to the 85 0 3 4 6 1

* V

-11- "single access" state. A "single-access" is intended for reading and writing commands from, and status information to, the FEC. A "multiple access" is mainly intended for reading graphic and font data, whereby the VME-MI 100 automatically starts a next access. The new address is generated by the address counter. The only action to be taken here is to read the data-in register 137.

The various states described above are selected with the VME-MODE lines which are connected to some 10 signal lines of the CPU 43. The read / write selector and the normal / mirrored selector are also connected to such signal lines. The CHANGE-ACKNOWLEDGE and VME-Register-Full signals come from the WAIT lines of the CPU 43. The VME address is stored in 24-bit counters 132 and 133 »the input and output data in 15 two 16-bit registers 137 and 138. "Address high" and "address low" of counters 132 and 133 and the data-out register 138 are loaded using register clock lines. The data-in register 137 can be read using a register enable line from the CPU 43-20 The LSM interface

In FIG. 5, the LSM interface 44 is further schematically shown.

When the RIM 16 is read out, the RIP 15 retrieves a 16-bit word from this memory and passes it via data lines 47 from the RIP bus 46 to register 111. The control block 110 gives a "load" over line 115 - signal to shift register 112 and the contents of register 111 are loaded parallel to the shift register 112. The laser printer delivers burst pulses at a frequency of about 24 MHz, which are applied over line 53 and through 1/0 buffer 113 to the shift register 112 and the control block 110. With these pulses, the content of the shift register 112 is serially extended and is fed via line I / O buffer 113 over line 18 to the modulator of the ROS.

The burst pulses are applied to a 16 counter in the control block 110, and when 15 pulses are counted or during the 16th count pulse, a now new word entered in register 111, 35 is passed parallel to shift register 112 and extended. Before the extend operation of this 16-bit word starts, the register 111 is loaded with a new 16-bit word. An "EMPTY" flag is set 8503 4Si -12-, J> »when data is put in shift register 112 and new data is allowed to be written in register 111. The "EMPTY" flag is connected to a "waiting line" of the CPU 43 of the RIP 15. In this way, an entire scan line is successively passed to the ROS. The control block 110 outputs condition signals to the CPU 43 over the conductor lines 49 of the RIP bus 46. After a scan line has been completed and before an SOS signal is supplied via line 52 from the ROS to the control block 110, the retrieval is of data from the RIM 16 stopped by the RIP 15 (wait condition). During this time, register 111 is cleared via line 114. On the SOS signal, the previously described cycle of filling register 111, passing to shift register 112, scrolling out, etc., is repeated for a next scan line. After loading a word in register 111, the "full" status is also passed via condition lines 49 to the CPU 43, where it waits to retrieve a new word until the contents of the register 111 have been loaded back into the shift register 112. Using a counter in the CPU 43, after a PAV signal, the number of SOS pulses is counted, and it can be used to determine when a page has been completely passed to the ROS.

20 The Central Processing Unit

In FIG. 6, the CPU 43 of the RIP 15 is further schematically shown. This CPU is built around a microprogrammable microprocessor, processor 74, type Am2911ö, and an associated address sequencer 70, type 2910A, both from Advanced Micro Devices.

On each clock cycle, the microinstruction to be executed is placed in the microinstruction register 72. This microinstruction comes from the micro-PROM 71 and is again addressed using the address sequencer 70. Each function in the processor 74 is controlled by part of the microinstruction 30 bits. These micro-instructions can be divided into bits for the address sequencer 70, the processor 74, the jump address control unit 79, the condition selector 75, the waiting selector 77 and the enable 78.

The order of execution of the micro-instructions stored in the micro-PROM 71 »is also controlled by the address sequencer 70. In addition to the possibility of sequential access to the addresses, conditional jump instructions can also be sent to any 8503 46 1 -13 - microinstruction is executed in the 4096 large micro word range of the micro-PROM 71. A LIFO stack provides a micro-subroutine return link and looping capabilities. The stack is nine steps deep. For each microinstruction, the address sequencer 570 provides a 12-bit address initiated from one of the four following sources: - the microprogram address register (PC), which usually indicates an address with an address increment of one, relative to the pending address. However, when a "wait" state is generated by wait selector 77, the PC is not incremented.

an external input, connected to lines 92, which receives its data from the jump address control unit 79.

- a nine-step LIFO stack, which is loaded with the contents of the micro program address register (PC) during a previous microinstruction.

a register / counter, which retains the data loaded from an external input during a previous microinstruction.

The processor 74 is a microprogrammable 16-bit microprocessor, type Am 29116, with an instruction set optimized for graphics applications. Specifically, the instruction set for processor 74 includes single and double operand, rotate-n-bits and rotate & merge.

The processor 74 receives its instructions for performing an operation from the microinstruction register 72 through bus 83 and an instruction modification circuit 73.

The instruction entry is also used as a data entry for "immediate" statements. When the "instruction enable" (IEH) input of the processor 74 is activated through line 9¾, the results of the executed instruction are held in the accumulator and the status register in the processor 74. When an "output enable" (0E) is activated via line 95, the data lines of the CPU 43 are switched as outputs and contain the content of the ALU of processor 74. Conversely, when the "output enable" via line 95 becomes inactive The data bus of the CPU 43 functions as a 16-bit input, 35 and data present on the RIP bus can be fed via data lines 47 to the processor 74. This data can then be kept in an internal register. The data bus of the processor 74 is directly connected to the data lines 47 of the RIP bus 8503461-14.

On the "status bus" 87 of the processor 74, the status of the AL0 is available during each cycle (e.g. carry, negative, zero, overflow). The instruction modification circuit 73 allows the instructions recorded in the micro-PROM 71 to be adapted to indicate the number of bits to be rotated with instructions, such as, for example, "rotate n-bits". This number of bits is then specified over a number of lines (91) of the processor data lines 47. When an IEN signal on line 94 renders the instruction input of processor 74 inactive, the same processor instruction bits on bus 83 to the processor 74, also to the jump address control unit 79 via bus 84, and thus be used to jump the address sequencer 70 to any other address. Normally, the unit 79 receives its jump address from the contents of a register which is filled via bus 90 with data from data lines 47.

Condition selector 75 includes a one-out-eight multiplexer, the output of which is connected via line 89 to address sequencer 70. One of the eight possible conditions, which of the condition lines 49 of the RIP bus, or of the processor status lines 87, are applied via status buffer 76 and lines 88 at the input of the condition selector 75, can be selected. The selected condition is used by the address sequencer 70 to execute the desired conditional instruction. Any new conditions can be loaded into the status buffer 76 by applying a selection enable signal (SLE) via lines 85 to the status buffer 76.

The "waiting selector" 77 also includes a one-of-eight multiplexer, which in active condition connects one of the eight "waiting" lines 97 through line 93 to the address sequencer 70. A zero level on a queue stops the program counter from the program address register. The waiting lines are connected to the condition lines of the RIP bus.

The enable block 78 has various functions and additionally generates all the signals required for the control lines on the RIP bus. It performs three different functions: A. Generating "enables".

850 3 46 1 * \ -15-

The enable signals determine which of the data registers connected to the RIP bus with their outputs must be activated.

One enable line is available for each register.

B. Generating register clocks.

5 The clock lines determine which data registers connected to the RIP bus with their inputs should clock in. There is one clock line for each register.

C. Generating other signals.

The signals on the signal lines are used as flags and function selectors on the interface modules connected to the RIP bus.

Raster Image bus interface

The connection between the RIP bus 46 and the RI bus 17 is formed by the RI bus interface 45 (Fig. 7). This interface buffers the bi-15 directional data, the addresses to be called and the modification code.

Buffering is performed using registers. The registers "data-out" 120, "address-low" 122, "address-high" 123 and the modification register 124 can be loaded from the RIP bus 46. Loading is done under the control of address and control lines 48 of the enable 20 block 78 of the CPU 43. The "data-in" register 121 can be read under the influence of an enable line control of the enable block 78. The "address-high" register 123 contains the most significant bits of the address The "address low" register 122 contains the least significant bits. After loading the "address high" register 123 25, the RI bus read / write cycle is automatically started, this means that the following processes by the controller 125 are executed: cycle 1 puts an address on the RI bus and activates RAV, cycle 2 turns data-off on the RI bus and deactivates RAV, cycle 3- reads the data on the RI bus in the "data- in "register 121.

30 Before starting an RI bus cycle, the CPU 43 must test whether the RI bus busy line 57 is idle. This busy line 57 is connected to one of the waiting lines of the CPU 43.

The Raster Image bus (RI bus)

The RI bus 17 connects the RIP 15 to the bit-map memory 16 (RIM) and is made up of 64 lines. It includes a 32-bit wide multiplexed address / data bus. On RI bus 17, RIP 15 acts as master. The RIM 16, which comprises one or more RIM boards, does not itself take 8503 4 l.

-16- initiative on the bus. In addition, RI bus DMA devices can be connected to the RI bus 17, which can submit a request to the RIP 15 to obtain access to the bus.

The RI bus 17 is a synchronous bus. RIP 15 provides a 5 clock signal (BCLK) to the RI bus. All actions on the bus are performed on the sides of the bi-phase clock. Thus, all actions of the RIP on the rising edge, and all actions of the RIM on the falling edge of the clock signal (BCLK) take place. The other states on RI bus 17 can be described using three signal levels, high, low and high impedance (tri-state). All changes in signal levels occur after they are initiated by an active edge of the bi-phase clock. There are thus three groups of signals: the clock signals, the address / data signals and the other signals.

The signals that occur on the bus are defined below: - BCLK: this is a symmetrical clock, which is offered by the RIP on the RI bus.

- RAD 00 .. RAD 31 (RIP address / data lines): this is a multiplexed address / data path, which is controlled by all bus devices with 20 tri-state drivers. All lines are active "high".

- RMC 0 .. RMC 3 (RIM modify code): on these lines, a code is offered by the RIP or a DMA device to the RIM board. This code specifies the "modify" function that takes place during the logical operation performed on the RIM board on the content of the addressed memory word. These signals are also tri-state.

- RROFF (RI-bus refresh-off): this signal indicates that the RIM boards can switch off the refresh in order to achieve a minimum cycle time. To prevent loss of data, a special addressing sequence is maintained between the RIM boards and the RIP.

- RBR 0, RBR 1 (RI bus bus request): With these open collector signals, two DMA devices can request the bus arbitrator to access the bus. The devices have different priorities.

35 - RBG (RI-bus bus grant): with this line, the bus arbitrator indicates that the bus is available for the highest priority requesting device.

8503461 -17- - RBUSY (Rl-bus bus-busy): with this open collector signal, an addressed RIM board can indicate that the board is unable to process a new bus cycle for a certain period of time.

5 - RAV (RI bus address valid): This tri-state signal, which is low active, indicates that the Rl bus has a valid address.

The R1 bus is provided with a 32 bit wide data and address path which is multiplexed on RAD 00 .. RAD 31. The assignment of these lines is as follows: 10 A 24 - D 16: in this situation the address lines are RA00 .. RA23 used. The lines RAD 24 .. RAD 31 are then not care. For the data lines, RAD00 .. RAD15 is used. The lines RAD16 .. RAD31 are not care at the time. Data transport thus takes place on the basis of 16-bit words and the addresses are 24-bit wide.

15 Another possibility to use the 32 data and address lines is: A24 - D16 - D16: This situation is the same as the A24 - D16 situation regarding the address lines. By adding a second sign in the same address space, taking the data via the lines RAD16 ..

20 RAD31 on the bus, a two-bit data bus can be created with two boards that are internally 16-bit wide. On a RIM board it can be set over which part of the address / data bus the data is transported.

With the aid of the signals RBRO, RBR1 and RBG, access to the R1 bus is controlled between the RIP and any DMA devices. This arbitration is entirely outside RIM 16.

Each cycle on the bus consists of a WRITE / READ cycle. If the bus is free (RBUSY not active), the RIP can put an address (ADR £ nJ) on the bus on lines (RAD00 .. RAD23). This is done together with the provision of a RAV signal and an RI bus modify code (RMcode) via lines RMC00 .. RMC03 · After the address, the RIP offers its data (DATAOjnJ) on the bus on lines (RAD00 .. RAD15).

The RIM board addressed by ADRfnJ makes the RBUSY signal active. The RIP then goes off the R1 bus to allow the RIM board addressed by ADRfn-13 35 to bug DATAI £ n_- | j so that the RIP can read in this data. Two consecutive WRITE / READ cycles are thus pushed together. This 8503461 -18- is further optimized by coinciding the time it takes the RIP to decide if RBUSY has become inactive with the final processing phase of the RIM board addressed by ADRfriJ in the current cycle. This has been achieved because the RIMbord 5 makes RBUSY inactive before the RIMbord is completely ready, but it is already certain that this will be ready when the RIP can detect this. The first cycle therefore contains invalid data and an extra cycle is also required to retrieve the latest data from the RIM.

A minimum cycle time is achieved on the bus in the manner described above. The minimum cycle time refers to that timing order of bus states, resulting in a maximum transfer rate on the bus.

Due to the refresh of the RIM, it is possible that a RIM board 15 is unable to achieve the minimum cycle time. The RIM boards make this known by means of the RBUSY signal. By extending this RBUSY 3 signal by a certain number of clock periods (BCLK), the RIP postpones its next memory access by an integer number of clock periods.

20 The same situation can occur if the RIP has not yet completed a certain task. The RIP indicates this on the bus by delaying the RAV signal for a whole number of clock periods.

Raster image memory

The RIM 16 (Fig. 11) includes a 24 Mbit dynamic memory 220, organized into 16-bit words and is used as a page-sized bitmap memory. Each memory location in memory 220 corresponds to one exact location on the final printed page. The RIM 16 is connected to the RIP 15 via the RI bus 17 and is filled by the RIP 15 with expanded font data and graphic data. An important process that takes place in the RIM 16 is the modify process, which is performed on an addressed word. The modify process comprises 16 different logical operations which can be applied to the incoming data and the data already present at a certain address. One particular modify function is selected by providing a RIM modify code on the lines RMC0 ... RMC3 223 of the RI bus 17.

This modify code is put in the RMC register 222 and fed to the logic calculator 223 (ALU) which is built with programmable logic. The new data (NT) is supplied via the DATA0 register 227 over data lines 225 to the ALU 223, while the old data (0D) already present in the memory 220 is supplied via data output lines 226 to the ALU 223. The result of the operation (MD) in the ALU 223 is written into memory 220 via lines 224.

The table below shows some modify functions with the associated RM codes and the corresponding logic functions.

Modify RMC Logic function function 3210 15

WRITE 0 0 0 0 ND

PAINT 0001 ND.OR.OD

MASK 0010 ND.AND.OD

ERASE 0 0 11 NIJ.AND.OD

20 INVERT 0 10 0 ND

INV.PAINT 0101 ND.EXOR.OD

NOP 0 110 OD

CLEAR 0111 ZERO

SET 1 X X X ONE

25 _ ND = new data 0D = old data

Since the RI bus 17 is a multiplexed bus, the individual addresses and data must be clocked in registers. The RI bus

17 is connected to an address / data bus buffer 228 for this purpose, and when an address is presented on the RI bus 17, this address is supplied via buffer 228 to the address register 229. When data is presented (one clock period later), this data is transmitted via buffers 228 in the DATA

35 register 227 stored. The data-in register 230 ("in" for the RIP

but "off" for the RIM) has been added to the data from memory 220 associated with the previously offered address on the 850 3 4 e; -20-

R1 bus 17.

The control of the RIM 16 is provided by the memory control circuit 231. The memory control circuit 231 contains a bus state sequencer for starting a number of actions on a RAV signal, consisting of clocking in an address, clocking in of associated data, clocking in the modify code and putting data associated with the previous address on the RI bus 17. In addition, the memory control circuit 231 includes a memory state sequencer which is synchronized with the bus state sequencer. The 10 memory state sequencer can be initiated by a refresh request or by a bus cycle for a memory access. When a refresh cycle is performed, the next bus cycle must be suspended. Circuit 231 is implemented with programmable logic.

Memory 220 is constructed with 256 K dynamic memory chips and is organized into six "banks" of 256 K words of 16 bits. Bank selection takes place by decoding the address lines A18, A19 and A20 in the address multiplexer 232. Addressing a memory location in one bank is done using address lines 20 AO - A7 and A16 and generating a row address strobe (RAS) from the control circuit 231 »and then address lines A8, A15 and A17 are applied to the memory address lines via the address multiplexer 232, and a column address strobe (CAS) is also generated by the control circuit 231.

Because dynamic memories are used, all memory locations of memory 220 must be refreshed at least once every 4 msec. This is done by periodically adding a "RAS-only" cycle. A row address is offered to all banks during this cycle. The refresh address in a row is derived using a 9-bit counter which is increased by one after each refresh cycle.

Activating the RROFF line of RI bus 17 interrupts the normal refresh cycle and RIP 15 ensures that the minimum cycle time of the next cycle is met.

35 Unaddressed banks of the memory then use the address on the RI bus 17 to perform a refresh. Refresh takes place on the addressed bank by accessing the selected address.

850 3 46 1

♦ * A

-21-

When reading the RIM 16, if only one printout of a page is to be made, the "CLEAR” modify code will be put on the RI bus 17 because the RIM 16 must be completely filled with zeros after reading. must be saved to be printed again, the "NOP" modify code will be put on RI bus 17. Graphical instructions

The bitmap cleaner 28 (Fig. 2) is arranged to execute various text graphic instructions, such as, for example, CHAR, MCHAR, LINE and CIRCLE.

All of these instructions, which are stored in the micro-PROM 71 (Fig. 6), are executed as micro-instructions for the CPU 43.

The algorithms for these instructions are implemented in such a way that the largest possible bitmap filling speed is obtained.

CHAR: is an instruction to place a character in the correct place in the bitmap memory 16. Since the word boundaries of a character usually do not match the word boundaries of the bitmap memory, a displacement is necessary (see Fig. 9). In the font memory 13, the bitmap representation 200 of a character 201 is stored in 16-bit words. A character usually includes a number of 20 16-bit words, some of which are indicated by 203, 204 and 205.

The angular point 202 of the character 201 is taken as an example here as a reference point, and the first 16-bit word 203 contains 16 bits, the first bit of which is indicated by "0" and the last bit with "F". The bit representation of the first word is thus: 25 0000 0000 0001 1111.

When this mark 201 is placed at the desired y position in the bitmap memory 16, the word boundary 207 of the bitmap memory will generally only rarely match the word boundary 0 'of the mark 201. The operation to be performed will thus correspond to shifting the bitmap representation of the character 201 over a number of (n) bits, indicated in the figure by Δy.

At micro-instruction level, the following steps can be performed: rotate: from bit 0 to bit F over / ^ y (n: s Δ y) 35 merge: mask = 1 rotate mask s 0 non-rotate MCHAR: is a instruction for placing a character in the 8503461 -22 bitmap memory 16 in mirrored form. The reading of the bit-map representation of the character by the VME bus interface is done in reverse order. The displacement of the word boundaries of the character in the bit-map memory 16 is done in an identical manner as described for CHAR. The mirroring circuit is also housed in the VME bus interface.

For writing characters, lines, circles, etc. in the bitmap memory 16, the front end has a number of overlay options (Fig. 10). These 10 options are shown schematically in Fig. 10 on the basis of a letter V (210). A hatch 211 means that the content of the RIM 16 is unchanged. It is assumed that an "O" in the RIM yields "white" and a "1" in the RIM yields "black".

WRITE: the existing content of the RIM 16 is made "0" and the bitmap representation of a character is written with ones (212). 15 INVERT: the existing content of the RIM is made "1" and the bitmap representation of a sign is written with zeros herein (216).

PAINT: The content of the RIM is not deleted and the ones of the character undergo the ”0R” function (213) with the content of the RIM.

20 MASK: The content of the RIM is made "0" in those places where the character contains zeros, and where the character contains ones the content of the RIM is maintained (214).

ERASE: the content of the RIM is made "0" in those places where the character contains ones, and where the character contains zeros, the content of the RIM is maintained (215).

INVERTING-PAINT: The content of the RIM is maintained where the character contains a "0" and where the character contains a "1" the content of the RIM is inverted.

To make lines, circles and arcs, the measurement and control methods are used, based on Bresenham's algorithm. This is based on the theoretical course of the lines and for each scan line that point is chosen that is closest to this desired line. The known algorithm is described, for example, in ACM Transactions on Graphics, Vol. 1, no. 4, oct.

35 1972, p. 259-279 by Robert F. Sproull, entitled "Using programm transformations to derive line-drawing algorithms".

An algorithm is used for generating circles with a line width of one pixel, as described for example by 8503461 -23- J. Bresham in communications of the ACM, February 1977, volume 20 no. 2, p. 100-106, "A liniar Algorithm for incremental digital display of circular arcs". Allows circles to be drawn on a grid-shaped display using only 5-fold, and therefore quick, instructions such as testing a sign. and subtract.

A method is described below for generating straight line segments with a thickness of 3 or more pixels, wherein that line segment is stored in a word-oriented bit-map memory.

10 The line segment has a certain thickness (D) and round ends. The start point and end point coincide with a grid point, and the thickness is an odd multiple of the grid spacing. The grid is assumed to be a bit map contained in a word-oriented memory. In the description of the algorithm, use is made of a clockwise rotating Cartesian coordinate system consisting of an x-axis and a y-axis. The organization of the memory is such that the words in the memory are parallel to the y-axis.

A line segment 250 (Fig. 12) is given by the coordinates of the starting point 251 (Xbeg, Ybeg), the coordinates of the ending point 252 (Xe, Ye) and the thickness D measured in the field spacing. The boundary of the line segment 250 is given by a closed curve, which is in the region (XI <= X <= Xr, Ybot Y <= Ytop). Each value of X (XI <= X <s Xr) has two points, 253 (X, Yb) and 254 (X, Yt) that lie on the boundary of the line segment. The area covered by the vertical line segments (thickness nil) from (X, Yb) to (X, Yt) with (XI <= X <= Xr) is equal to the area occupied by the line segment with thickness D. The mapping of the line segment can thus be reduced to mapping the vertical segments for successive values of X between points Yb and Yt. The vertical line segments 30 are in the word direction of the memory. To depict the line segment with thickness D, the start and end points of these vertical line segments must be determined. These points are generated by determining the image of the boundary of the line segment with thickness D. The line segment 250 of thickness D can be delimited by a line through P1 and P2, a line through P3 and P4, a circular arc through P3 and P2 and a circular arc through P4 and P1. As noted earlier, line segments can be mapped using the Bresenham algorithm. It is therefore necessary that the start and end points of the line segment coincide with a grid point. In most cases, however, points P1, P2, P3 and P4 will not coincide with a grid point, but will each be surrounded by four grid points: Pi1, Pi2, Pi3 and Pi4 5 (i = 1 ... 4).

Figure 13 shows a line through points PI and P2. Of the grid points P1j (j = 1 ... 4), the point which has the smallest distance to the line must be chosen as the starting point of the line segment to be displayed, i.e. point P12. Analogously, a choice is made for the end point, point (P24), of the line segment to be displayed. The Bre-senham algorithm is also used to map circles. The starting point (Xbeg, Ybeg) and the ending point (Xe, Ye) of the line segment to be imaged with thickness D now coincide with the grid point. The requirement of the Bresenham algorithm that the center of the circle must coincide with the grid point is thus met. Not all the grid points of the circle image have to be generated, but only the points that belong to the image of the arcs that form the image of the boundary of a line segment of thickness D with the line segments shown. The coordinates of the grid intersections P1 *, P2 *, P3 * and P4 * can now be determined with the aid of 20 data about the start and end points and the thickness of the line segment.

Given a circle 261 (fig. 14) with center 251 (Xc, Yc) and radius R and a line segment 262 with starting point (Xbeg, Ybeg). The starting point 25 of the segment and the center of the circle coincide with point 251. The radius R of the circle 261 is equal to (D-1) / 2. The circle 261 and the segment 262 intersect at the intersection S. Of the four grid points S1, S2, S3 and S4 surrounding S, the one with the smallest distance from the tangent line 263 to circle 261 must be selected by S. This grid point S * with the coordinates (X *, YK) provides the information to determine the coordinates of the grid intersections P1 *, P2 *, P3 * and P4X, ie the start and end points of the two line segments of the boundary. The perpendicular distances from the point S * to the center 251 (Xc, Yc) of the circle 261 are determined, where Hx = Xx - Xc, and Hy s Y * - Yc. It follows for the coordinates of the grid intersections: 8 5 Θ 3 4 o's -25- PI *: (pbeg - HyJ, pbeg + HxJ), P2 *: (pe - HyJ, pe + HxJ), P3 * s (pe + HyJ, pe - HxJ), and P4 *: (pbeg + HyJ, pbeg - HxJ).

5 Points P1 * to P4 * now coincide exactly with the grid points. The images of the line 262 and circle 261 are determined with the Bresenham algorithms.

When generating a segment, it is assumed that the center of the circle coincides with the origin of the coordinate system and that a segment is located in the first octant. This assumption does not detract from the generality, since the other cases can be transformed to this case by a simple translation.

The Bresenham algorithm for the line segment is started at the origin of the coordinate system and the Bresenham algorithm for the circle is started at point (R, 0), where R is the radius of the circle. These algorithms are executed almost parallel in the front-end. The grid points generated are synchronized to an equal y value. With the following algorithm, the 20 coordinates (X *, Y *) of the intersection point S * are determined. The algorithm converges to the area around the intersection point S. In this area, a selection for S * with the coordinates (X *, Y *) is made. Fig. 15 shows the determination of the intersection point S * in a flow diagram.

After starting (300) the algorithm, first the different 25 variables of the line and circle are initialized (301): XL = 0, YL = 0, XC = R and YC = 0. When the conditions XI <XC ( 302) the value of XL is increased by one (303). Then the Bresenham algorithm calculates the value for YL of the line (304). If the conditions YL> YC (305) are not met, the program jumps back to block 302. If XL ^ XC still applies, the program loop consisting of blocks 303 and 304 is run through again and the value of YL is again compared with YC in block 305. If the condition YL> YC is met, then YC is increased by one (306) and using the Bresenham algorithm, XC is calculated for the circle (307), after which the program returns to 302. In this way, the two program loops consisting of blocks 302 to 305 and blocks 302 to 307 continue through 8503461 -26- until XL is no less than XC (302). The program then jumps to block 308. If now XL = XC then X * is made equal to XL and Y * to YL (309). If XL XC (308) then follows for the values of X * and Y * (310): X * = XC + 1 and Y * s YC - 1.

The line segment 250 (fig. 16) is given by the coordinates of the starting point (Xbeg, Ybeg), the coordinates of the ending point (Xe, Ye) and the thickness D measured in the field spacing. It is assumed that Xe> = Xbeg and Ye> s Ybeg. In other words, the line segment is at an angle to the positive x axis that is between 0 ° and 90 °. If Xe <Xbeg, 10 then the assumption Xe> = Xbeg can be satisfied by switching the start and end points. If Ye <Ybeg then by mirroring a line segment around the horizontal line y = Ybeg (Ye ° = 2 x Ybeg - Ye) the assumption Ye Ybeg can be satisfied. However, the start and end points of the vertical line segments must then be mirrored about the line y = Ybeg before the raster points belonging to the image of these vertical line segments (in the bit map) are activated.

After determining S *, the coordinates of P1 * (XT *, Y1X), P2 * (X2 *, Y2 *), 20 P3 * (X3 *, Y3X) and P4 are described in the manner described above. * (X4 *, Y4 *) determined. The data is now available to run four algorithms, two line and two circle algorithms, almost in parallel. In fig.16, circle 1 runs from point 255 to P1 * and from P2X to point 256, circle 2 runs from point 255 to P4 * and from P3 * to point 256. Line 1 runs from P1 * to P2 * and line 2 runs from P4 * 25- to P3 *. The circle algorithms 1 and 2 generate a semicircle which, when P1 * and P4 *, respectively, replace the center 251 (Xbeg, Ybeg) with the center 252 (Xe, Ye). The line generation successively traverses regions 270 through 274.

In figures 17a, b and c a flow diagram shows the applied algorithm. The program starts (320) with initializing some variables (321) such as R = (D - 1) / 2, XI = Xbeg - R, XR = Xe + R, Xc1 = Xbeg, Yd = Ybeg, Xc2 = Xbeg , Yc2 = Ybeg, X = XI,

Yt - Ybeg and Yb s Ybeg. For X = XI, the first vertical line is also drawn (321). The code (Drln (X, Yb, Yt)) denotes the instruction: draw a vertical line at this X, between points Yb and Yt and place this line at the corresponding place in the bit-map memory. Subsequently, the calculation and generation of the vertical lines in the area 270 is started and the generation (Fig. 16). X <X1 * (324) is tested. If this is the case, first X is increased by one (322) and with the aid of the Bresenham algorithm the point Yt on circle 1 and the point Yb on circle 2 (323) are determined for this value of X.

5 Also, the vertical line between Yb and Yt is drawn (323) (Drln (X, Yb, Yt)) and the program returns to 324. As long as X <Xl *, loop 322, 323, and 324 continues to run .

When X = X1 *, the program goes to block 325. Here. 10 compares whether X4 * <X2 *. If the answer is no, then, as will be explained later, the program is run from block 350 to block 364. This applies, for example, to steep lines and lines that are short in relation to their thickness. When it holds that X4 * <X2 * (325) and X <X4 * (328) then X is increased by one (326) and 15 using the Bresenham algorithm, the point Yt on line 1 is determined for this value of X and the point Yb on circle 2 (327). In addition, for this value of X, the vertical line between Yb and Yt is drawn (323) (Drln (X, Yb, Yt)) and stored in memory.

As long as X <X4 * (328), so for the area 271 (Fig. 16) the 20 program loop 326,327 and 328 is run. Upon reaching X = X4 * testing for X <X2 * (331) and if so the program continues to increase the value for X by one (329), calculating Yt with Bresenham's algorithm at line 1 and Yb on line 2 and again Dlrn (X, Yb, Yt) (329). As long as X <X2 * (331) applies for the area 272 (Fig. 16), the program loop 329,330 and 331 are run through.

When X = X2 * is reached, the original variables Xc1 and Yc2 are first changed in block 332 by now entering the coordinates of the line end point. So: Xc1 s Xe and Yd a Ye. Generation of the area 273 (Fig. 16) 30 then takes place. It is tested whether X <X3 * (335) and if so, the value of X is increased by one (333) and with the Bresenham algorithm the value for Yt on circle 1 is determined and the value for Yb on line 2 (334). Drln (X, Yb, Yt) (334) places the corresponding vertical line in the bitmap memory. As long as: X <X3 * (335), the 35 program loop 333,334 and 335 are run through. When X reaches the value for X3 *, the original variables Xc2 and Yc2 are adjusted (336) according to: Xc2 = Xe and Yc2 = Ye.

§ R I) η * \ «J v o. <· -28-

Generation now takes place for the last region 274 of the line segment. If X <XR (339) applies then X is increased again by one (337) and with the Bresenham algorithm Yt on circle 1 and Yb on circle 2 (338) is determined and with Drln (X, Yb, Yt) the vertical 5 line placed in the bit-map memory. As long as X <Xr (339) applies, the program loop 337,338 and 339 are run through. When X reaches the value XR, the generation of the segment is complete and the program stops in block 364.

For straight lines (X4 *> X2 *) the program jumps from block 10 325 to 350. When X <X2 * (352) holds, the value for X is increased by one (350) and with the Bresenham algorithm Yt is now line 1 and Yb on circle 2 (351) are determined and with Drln (X, Yb, Yt) this vertical line is written in bitmap memory (351). As long as: X <X2K (352), the program loop 350,351 and 352 are run through.

For X = X2 *, as in block 332, the variables for Xc1 and Yc1 are changed to Xc1 = Xe and Yc1 = Ye (353). When X <X4 * (356) applies, X is increased by one (354) and with the Bresenham algorithm Yt on circle 1 and Yb on circle 2 is now determined (355) and the line between Yb and Yt on the corresponding place on the bitmap memory 20 is set aside (355). As long as the following applies: X <X4 * (356), the program loop 354,355 and 356 are run through. At X = X4 * it is tested whether X <X3 * (359) and if so, X is increased by one (357) and with the Bresenham algorithm Yt on circle 1 and Yb on line 2 is determined and with Drln (X , Yb, Yt) (358), this line is written into memory 25. At X <X3 * (359), the program loop 357,358 and 359 are always run through. When X = X3 * the variables are changed (360): Xc2 s Xe and Yc2 = Ye. As long as X <XR (363) holds, X is increased by one (361) and with the Bresenham algorithm Yt on circle 1 and Yb on circle 2 is determined (362) and with Drln (X, Yb, Yt) (363) a 30 memory store. As long as X * Xr (363), program loops 361, 362 and 363 are run. When X reaches the value XR, the line generation ends and the program (364) stops.

Correspondingly, an algorithm can be drawn up for line segments with straight ends. Such a line section 35 is shown in Figure 18. The boundaries of the line segment are the points P1, P2, P3 and P4. As with the generation of a segment with round ends, these points will have to coincide with the grid points 8503461 p p -29-P1 *, P2 *, P3 * and P4 *. These points are therefore determined in a corresponding manner. S * is first determined with an algorithm as described in figure 15. Subsequently, the auxiliary functions Hx and Hy are defined according to: 5 Hx = X * - Xc and Hy = Y * - Yc. It follows again for P1 *: (JXbeg - Hy - HxJ, (Ybeg + Hx - HyJ) P2 *: (fXe - Hy - HxJ, £ Ye + Hx - HyJ) P3 * s (£ Xe + Hy - HxJ, CYe - Hx - HyJ) and P4 *: (fXbeg + Hy - HxJ, £ Ybeg - Hx - HyJ) 10 Now all data is known for determining the line segments P1 * P2 *, P4 * P3 *, P1 * P4 * and P2 * P3 * meaning line 1 (line 1), line 2 (line 2), line 3 (line 3) and line 4 (line 4) respectively. The (Pascal) program looks like this: XI: = XI *; 15 Xr: = X3 *; X: = XI;

Yt: s Ybeg;

Yb: = Ybeg;

DrawVerticalLine (X, Yb, Yt); 20

IF (X4 * <X2 *) THEN BEGIN

WHILE (X <X4 *) DO START

X: = X + 1; BRESENHAM_LINE 1JSTEP (Yt); BRESENHAM_LINE3__STEP (Yb);

DrawVerticalLine (X, Yb, Yt) END;

30 CX = X4 * J

WHILE (X <X2 *) DO START

X: s X + 1; BRESENHAM_LINE 1 JSTEP (Yt); BRESENHAMJLINE2JSTEP (Yb);

DrawVerticalLine (X, Yb, Yt)

tX = X2 * J

8503461 ί · -30-

WHILE (X <XR) DO BEGIN

X: = X + 1; BRESENHAM_LINE4_STEP (Yt); BRESENHAM_LINE 2_STEP (Yb);

DrawVerticalLine (X, Yb, Yt) END;

END

£ X = Xright J

10 ELSE

GET STARTED

WHILE (X <X2 *) DO BEGIN X: = X +1; BRESENHAM_LINE1__STEP (Yt); BRESENHAM_LINE3-STEP (Yb); DrawVertikalLine (X, Yb, Yt) END; CX = X2x]

20 WHILE (X <X4 *) DO START

X: = X + 1; BRESENHAM_LINE4_STEP (Yt); BRESENHAM_LINE3_STEP (Yb); DrawVerticalLine (X, Yb, Yt) END; CX = X4 * 3

WHILE (X <XR) DO BEGIN

X: + X +1; BRESENHAM__LINE4_STEP (Yt); BRESENHAM_LINE2_STEP (Yb); DrawVerticalLine (X, Yb, Yt) END;

35 END

CX * Xright J.

8503461 -31-

The above-described algorithms make use of the word organization of the memory and guarantee that the number of accesses to the memory is minimal. The thickness of a line segment is usually small compared to the length of that line segment. This implies that it takes relatively little time to determine the coordinates from P1 * to P4X, so that described lines of the "Solid" type can be displayed on a grid extremely quickly.

The invention is not limited to the described embodiments. For example, with comparable methods of line generations, line segments can be implemented on other than orthogonal grids. However, these and other methods which can be easily deduced from the line generations described by those skilled in the art will all be covered by the following claims.

3503461

Claims (4)

A method for generating a line segment of thickness D on a homogeneous grid whose grid points are arranged in a number of parallel lines, and wherein the bit representation of the line segment (250) is stored in a word-oriented bitmap Memory in the form of a large number of pixels or pixels, characterized by determining the envelope of the line segment and mapping this envelope on the grid dots, determining for the successive grid lines the length of the section through the segment , and placing the bit representation of these lengths in the bit map memory in corresponding places, the direction of the determined lengths corresponding to the word direction of the bit map memory. Method according to claim 1, characterized by determining the mapping of the start and end points of the line segment (250) on the grid points, generating a circle (261) with the starting point of the line segment as the center point (X *, Y *) and with (D - 1) / 2 as radius, determining the four grid points within which the intersection (S) of this circle (261) and the line (262) through the starting point (251) and the end point (252) of the line segment (250) is located, determining that grid point (S *) in the immediate vicinity of the intersection point (S) that has the smallest distance from the tangent (263) to the circle (261 ) through the intersection point (S), and determining four grid intersection points (P1 * to P4 *) as points of the envelope shown by means of this determined grid point (S *). Method according to claim 2, for generating a line segment with round ends, characterized in that the four grid intersections (P1 * to P4 *) represent the images of the terminals between the round ends and the straight enveloping lines of form the line segment. Method according to claim 2, for generating a straight-ended line segment, characterized in that the four grid intersections (P1 * to P4 *) form the images of the vertices of the envelope lines of the line segment. 8503461