NL8302290A - MODULERIZED COMPUTER SYSTEM. - Google Patents

Description

N.0. 31919 1

Modulerized computer system.

The invention relates to a computerized data processing system and more particularly relates to a modulerized system. The invention also relates to circuits and systems in connection with the distribution of power in computers and the like.

Today there are a number of modulerized computer systems. These are referred to as "suitcase" or "attache suitcase" computers Such systems generally include a small computer which has a central processing unit (CPU) and input / output (I / O) devices, such as a keyboard and a display device The computers are designed to store information and interact with other units, such as floppy disk drives, CRT displays, printers, etc. Generally, these computers have been found to be bulky, often weighing more than 20 pounds, that they absorb a large amount of power, and that they have a limited duty cycle requiring frequent charging and recharging of their batteries for operation In addition, such devices are limited at the time of manufacture. with regard to which specific peripherals they can use, tfan-20 therefore a peripheral is exchanged in a manner that at the time of the manufacture of the computer has not been considered or if a new peripheral is desired, the computer will have to be modified.

Another drawback of such disappearing computers is the use of short-lived power sources. Long-life batteries are often bulky, and their application greatly increases the weight of the unit. Furthermore, monitoring circuits used to determine whether batteries still have enough voltage to operate the computer or to prevent the computer from turning on usually cause some power loss even when the computer is turned off, thereby limiting the operating life of the batteries further decreases.

Many approaches to limit power consumption from batteries are known. It is therefore known to save battery life by switching the batteries so that they are selectively connected in series or parallel according to at least one predetermined state, such as a phenomenon or voltage level. It is also known to provide an indication of voltage level by means of any warning means, such as a lamp, to warn the user that the power supply will shortly fail.

It is believed that it is known in the prior art to provide a computer memory for storing information in the same pattern or arrangement as this information would be when displayed on a standard CRI display. While such computers have a smaller power display, it is believed that it is known to treat the smaller display as a "window" that presents the information in memory and "scroll" the "window" relative to the memory display (scroll ) "or to move. Such a display is believed to have been identified as an Osborne computer in the June 1982 issue of Byte Magazine.

On the other hand, it is believed that the application of a "window" display in combination with a stored larger display, which may then also be associated with a CRT display at a separate time or at the same time, and showing the line and drawing position can be coordinated, hitherto unknown.

The object of the invention is to provide means for determining the level of the battery voltage of a battery-powered system, in which the determination means are removed from the battery when the device is not in use.

The invention also aims to provide an intelligent switchover of battery power sources within a computer in order to extend the working life of the battery and to strictly maintain the life of the battery.

The invention also aims to provide a computer which has the ability to change its operation in order to accept and interact with peripherals, the peripherals of which the work requirements were not known at the time of the computer's construction.

Another object of the invention is to provide a computer that is highly portable, inexpensive to manufacture, easy and simple to use.

Another object of the invention is to provide an I / O display that copies or repeats a predetermined portion of the information from a particular area of a memory to thereby provide a "window" in the memory.

Another object of the invention is to provide means for rolling the window around the defined region.

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The invention also aims to provide a computer with a "window" display that can be moved to predetermined parts of the area independently of a cursor position.

The invention also aims to provide means for returning the moved "window" display to the cursor-displaying position upon instruction.

The invention also aims to provide a computer which, when switched ON, configures itself for use with peripherals.

According to an aspect of the invention, there is provided a computer having a central processing unit (CPU) and read / write memory means therein. The read / write memory means has dedicated locations reserved for simulating the rules and drawing locations of an I / O display. I / O means are also provided. The I / O means include an alphanumeric keyboard and an alphanumeric display. The I / O display has considerably less capacity than the simulated I / O display in the read / write memory means. The I / O means are connected to the CPU and the read / write memory means such that the display provides a "window" in the simulated display. The information displayed in the "window" copies or repeats the information in the corresponding drawing. and control locations in the simulated display The keyboard contains at least one means of delivering an instruction to the CPU This instruction selectively causes the CPU to copy additional information from the simulated display and takes excess information from the I / O 25 display to thereby move or scroll the "window" relative to the simulated display.

According to another aspect of the invention, there is provided a computer of the type that can be coupled to and interact with a number of peripherals. Each peripheral is connected to a 30 modular unit. The computer according to the invention has a CPU and read / write memory means. The read / write memory means is operatively connected to the CPU. Each module has fixed memory means. The fixed memory means can be operatively connected to a peripheral device and to the CPU. The fixed memory means have instructions therein to initialize at least the peripheral. The computer also has means operatively engaged by the CPU and each of the module hard memory means to selectively connect the CPU to a predetermined of the hard memory means instead of the read / write memory means to initialize and initialize the peripheral device. operate.

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According to another aspect of the invention, there is provided a computer of the type that can be connected to and operate with a number of peripherals. The computer contains a CPU within the computer and read / write memory means. The read / write memory means are operatively connected to the CPU. A number of modules are also provided. Each module can be connected to a peripheral device. Each module has fixed memory means operably connected to the peripheral and the CPU. The fixed memory means has instructions to initialize and operate at least the peripheral. The computer has means operatively engaged by the CPU and the module fixed memory means to selectively connect the CPU to the fixed memory means in a predetermined one of the modules instead of the read / write memory means. As a result of this replacement, the peripheral can be initialized and operated. The selection means has means within the CPU to interrogate each module in series and to carry out the initialization. The initialization includes storing in the read / write memory means at least the presence or absence of a peripheral.

According to yet another aspect of the invention, a device is provided for selectively selecting a station from a plurality of stations. This device comprises at least one circuit associated with each of the stations. Each circuit is connected in a daisy chain. The circuit has a bistable flip-flop and two ports connected to the flip-flop. The Q and Q * outputs of the flip-flop 25 are respectively connected to one of the inputs of the gates. The output of one of the ports is connected to the clock input of the flip-flop at the next station in the daisy chain. The other inputs of the gates are connected to the clock input of the flip-flop.

The D inputs of the flip-flops are connected to each other and to the release or wipe input to complete the daisy chain. Means are provided to output a clock signal to the first input of the clock inputs of the first flip-flop in the daisy chain and a signal to each input of the D inputs of the flip-flops such that when there are logic inactive signals are supplied by the supply means 35 to the D inputs and the first of the clock inputs, the circuits are inactive. When logic active signals are applied to the D inputs and an active signal is applied to the first clock input, the gate connected to the Q output provides a logic active signal to the first circuit. When the signal at the first 40 clock input is switched from an active state to an inactive state and then to an active state, the signal from the gate connected to the first Q * output becomes active and the signal from the port connected to the Q output inactive. As a result, the clock input of the next circuit becomes active and the gate of the second circuit connected to the second circuit flip-flop Q becomes active. All other circuits remain inactive.

According to yet another aspect of the invention, a power distribution system is provided for connecting a power source to a computer or the like. The power distribution system has a protection circuit which is connected to the power source. An on / off switch is also fitted to connect the protection circuit to earth. A battery protection circuit supplies a BPRT-3 * signal to the protection circuit to indicate that a second predetermined voltage level is coming from the power source.

Switching means are provided which respond to the signal of the protection circuit and have an open and closed state. In the closed state, the switching means provide power or power.

The battery protection circuit is connected to ground and can absorb power from the switching means when the switching means are in the closed state to thereby complete the battery protection circuit. The battery protection circuit has means to detect the power level and to deliver the BPRT-3 * signal to the protection circuit. Due to the fact that the on / off switch is closed and the switching means are in a closed state, when the battery protection circuit issues the BPRT-3 * signal, the protection circuit opens the switching means in response to this BPRT-3 * signal. provide condition.

According to yet another aspect of the invention, a circuit is provided for determining the voltage level of a power source and for outputting a signal to indicate the presence of a low voltage. The circuit includes a comparator circuit to output a signal indicating a high voltage level and a low voltage level. A level shifter is also provided to shift the indicated signal. Furthermore, a coupling circuit is provided to connect the comparator circuit to the level shifter circuit. The coupling circuit breaks the other two circuits when the voltage level compared by the comparator circuit is above the low voltage and connects the two circuits when the compared voltage level is below 40 the low voltage.

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The invention will be further elucidated with reference to the drawings, in which: figure 1 shows a perspective view of the computer constructed according to the teachings of the invention in combination with peripheral equipment; Figure 2 shows a logic and supply flow diagram of the computer of Figure 1; Figures 3 to 6 show diagrams of parts of the power supply system of the computer; Figure 7 shows a block diagram of the mutual working connection of the power supply circuits; Figure 8 shows an information flow block diagram of the computer according to the invention; and Figure 9 shows a circuit diagram of a daisy chain configuration constructed in accordance with the teachings of the invention.

Small computers have many features that were previously only available in larger complex units. The history of computer development shows an ongoing decrease in computer size associated with an increase in the functions performed (ie, computer "power"). This observation is nowhere better reflected than in the application of a computer in the office environment As a result of this steady improvement, demand has developed for certain features that have not been available so far, for example, users have been looking for a relatively light computer that has a duty cycle of sufficient length to get most operations away from an AC power source during a normal working day A further object was to provide a computer with input / output means that allows the user to display at least some of the information addressed by the computer and yet enter the computer. enables to operate and display a full CRT screen in the office, another purpose is to reduce the impact of aging caused by designing new peripheral units that were not foreseen when the computer was manufactured, or to be modified when existing peripherals are greatly improved so that the work requirements change. It is believed that no existing computer can fulfill these purposes.

In order to meet these purposes, a portable computer 20 (Figure 1) is provided which can work separately and in an office with peripherals. Thus, the computer 20 is connected to a 40 "office station" interface 22 and (in the example of Figure 1) to 1 * 7 a floppy disk drive 24 and a CRT display 26 which are of known design. As explained below, the display 26 and the drive 24 need not be of a presently known design to be operated by the computer 20.

The portable computer 20 may include input / output devices that include, for example, an alphanumeric keyboard 28 and an alphanumeric display 30.

One of the essential elements of the portable computer device is a means of enabling the economical use of its power supply to save power under the control of the computer battery. This computer 20, as part of the operating means, has a fixed memory which serves to hold information and which can also be used as a functional alternative to a disk drive. To this end, the computer 20 can use at least one bubble (bubble) memory 32 (Figure 2). Power can be supplied from a voltage source, which may be a source of battery power 34, for example. Power from the battery source 34 may be supplied to a voltage regulator or regulators 36. Also, the power supply can be supplied by a battery charging circuit 37 which can be used to either charge the battery 34 or to supply such a voltage as necessary to the voltage regulator 36. The power supply of the voltage regulator 36 is also supplied to a CPU 38 and input / output devices 40 are provided which generally include both the alphanumeric keyboard 28 and the display 30 of the computer 20.

Overall, certain design uses have been adopted. It will be understood, however, that complementary uses can also be applied without substantial change in the function of the computer. Therefore, all voltage sources are positive, the transistors are of the NPN type unless otherwise specified.

For a personal computer to be portable, it must have an extended battery life. This means that the battery-powered power supply should be used as sparingly as possible. An important approach to the invention is to provide circuits that do not consume any power when not in use (ie, when the user's on / off switch is OFF). When the computer is turned ON, the power circuit provides five important functions. The circuit determines when there is sufficient battery power to operate the computer. When there is enough power on-40, it will turn the computer OFF. When 8302290 A ’* 8, when there is sufficient power supply, it will allow the computer to stay IN. When the battery power becomes too low during operation (but not low enough to turn the computer OFF), the circuit will issue a warning to the user that the batte-5 driving power is too low. When the battery power becomes too low, it will turn the computer OFF. When the computer is turned OFF, it will issue a warning to a bubble memory controller to provide proper shutdown of a bubble memory in the computer. Ultimately, when the computer is turned OFF, when the user's switch is still ON, the power draw will be reduced to the power used by a relatively small number of discrete circuit elements with low power draw.

In view of the fact that this computer is a portable and given that the battery power source 34 is subject to losses, the computer 20 is provided with a battery level sensor or sensor circuit 42.

The logic power switching circuit 44 directs the flow of power. The combination of the battery charging circuit 37, the battery power source 34, the voltage regulator 36, the logic power switch circuit 44, and the battery level sensors 42 form the heart of the power distribution system 46.

The operation of the distribution system 46 can be more fully understood from the interconnections of its components. The positive and negative terminals 25 of a secondary battery 48 are directly connected to the luminaires 54 and 56 of a relay 58 (Figures 3 and 7). Each luminaire 54 and 56 can make contact with one of the pairs of fixed contacts 60 and 62, 64 and 66 respectively. Relay 58 is operated in such a way that in the OFF state the luminaires 54 and 56 will contact the fixed contacts 62 and 66 and IN will contact contacts 30 60 and 64. The fixed contacts 62 and 64 are connected to each other and to a positive terminal 74 of a primary battery 76. The negative terminal 78 of the battery 76 and the fixed contact 66 are connected to ground 80.

The positive terminal 74 of the primary battery 76 is connected such that a B + voltage is applied to a protection circuit 52 (Figure 3). The protection circuit 52 is intended to prevent the computer 20 from turning ON when the battery voltage is too low, to turn the computer 20 OFF in response to parasitic signals, and at the same time to conserve the most significant power-absorbing circuits - including of those intended to monitor the voltage of the 8302290 * * 9 „batteries 48 and 34 - when not in use keep the batteries 34 and 48 disconnected.

A resistor 68, which may be, for example, a 47 K ohm resistor, is connected to the positive terminal 74 of the primary battery 76. A resistor 70 is connected in series with a capacitor 72. The other end of the resistor 70 is connected to the positive terminal 74 and the other end (negative polarity) of the capacitor 72 is connected to the other end of the resistor 68. The resistor 70 in this example may be 20 K ohms and the capacitor can be 15 microfarad 10. A diode 120, which may be an IN914A diode, is connected across the resistor 70 with its cathode connected to the positive terminal 74 of the primary battery 76.

A resistor 122, which receives the battery protection signal (BPRT-3 *) at one end, which will be explained more fully below, may be 20 K ohms. The other end of this resistor is connected to another 20 K ohm resistor 124. The junction of the two mentioned resistors 122 and 124 is connected to the base 88 of a transistor 90. The transistor 90 may be of the type 2N2222A whose emitter 92 is connected to the resistor 124 and the other end of the the resistor 68.

The anode of diode 120 is also connected to an input 93 of an SS flip-flop 94 and an input 96 of a logical HAND gate 98. The flip-flop 94 and the NAND gate can each be 74COO gates. For example, a bias resistor 100 of 200 ohms is connected to the flip-flop 94 and to the positive terminal 74 of the primary battery 76.

A 20 K ohm resistor 102 is connected from the positive terminal 74 to the collector 104 and another of the inputs 106 of the RS flip-flop 94. The outputs of each gate of the two ports of the flip-flop 94 are connected to one of the respective inputs and the output 30 of one of the gates connected to the input 108 of the NAND gate 98. All these connections are known in the art.

The output of the NAND gate 98 is connected through a 20 K ohm resistor 110 to the base 112 of an MPSA-14 transistor 114. The base 112 is connected to the resistor 110 through a 20 K ohm resistor 116 to an earth pin of the RS flip-flop 94 and the emitter 92. The emitter 118 of transistor 114 is connected to resistor 116 and emitter 92.

The protection circuit 52 (Figure 3) is schematically shown as a box in conjunction with the general circuit configuration (Figure 4). The collector 126 of the transistor 114 (figure 3) is connected via the line 40 to a terminal 130 of a coil 132 of a relay 3 ό Ü 2 C 2 Ü> * fc 10 134. The other side 136 of the coil 132 is connected to the normally open relay contact 138 and the positive terminal 74 of the primary battery 76.

The base 140 of a 2N2907 PNP transistor 142 is connected to the positive terminal 74. The emitter 144 of the transistor 142 is connected to one side 130 of the relay coil 132 to the protection circuit 52. The emitter 144 is also connected via a series connected 0.1 microfarad capacitor 146 and 10 ohm resistor 148 connected to ground 80.

The on-off switch 84 of the computer has a contact 86 connected to earth 80. The arm 82 of the switch 84 is connected via a line 150 to the protection circuit 52 (figure 3). Lead 150 connects resistor 68, capacitor 72, resistor 124, emitter 92, RS flip-flop ground pin, resistor 116, and emitter 118.

Collector 152 of PNP transistor 142 provides a BPRT-1 * signal over line 314 (Figure 4), the function of which will be explained below.

The arm 156 of the relay 134, when in contact with the open contact 138, provides a voltage of 6 V to the system (SYS) from the battery 76 over the lead 158.

The SYS voltage is supplied along line 158 to a 5 V regulator 160 (Figure 5). The regulator 160 is of conventional design and is not in itself part of the invention. The lead 158 (which provides 6 V 25 SYS) is connected to the emitter 162 of a PNP transistor 164 (which may be a TIP42A) as well as the junction of a 510 ohm resistor 168 and a 5.49 K ohm resistor 170. The base 166 of transistor 164 is connected to the junction of the other side of the 510 ohm resistor 168 and a 75 ohm resistor 172. The 75 30 ohm resistor 172 is connected to the collector 174 of a 2N2222A transistor 176. The other end of the 5.49 K ohm resistor 170 is connected to the emitter 178 of the 2N2222A transistor 176 and the first anode of a series circuit (cathode to anode) of three 1N914A diodes 180, 182 and 184. The last diode 184 is connected to ground 80 The collector 186 of the TIP42A transistor is connected to the anode of a 1N4Q02 diode 188. The cathode of this diode 188 is connected to lead 158.,

The two transistors 164 and 176 form a voltage regulator. The base 190 of the 2N2222A transistor 176 is connected to the connection point of a 5.49 K ohm resistor 192 and the anode of a 1N419A

11 diode 194. The cathode of diode 194 is connected to the output of an LM358AN operational amplifier 196 and a 0.01 microfarad capacitor 198. Other connections to the operational amplifier 196, which are known, are constituted by a 100 ohm resistor 200 connected to a 1 microfarad capacitor leading to terminal 8 of the amplifier and grounding of terminal 4. The 100 ohm resistor 200 is connected to the 5.49 K ohm resistor 192 and to the 3.75 K ohm resistor 204. Resistor 204 is connected to terminal 3 of amplifier 196. A zener diode 206 connects terminal 3 and resistor 204 to ground 80 to provide a regulated 2.5 V at that point.

The capacitor 198 is connected to a 200 ohm resistor 268. The other end of the resistor 268 is connected to the terminal 2 of the operational amplifier 196, a 0.1 microfarad capacitor 270 and the center arm 272 of a 200 ohm potentiometer 274. The One side of the potentiometer 274 is connected to a 2.49 K ohm resistor 276. This resistor 276 is connected to the junction of capacitor 270 and collector 186 of transistor 164. The other side of potentiometer 274 is connected via a 2.49 K ohm resistor 278 connected to ground 80. A 0.1 microfarad capacitor 280 20 is connected across the zener diode 268. A 680 microfarad capacitor 282 is connected to the collector 186 and to ground 80 creating a regulated 5 V (Vjyjg) at its output.

The battery charging circuit 37 (Figure 4) is a known circuit. The circuit includes a 1: 1 bifilar wound transformer 284, each winding of which is connected to, for example, a BCA connector (not shown). The positive terminal of this connector is connected via a winding 286 to a protection diode 288. A 100 microfarad capacitor 390 is connected with its positive terminal to the cathode of the diode 288 and to the other winding 232 of the transformer 284 and the emitter 234 of a 2N2222A transistor 236. The base 238 of transistor 236 is connected to ground 80 and to emitter 234 via a 0.8 ohm resistor 240. The collector 330 is connected to the terminal 1 of a current limiting constant voltage circuit LM 317 324. The diode 288 and the capacitor 390 are connected to the terminal 3 of the circuit 324. The emitter 330 is also connected to the terminal . point of the 243 ohm resistor 326 and a 1.24 K ohm resistor 336. This resistor 336 is connected to ground 80. The first resistor 326 is connected to terminal 2 of circuit 324 and the anode of a 1N5820 diode 328. The The cathode of the diode 328 is connected to the positive terminal 74 of the battery 76.

83 02 2 9 0 "12, The battery level sensing or sensor circuit 42 (FIG. 5) includes a battery protection circuit 318 and a battery low indication circuit 292 (bat layer circuit). The battery protection circuit 318 is intended to provide another battery protection signal, the BPRT-3 * signal, the function of which will be explained below. This circuit 318 has a voltage comparator circuit 334 which provides a hysteresis effect. These circuits are known in the art. Such a circuit is indicated in the National Semiconductor Linear Data Book ¢ 1980) paragraph 529. Its function is to compare a fixed voltage with the battery voltage and to output a logic signal with respect to a high and low voltage level. This circuit 334 is connected at its output to a logic level shifting circuit 338. At the junction of one of the interconnections 352 between the two circuits 334 and 338 (which is also the voltage source of the battery) is a 5.49 K ohm resistor 340. The other end of resistor 340 is connected to the anodes of the two diodes 346 and 342. One diode 346 is connected to the other terminal of the voltage comparator circuit 334 and the other diode 342 is connected to the logic level circuit 338. The function of this resistance-diode combination will be explained more fully below. Battery level sensing circuit 42 is supplied with power through a connection to the SYS line 158 and through a filter circuit having an in-series 240 microhenry coil 344. The other end of the coil 344 is connected to ground 80 via a 47 microfarad capacitor 266. This filtered voltage is also supplied to the voltage regulator circuit 160 through a connection between the capacitor 266 and the coil 344 and the resistors 192, 200 and 276 and the capacitor 270.

A communication power supply circuit 316 (Figure 6) can now be considered part of the overall system. A one-to-one transformer 208 is connected to a side of a coil 210 to a side of a capacitor 212 and to the pin 8 of a voltage doubler 214. The voltage doubler 314 is in fact a switching regulator which can, for example, have an ICL part number 7660. and which is connected in a manner known in the art. Thus, a diode 216 is connected to the positive side of a polarized capacitor 218. The other side of the capacitor 218 is connected to the pin 2 of the doubler 214. At the junction of the diode 216 and the capacitor 218, the anode from a diode 220 connected in turn 40 to the positive side of a polarized capacitor

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ij V "Λ» ·· <-j 1 «* 13 222. The negative side of this capacitor 222 is connected to pin 5 and pin 3 of doubler 214, and to the negative side of polarized capacitor 212 as well as the one side of the second coil 224 and the one-to-one transformer 208. The other side of the coil 224 is connected to ground 80. The negative side of capacitor 222 is connected to the positive side of a polarized capacitor 226. The negative side of the capacitor 226 is connected to the anode of a diode 228, the cathode of which is connected to the pin 5 of a power reversal circuit 220. The power reversal circuit 230 may again be a chip such as an IC 7660 which is connected to the Thus, a capacitor 232 may be connected across pins 2 and 4, while pin 3 of the inverter 230 is connected to pin 5 of voltage doubler 214.

Voltage is supplied to this circuit through 15 provided by the voltage regulation circuit. This circuit provides at its output across capacitors 222 and 226 the voltages + Vcomm and "vC0MM> ie 10661 will be fully explained below.

The computer 20 also provides a signal indicating that the battery 76 is about to lose its power. This BA.T low (ΒΑΤ-LOW) signal is provided by the battery low circuit 292 (Figure 5). Power is supplied to a voltage comparator 294 through a filter consisting of a coil and capacitors 344 and 266.

A 5.49 K ohm resistor 296 is connected at one end to the power source (filtered SYS) and to the two anodes of the connected 1N914A diodes 298 and 300. The cathode of one diode 298 is connected to the output of comparator circuit 294. The cathode of the other diode 300 is connected to the base 302 of a 2N2222A transistor 304. The base 302 is connected to ground 80 through a 5.49 K ohm resistor 306. The emitter 208 is forbidden with ground. The voltage Vggg is applied to the collector 312 via a 5.49 K ohm resistor 310.

The collector provides the BAT layer signal.

The battery layer circuit 292 differs from the battery protection circuit 318 in that the battery layer circuit 292 provides a status indication of the battery 76 at a relatively higher level of voltage. The resistor-diode combination 340, 346, 342 of the battery protection circuit 318 operates in much the same way as the resistor-diode combination 296, 298, 300 of the battery-low circuit. When comparator circuit 334 or 294 is at logic 40 high level, it biases its associated output diode 346 or 298 14 thereby decoupling comparator from logic shift circuit 338 or transistor circuit 304. This decouples voltage levels from logic circuit of those in the comparator circuit. Therefore, the flip-over point of the comparator does not depend on logic levels.

The power is turned ON by closing the user's on / off switch 84 (Figures 3, 6, 7). The voltage from the primary battery 76 of the battery 34 or the charging circuit 37 is applied to the protection circuit 52. The voltage applied to the RC charging paths 70 and 72 (Figure 3) is applied to the RS flip-flop 94 and the NAND gate 98 applied to provide a power-in signal to line 128. As a result, the relay 134 (Figures 4 and 7) closes. As a result, Vgyg is supplied to the battery level sensing circuits 42, the voltage regulator 36 and the communication power source 316.

When the voltage of the primary battery 76 is allowed to drop to a predetermined value, the comparator 294 will pull from the bat layer circuit 292 and output the BAT layer signal to a liquid crystal display (IfiD) on the keyboard to display the data. -20 to warn the user.

When the voltage of the primary battery 76 decreases even further, the comparator 334 of the battery protection circuit 318 will be drawn, causing the logic level circuit 338 to output the signal BBPRT-3 * to the protection circuit 52. This signal, a logic high level, is applied to the series circuit of resistors 122 and 124 (Figure 3) across the base 88 of transistor 90. As a result, transistor 90 is turned ON. The voltage drop at the collector 104 causes the RS flip-flop 94 to change state, opening the relay 134. The opening (off) of relay 134 terminates the SYS voltage and VrEG voltage thereby shutting down the computer 20. It should be noted, however, that before the computer 20 turns off, the voltage across the coil 132 of the relay will reverse (and subsequently decrease), turning on the transistor 142 and outputting the signal BPRT-1 * 35 to the bubble control circuit 244. A finite period of time is required for the voltage to drop and thereby open relay 134. This time period is sufficient for the bubble memory driver 244 to perform a proper shutdown of its operation. The shutdown by the control circuit 244 forms an intrinsic function of the control circuit 244.

83 02 2 9 0 »> 15, The presence of the RS flip-flop 94 avoids a logical problem. that would occur if the BPRT-3 * signal were applied directly to the relay driving circuit 90. Once the BPRT-3 * signal succeeds in turning the computer OFF, the battery-5 driving power will be removed from the battery protection circuit 318 (Figure 7) and the BPRT-3 * signal will be lost. Logically speaking, when the BPRT-3 * signal is removed, the relay 134 switches ON. A "hiccup (motor boating)" oscillation will then result. The RS flip-flop 94 serves as a memory means to prevent this phenomenon. Once collapsed into a state, flip-flop 94 will maintain that state even after the supplied or "flip" signal is removed. Therefore, when the BPRT-3 * signal is applied to the flip-flop 94, the relay 134 is turned OFF and remains OFF.

When the power is turned ON, it is clear that the battery-low circuit 318 will initially see a battery voltage below the desired threshold and will output the BPRT-3 * signal.

As a result, two signals are applied to the RS flip-flop 94. A power reset signal is generated by the closure of the switch 84. A BPRT-3 * signal indicates through the transistor 20 90 the protection status of the battery. The first signal closes the real 134 and the last signal opens the relay 134. Obviously, this conflict between the opening and closing signals creates a logical ambiguity. Gate 98 resolves this ambiguity. With the power supply to IN, a low-value signal will be directly supplied from gate BC 70 and 25 72 to gate 98.

This output ensures that the relay 134 is turned ON regardless of which signal comes from the RS flip-flop 94. This signal remains on for the SC time constant of the resistor capacitor network 70 and 72. When the BPRT-3 signal remains on after the constant 30, there is a legitimate reason for the presence of the battery protection signal. When this condition occurs, relay 134 will be turned OFF as noted above.

An important aspect of the circuit is its extraordinary efficiency. It is noted (Figures 3 and 7) that when the user's switch 84 is OFF, there is actually no power-taking circuit connected to the battery 34. The protection circuit 52 is the only circuit connected to the power side of the power supply on the relay 134 and is separated from ground by the user switch 84. Therefore, contrary to what is valid for all known power systems, this computer does not consume any power or no power at all, until it is called up.

In the preferred embodiment, the bubble memory 32 within the computer 20 is used as the equivalent of a disk drive. The computer 20 uses memories for various reasons, as will be explained in more detail below. The bubble memory 32 may be under the control of a bubble memory control circuit 244. This memory 32 is used in conjunction with a read / write memory 246 which is preferably a RAM.

During operation of the computer 20, the bubble memory 32 10 requires a voltage of 12 V to operate. This voltage is obtained when the computer sends a bell-in (BUB-ΟΝ) signal to a relay (not shown), which causes the relay arms 54 and 56 to move in contact with the contacts 60 and 64, respectively, causing the batteries 48 and 76 are placed in series. The series voltage 15 is then fed through a voltage regulator 322. This regulator 322 can be of known construction. The regulated voltage includes vSPOEL *

As indicated previously, when the CPU 38 requires the bubble memory 32, it will issue a bell-in signal. Switching ON the bell-in transistor (not shown) causes a current flow through a relay coil (not shown) of the relay 58, as a result of which this relay will close. When the relay 58 is turned ON, the luminaires 54 and 56 respectively move from one fixed contact 62 and 66 to the other fixed contact 60 and 64, respectively. When the system is IN, the voltage V ^ gg provides power to the bubble memory driver 244 and the bubble memory 32. In addition, the second battery 48 is placed in series with the primary battery 76, thereby providing VgpoEL for operating the bubble memory 32. When the use of the bubble memory 32 is completed, the CPU 38 turns the bell-in signal off and the bell-in transistor will turn OFF. Relay 58 will turn off, bringing relay arms 54 and 56 to their original positions. As a result, the battery 48 is placed parallel to the battery 76. As will be explained more fully below, the use of the bubble memory 32 is limited in duration, thereby saving the life of the batteries 48 and 76.

Any suitable power source can be used. Preferably lead acid batteries are used in view of the relatively constant voltage during discharge and in view of their relatively low cost. It is known that once a lead acid battery 'O;' ". - · ,.

ς. * * - 17, is discharged beyond a certain point, it becomes damaged and cannot be recharged until its previous potential, as a whole.

In order to control the recording from these batteries 48 and 76, the battery sensing circuit 42 is provided. When the primary battery 76 reaches a first predetermined level, the MT low signal is provided by the power distribution system, which signal lights an LED 250 (Figure 2) on the keyboard 28. When the BAT layer signal is provided to ignite an LED on the keyboard 28, there is approximately half an hour of battery life remaining. At the end of this half-hour period, the voltage will reach a second predetermined level. In response to this voltage, the system operates as indicated above to turn the computer 20 OFF.

When the correct power is supplied by the batteries 76 and 48, the power supply supplies the voltage through the voltage doubler 214 and the reversing circuit 230 thereby increasing the voltages

VcOMMf and VCOMM- are obtained. These power sources are provided to a communication interface 256 such as a telephone or the like. This hardwired input / output device is preferred 20 so that the information processed by the computer 20 can be transferred by telephone or the like to another computer 20 or to an office station as will be more fully explained below.

As a general overview of the operation of the computer 20, the GPU 38, when turned ON, will provide instructions from a fixed memory,

25 which is preferably an EPR0M 242. The instructions in the EPR0M. 242 are used to transfer instructions from the bubble memory 32 into the RAM

246 to read. The bubble memory 32 is used to pursue or simulate a disk drive allowing the user to program the computer 20 with application programs (e.g., Super-30 calc, Wordstar, etc.). For the purposes of this discussion, it is assumed that no application programs are in use, that is, it is assumed that the computer 20 is only running its operating system program.

More specifically, the CPU 38 is preferably a Zilog Z-80L 35 CPU. Signals are applied to a memory encoder and page switching circuit 258 (Figure 8). The interconnection of the CPU 38 and the memory circuit 258 as well as the design of the circuit 258 are known in the art and can be determined with reference to the TI TTL Data Book and the Z-80 Technical Manual.

The EPROM 242 can be, for example, a 27C32 memory of National Se-83 0 2 2 9ff 18 miconductor. Its interconnection within the computer 20 can be derived from the product specifications. The EPROM 242 loads the operating system into the RAM 246 by operation with the CPU 38. The RAM 246 is preferably a 64 K byte unit provided by Motorola (part number 5 6665A). The RAM 246 is daisy chained to the computer 20 in standard configuration, referring to the product specification sheet, the TI TTL Data Book, the Z-80 Technical Manual and the Zilog Applications Handbook. The EPROM 242 preferably has an 8 K capacity. At the time when the CPU 38 turns ON, the RAM 246 and the EPROM 10 242 are authorized by the memory encoding page switching circuit 258. The memories of the EPROM 242 and the RAM 246 are preferably selected to have an operating speed in similar to that of CPU 38 to simplify interconnections.

The bubble memory 32 is forced under the influence of the instructions received from the CPU 38 and the EPROM 242 to read instructions to the CPU 38 by the bubble control circuit 344 and, consequently, to the RAM 246. Preferably, the bubble memory 32 is a 7110 memory from Intel Magnetics and the bubble memory driver is an Intel Magnetics 7220-1. The interconnection of the bubble memory 32 and the bubble memory driver 244 to the computer 20 is shown in the Intel BPK-72 User Manual.

The interrupt or interrupt control circuit 242 is known. At the heart of such a unit is a 4532 Motorola priority coding circuit. The interconnection thereof to the computer 20 including affected circuits is found in the Motorola CMOS Data Book and the Z-80 Technical Manual. These interrupts are monitored by the CPU 38. One of the interrupts can come from a keystroke delivered via the keyboard 28.

The keyboard 28 is one that is readily available from 30 HiTek, Ine. The keyboard control circuit 248 can be obtained from Intel, part number 80C49. The control circuit 248 includes a programmable microcomputer. It is programmed to recognize the keystrokes and to issue predetermined codes to the CPU 38. In order to accomplish this data transfer, the keyboard 28 can send an interrupt signal to the CPU 38. The CPU 38 responds to the interrupt and the keyboard information is then fed to the CPU 38.

The timing of the computer is obtained by means of a clock 254 which, for example, emits a frequency from a 40 4.9152 MHz oscillator. The circuits for the clock are easily available 83 0 2 2 9 0 r * γ 19. Preferably a Frequency Control Products 9101-02 can be used which can be installed according to the product specification sheet and the Z-80 Technical Manual. The clock 254 generates a clock signal for the CPU 38, for the interrupt control circuit 252, the RAM 246 and the office station interface 22 as well as for the communication interface 256.

It is possible that interrupt control circuit 252 will receive a number of interrupts from different sources. The interrupt control circuit 252 determines the priority of each interrupt when they are received.

As previously indicated, the computer 20 uses a bubble memory 32 configured as a disk or disk drive, e.g. drive A, and which is preferably adapted to apply CP / M nomenclature. Preferably, a 128 K bubble memory is used.

When the power distribution system 46 provides power to the computer 20, the power provides a power reset circuit 262 which is a known circuit. As a result of this power supply, the power reset circuit 262 provides a release 20 (CLR) signal which is applied to the keyboard driver circuit 248, the office station interface 22, and the communication interface 256, the bit addressable control port 348, as well as the CPU. 38, the keyboard control circuit 248 and the keyboard 28, the interrupt control circuit 252 and the bubble memory 32 and the bubble memory control circuit 25 244. The pulse width of the CLR signal may be approximately 500 milliseconds to ensure the IN circuit of the computer 20.

The system includes an input / output encoding circuit 264 which authorizes, for example, an ICD interface 260.

The input / output encoding circuit 264 is a well-known circuit whose design can be derived from the TI TTL Data Book. The LCD is preferably a four-line by eighty-character (4 x 80) display available from Epson America. The LCD interface 260, also provided by Epson America, is daisy-chained for display purposes in accordance with the TI TTL Data Book and the Epson America product specification.

As mentioned previously, a communication port interface 252 is provided so that the computer 20 can communicate with other equipment by telephone or other means. The interface 252 preferably includes a 6402 UART from RCA. It can be installed under 20

,, * fit of the procedures and involved parts indicated in the RCA

CMOS Data Book, the Z-80 Technical Manual, the Harris CMOS Data Book and the EIA Specifications No. RS232C.

The keyboard 28 is preferably organized in rows of a 16 column matrix with discrete shift, slide lock, capital lock and control keys. The slide lock and capital lock keys are preferably electronic lock keys with LED indicators indicating that the capital lock and slide lock positions are in operation. The master-10 letter lock key works in a usual alternate manner while the slide lock key locks only in a slide lock position. All of the above is known in the art.

Preferably, the keyboard 28 employs a two key roll over operation. The keyboard 28 is scanned and its operation is known in the art.

The computer 20 described so far is a programmable data input device with a keyboard input / output with a 4 x 80 display. However, this computer 20 has the ability to use not only with peripheral devices (ie devices externally to the computer) but can adjust its operation to these peripheral devices, including those manufactured at the time this computer 20 was manufactured. was not yet known, to accommodate. As mentioned earlier, the computer 20 is connected to an office station interface 22. This interconnection can be effected via 74SLS45 buffers 25.

The guiding principle behind the office station interface 22 is the use of modules (not shown). These modules provide the portable computer 20 with all the necessary tools to support peripherals and their functions. In particular, each module has a program store which can be in the form of an EPR0M. This storage is used to hold the drive program, program connection information, diagnostic programs, and device identification data necessary to operate the peripheral equipment.

The RAM required to support a cost effective module operation, ie buffer space, is also introduced into the system by the module.

The computer 20 uses a page mechanism to enable the EPR0M and RAM in each module to overlay or overlay the main computer RAM 246.

40 When the CPU 38 is turned ON, the EPROM 242 is authorized.

O ™ Λ 21

The GPU 38 takes its instructions from the EPROM 242 and the bubble memory 32 (ie "boot" program) to the RAM 246. Some of these instructions investigate the office station interface 22.

The purpose of this investigation is to determine whether or not random peripherals are attached to the office station and to their attributes and capabilities.

This research is accomplished in the following manner. Each module can be provided with a unique code. This code can be applied in any known manner and is preferably entered by setting the state of a set of eight (not shown) switches present on the module. During the execution of the survey, a specific I / O instruction is issued by the CPU 38 on a per module placement basis. All modules receive and compare the code issued by the CPU 38 with the code set on their respective switches. An equality between the two codes on any module causes this module to transition into an authorized state once. When a module is in the authorized state, this module has the ability to cover or overlay the computer EAM 246 (overlay). This is accomplished by means of a memory enable withdrawal signal from the module to the memory encoder 258. After initialization is completed, each time a module is to be used, its specific authorization address (ie the state of the eight switches) ) used.

During initialization, it may be desirable to develop a table of operating characteristics of a module. This can be accomplished by copying from an authorized module memory (i.e. from the overlapping area) into the non-overlapping area of the RAM 246.

Upon receipt of the memory authorization takeout signal, the memory encoder 258 will remove the authorization of the RAM 246 in the pre-designated area, which may range from, for example, 4000 to 8000 in hex. A module that values this signal is required to provide data from its own memory to the RAM 246 during this time. This causes an overlap of that module's memory over the RAM 246 in that range (that from 4000 to 8000 can walk). The state of the CPU 38, i.e., reading or writing, requires the authorized module to control the direction of the buffers 350 (Figure 8). The modules carry out this direction control with a signal that can be indicated with DIR.

40 The memory authorization withdrawal signal is generated by the modules in the following manner. Each module has a memory coding circuit (not shown) which decodes the state of the CPU 38. When the module coding circuit detects activity by the CPU 38 in the overlap region and the module is authorized, the module's memory coding circuit then generates the memory enabling path for the memory coding circuit 258 of the computer 20. Upon receipt of the authorization take-away signal, the memory encoding circuit 258 removes the authorization from the RAM 246. Simultaneously, the module initiates its own memory cycle and authorizes data 10 on the data bus of the CPU 38.

To remove authorization from the module, the CPU 38 issues the same I / O instruction with a different address (i.e., an address directed to another or no module). The module receiving this different address decodes this phenomenon and replies thereto the authorization. Modules with removed permission are prohibited from overlapping RAM 246.

The investigation is accomplished by successively attempting to overlap the RAM 246 with the memory of each module. In the memory of each module, peripheral identification message and program input points are provided. After the module has been authorized due to the identity of the switching codes, the CPU 38 acknowledges the device identification message. The program entry point information is used to run each initialization program unique to the module and to determine its identity and attributes. Nonexistent modules will not overlap the RAM and therefore will not generate an identification message.

An alternative to using specific addresses on each module with associated switches is to include each module in a "daisy chain". In such an arrangement, the authorization or initialization process does not apply a specific address for each module.

Each module may have a daisy chain circuit 352 (Figure 9) consisting of a reversing circuit 354 connected to the D input and the release input of a bistable flip-flop 356. The clock input of the flip-flop 356 is connected to an input of each of two CF gates 358 and 360. The Q output of the flip-flop 356 is connected to the second input of one of the CF gates 358 and the Q * output is connected to the second input of the other OR gate 360.

The input of each inverter 354 of each module is connected to the inputs of all other inverters 354 of the other

S 3 0 2 2 9 Q

23 re modules and with the DEV EN * (for "device enable") output from the computer 20. The signal applied to the clock input of the flip-flop 356 is identified as DEI * (for "device enable in"). The signal from the first OR gate 358 is identified as BD EN * (for "board 5 enable"). The signal from the second CF gate 360 is identified as DEO * (for "device enable out"). The DEO * signal line is connected to the DEI * input on the next module in the sequence The BD EN * signal upon receipt activates the memory on that module as indicated in the initialization and operation as mentioned above.

When operating the daisy chain, the computer 20 provides two signals to the office station interface 22 (containing the modules): the DEV EN * and a DEV CLK *. In the arrangement adopted for this explanation, DEV EN * and DEV CLK * are "active" when they are logically low and they are "inactive" when they are logically high. When DEV EN * 15 and DEV CLK * are inactive, the modules are all in the inactive state. That is the first state to be obtained for the computer 20 to address a desired module. To select a desired module, the DEV EN * signal must be activated. After this is done, the computer 20 provides an active DEV CLK * signal. A 20 counter in the computer 20 will determine from which module it is required to be activated. When the first module is not desired, the computer 20 causes the DEV CLK * signal to go into idle state and then make it active again. The first module has been inactive and the second module is now active. During this period, DEV 25 EN * is active. If another module is desired, the process continues until the computer 20 counts down until the desired module is reached.

All modules are subsequently questioned during initialization. During operation, the modules are counted down the daisy chain until the desired module is reached.

During the operation of the computer 20 and any module associated with the office station, the readily accessible memory when used must issue a BUSRQ signal (bus request) to the CPU 38. The CPU 38 will send a BUSAGK signal ( bus acknowledge). At that point, the module can use its direct memory access (DMA.) Capability. This is known in the art as shown in the Z-80 Technical Manual and the Zilog Applications Handbook.

During the general operations of the computer 20, a lock is provided when the CPU 38 "writes". For example, when it is necessary to control the bubble memory and to provide the required power, the CPU 38 therefore writes to this bit address 8302290 24, sable control port 348, which may be, for example, a 74LS273 chip, to thereby enable the call-in ( BUB-ΟΝ) signal to the power supply.

One of the peripherals that can be used is a CRT-5 display 26 of 24 lines by 80 characters. A 24 line by 80 mark portion of the rim 246 may be set aside. Information read into the RAM 246 from the keyboard 28 is maintained by the RAM 246 in a manner similar to a CRT display of the same size. The RAM 246 is treated as if it were a CRT 10 for this purpose.

As a result of this approach, the LCD 4 lines by 80 characters display copies the information stored in RAM 246 or rather that part of the information that it can accommodate. This can be done under program control. Therefore, the 4 lines by 80 characters (4 x 15 80) display can be considered a "window" in a 24 lines by 80 characters (24 x 80) "folder" or area of the RAM 246.

In accordance with the teachings of the invention, the keyboard 28 is provided with five keys in addition to the keys normally present on a keyboard. These five keys serve to move the window (ie the 4 x 80 display) around the 24 x 80 area of the RAM 246. There is a unique code associated with each of the five keys. These five keys are referred to by a group of window control keys. A key will jump the window to the top of the 24-line by 80-character memory area. A second key will jump the window to the bottom of the 24 x 80 area. A third key will scroll the window until that window reaches the top of the 24 x 80 area. A fourth key will scroll the window down until the window reaches the bottom of the 24 x 80 area. The fifth key is a "snap" or "house" key that returns the window to its original position. The operation of the fifth key presupposes that, during the operation of each of the other four keys, the window moves not only with respect to not only the 24 x 80 map but also with respect to the cursor. Entering data with the window rolled away from cursor 35 will cause the same "snap" or return.

When in operation one of the five keys is hit, the keyboard control circuit 248 identifies that keystroke as one of the window control keys and stores that information in a FIFO memory located within the control circuit 248 and outputs an interrupt signal 40 to the CPU 38. The CPU 38 then executes an interrupt routine 8302298 25 which is known in the art. After completion of the interrupt routine, the CPU 38 will continue to operate. On the next delivery of a basic input-output system (BIOS) routine (for example, which has to do with the keyboard 28, the bubble memory 32, or the LCD 60), the CPU 38 checks the FIFO memory in the keyboard driver circuit 248. When a window control signal of one of the five keys is found, that signal will be output by the CPU 38.

If a character is ever displayed on the 4 x 80 display, it is also stored in RAM 246. At the same time, the keyboard driver circuit 248 causes the window start point to be stored in the RAM 246. This information, called "pointer", is stored. In addition, when the window is moved or rolled, a second pointer is stored in the same manner to indicate the window position.

When the house or snap key is pressed, the CPU 38 identifies the window pointer corresponding to the location of the window when the cursor was last displayed and the window pointer corresponding to the current location of the window. When these two pointers are different, the CPU 38 returns the window to the original location. This is also done when a character is entered and the window is moved to a different location from the cursor.

As part of its operation, the 4 x 80 display can be coordinated with a 24 x 80 display from a CRT monitor. This can be done by starting the characters in the 24 x 80 display in the same place as in the 24 x 80 display. Synchronization between these two views can be maintained by the one-to-one ratio of the storage area to the CRT view. As a result of the 4 x 80 display, it will display a coordinated though smaller portion of the CRT display.

It will be understood that within the scope of the specification and claims an assumption has been made regarding the polarity of the power supply (where ground is the negative terminal of the primary battery) and the circuitry including the chips and the discre -35 transistors are connected in accordance therewith. However, the entirety of the description and claims should be read so that the inverse logic polarity and circuits thereof are also within the scope of the invention.

After the following claims, a print-out 40 of the source code of the operation of the drive programs for the 26 ICD display is indicated. keyboard according to the aforementioned.

It is noted that the LCD display is one of many types of displays that can be used. It is also noted that the number of lines selected for the display device 30 may be any number 5 provided that it is less than the number of lines of the display on the monitor where the display is coordinated with the read / write memory means of the computer so that it is coordinated is with the CRT display or at the time of initial input or some time later when the CRT is connected to the computer. Therefore, the 4 x 80 10 display device 30 may also be an 8 x 80, 12 x 80 or the like display device.

8302290

Claims (92)

The computer of claim 1, wherein the keyboard has means to provide an order to the CPU to cause the "window" to scroll to the top of the simulated view; an order to cause the CPU to roll the "window" to the bottom of the simulated view; an order to scroll the "window" up one line of the simulated view; and an order to cause the "window" to scroll down one line of the simulated view. The computer of claim 2, further comprising means for displaying a cursor for placing characters within the 1/0 display; wherein the window when scrolling through the scrolling orders moves relative to the cursor; the keyboard having means to issue a "house" order such that the window, when moved from its original position relative to the cursor by one of the scrolling orders, is returned when the "house" order is executed to the original position. The computer of claim 3, wherein the scrolling order is executed by the CPU, wherein indicia of the position of the window are stored in the scrolling position by the CPU in the read / write memory means; wherein the CPU stores indicia in the read / indicia in the read / write memory means which indicates the position 40 of the window relative to the cursor for the scrolling order v .... ----- V; wherein the CPU, when executing the "house" order, determines whether there is a difference between the indications of a rolled position and the cursor position of the window and, if this difference exists, returns the window to its cursor position. The computer of claim 4, wherein the 1/0 means further includes memory means, the keyboard outputting keystroke signals, the scroll and house orders predetermining certain window control signals which are distinguishable from all other keystroke signals, which are output from the keyboard are stored in the 10 memory means of the I / O means. The computer of claim 5, wherein the 1/0 means includes keyboard control means including the memory means connected to the CPU, the keyboard control means delivering an interrupt or interrupt signal to the CPU upon the output of the window keystroke signal. 7. The computer of claim 6, wherein the CPU in response to the interrupt signal outputs the control signal by selectively triggering readings from and to the simulated display thereby moving the window relative to the cursor. The computer of claim 7, wherein the window indicia comprise indicia indicating the position of the start of the window and named "pointer" indicia. 9. The computer of claim 8, wherein the keyboard control memories comprise a first-in / first-memory, and the read / write memory means comprises a BAH. The computer of claim 9, wherein the command location comprises 24 lines by 80 characters and the window comprises 4 lines by 80 characters. The computer of claim 9, wherein the commanded location comprises 24 lines by 80 characters and the window comprises 8 lines by 80 characters. 12. The computer of claim 9, wherein the command location comprises 24 lines by 80 characters and the window comprises 12 lines by 80 characters. The computer of claim 9, wherein the I / O display is an LCD display. 14. Computer that can be connected and interact with a number of peripherals, each connected to a modular unit, 40 which computer includes one. a) a CPU within the computer; b) read / write memory means within the computer operatively connected to the CPU; c) fixed memory means within each of the modules and operably connectable to a peripheral and the CPU, which fixed memory means has instructions therein to initialize at least the peripheral; and d) means within the computer operatively engaged by the CPU and each of the module hard memory means to selectively connect the CPU 10 to predetermined means of the hard memory means rather than places in the read / write memory means to initialize the peripheral and operate. 15. The computer of claim 14, wherein the module further includes means for providing a memory authorization takeout signal, wherein when the connection means engages the module of fixed memory means, the issuing means, upon subsequent reference by the CPU to the sites, outputs an authorization takeout signal to the read / write memory means of the computer to thereby remove the permission for the read / write memory means and to obtain the CPU instructions from the fixed memory means as if these fixed memory means were the read / write memory means. The computer of claim 15, wherein the replacement of the read / write memory means by the fixed memory means thereby causes a page operation in the fixed memory means instead of the read / write memory means. The computer of claim 16, wherein the providing means has a module memory encoding circuit. The computer of claim 17, wherein each module has means to establish a unique code, the CPU thereby issuing the code for one of the modules thereby authorizing this module and causing the memory coding circuit to output the memory enable take-away signal. 19. The computer of claim 18, further comprising a computer memory encoding circuitry within the computer and connected to the module memory encoding circuit, wherein the computer memory encoding circuit, upon receipt of the memory enabling take-down signal from the module memory encoding circuit, outputs a signal for the authorization of the read / write memory means. to dispel. The computer of claim 19, wherein the hard memory module has a predetermined memory size and corresponds to: the memory size in a predetermined location of the computer read / write memory means, the hard memory module having the same size and a page operation instead of the place in the read / write memory means. The computer of claim 20, wherein the unique code comprises a series of switching means, each of which provides a combination of IN / OUT states unique to said module, which switches connect the fixed memory means and the module memory coding circuit to the computer. The computer of claim 21, wherein the series of switches provides a unique identification code that authorizes the module upon receipt from the CPU. The computer of claim 22 further comprising first fixed memory means connected to the CPU having at least instructions 15 therein to operate the computer, wherein when the computer is turned ON it provides the instructions of the first fixed memory means to the CPU for storage in the read / write memory means and for the CPU to interrogate each of the modules with said codes. The computer of claim 23, wherein the CPU, at said interrogation, issues one of the codes corresponding to the code of one of the modules thereby authorizing said module, the module memory means therein providing device identification messages and program entry points wherein, upon issuing the authorization code, the CPU acknowledges the device identification message, wherein the module provides fixed memory means necessary for operation, from the peripheral to the computer for storage in the read / write memory means outside the overlapping area. The computer of claim 24, wherein the first fixed memory means includes at least one EPROM which upon initialization issues each said code to all module switches and memory coding circuits simultaneously, each code comprising 1/0 instructions, each module comprising fixed memory means a drive program , program connection information, diagnostic programs and device identification data to operate the peripheral device, the CPU issuing the I / O instructions to all modules following initialization, which I / O instructions removes the authority from all fixed memory modules except the module which uniquely series of switches with the code mentioned. The computer of claim 1, further comprising a CRT monitor and means for connecting the CRT to the CPU, the Tj 0 display having the ability to display characters in the same character locations per line as the CRT. view when the window scrolls relative to the simulated view. The computer of claim 26, wherein the I / O display has at least one dimension (character width or total lines) identical to the CRT display. The computer of claim 27, wherein the I / O display has four display lines. The computer of claim 27, wherein the I / O display has eight display rules. The computer of claim 27, wherein the I / O display has twelve lines of display. The computer of claim 27, wherein the simulated display 15 has the same size and dimension as the CRT display. The computer of claim 2 further comprising a CRT monitor and means for interconnecting the CRT to the CPU, the If 0 display having the ability to display characters in the same character locations per line as the CRT display when the window is at relative to 20 of the simulated view. The computer of claim 32, wherein the I / O display has at least one dimension (character width or total lines) identical to the CRT display. 34. The computer of claim 33, wherein the I / O display has four display rules. The computer of claim 33, wherein the I / O display has eight lines of display. The computer of claim 33, wherein the I / O display has twelve lines of display. The computer of claim 33, wherein the simulated display has the same size and dimension as the CRT display. 38. The computer of claim 4 further comprising a CRT monitor, and means for connecting the CRT to the CPU, the I / O display having the ability to display characters In the same characters per line as the CRT view when the window scrolls relative to the simulated view. The computer of claim 38, wherein the I / O display has at least one dimension (character width or total lines) Identical to the CRT display. The computer of claim 39, wherein the I / O display has four lines of display. The computer of claim 39, wherein the I / O display has eight lines of display. The computer of claim 39, wherein the I / O display has twelve 5 lines of display. The computer of claim 39, wherein the simulated display has the same size and dimension as the CRI display. The computer of claim 9, further comprising a CRT monitor and means for connecting the CRT monitor to the CPU, the I / O display having the ability to display characters in the same character locations per line as the CRT view when the window is rolled relative to the simulated view. The computer of claim 44, wherein the 1 / O display has at least one dimension (character width or total lines) identical to the CRT 15 display. The computer of claim 45, wherein the I / O display has four display lines. The computer of claim 45, wherein the I / O display has eight display lines. The computer of claim 45, wherein the I / O display has twelve lines of display. The computer of claim 45, wherein the simulated display has the same size and dimension as the CRT display. ********* 83 02 2 i »ü f —1— 1 ^ -« {· -r ^ j. J | ix ·}. 5 · ~ ^ * (• - «'' '· π. SUUPCE STATEMENT nj ^ SJ';: - '· 1 * H LüD MODULE o' i HlSTuRY 4; 11/18/82 changeAwindow up / down 5; * '6; 10/25/82 7; 10/20/82 Ö; 10/19/82 FIX IT 9; 10/18/82 CONVERT FROM PLZ 10; 11 cr equ Odh 12 If equ Oah 18 esc equ Ibh 14 bs equ 8 15 els equ lah 16 bell equ 7 17 cup equ Obh 18 cur equ Och tv chm equ leh 20 newln equ 1 fh 21; 22 maxrow equ 24 23 maxcol equ 80 24 scrsize equ maxrowsmaxcol 25 savret defs 2; save return addr for wrlcd 26 j 27 global lcdcon ledsta exicdr nullout nullinp 28 global dried 2v> 30 external cury curx cursor toplcd last * t selcfl esefig 31 external DEF8TA screen keyent keydir ledkey t-chain 32 external keyemd kvalue BREAK -. wC «1 tjt vs da fiiv: · 34 tnecmd defb 6 004 οι Tf '*. **}' X 36 def-o 1 07 O / # 38; 89. Revision history 40. date comments 41; 42} 820622 Changed LCD cursor to blinking block. 43. Added mpy80 for .i nsertel i ne and deleted 44 »820614 Initial release. 45 1 46 global upled setcur wrlcd 47 global mov scroff fill mpy80 outlcd 43 49 * ï BIOS. DEF. 8 227 «-LIST ON 223 229 i 230. setcur 231. plz call: 232. set cursor to position specified by curx * cury \ 233 i setcur procedure 234 asm call: - 235} call setcur 83 ^ 2 2 9 0 ♦ - 2— LCIi MUUUI.-I :: L '-'- D i - LU * / * <ïB, l COiifi <i' - - t '·: i'. TL i Ifi NT "0005 3A0000 X 237 setcur ld ai (toplcd); cursor wi t, ui u range of led 0008 4F 238 1 d Ci a 0009 3A0000 X 239 ld (cury) OÖÖC 91 240 sub c OoOD 6F 241 ld ba * OOOE 380A 242 yr Ci nocur i cursor nol- on display 0010 FE04 243 cp 4 0012 3006 244 jr nci nocur; not on display 0014 3A0000 X 245 ld a, (curx) 0017 5F 246 ld e, a 0013 lö04 247 yr setc OOIA 2E0Ö 248 nocur ld 1 »O 00IC 1E50 249 ld e» 80; place off of display 001E 3E0E 250 setc ld ai Oeh; turn cursor of f in all segmer 0020 OEI3 251 ld ollcU 0022 COEFOO R 252 call outlcd 0025 OEI A 253 ld c, 12 cU 0027 CDEFOO R 254 call out LCD 002A 0E1C 255 ld c, 13c tl 002C CDEFOO R 256 call out LCD 002F 0E1E 257 ld o 14ctl 0031 CDEFOO R 258 call out LCD 0034 7B 259 ld a. e 0035 325001 R 26-0 ld <lcdx) »ai set led cursor addr 0038 7D 261 ld ai 1 .0039 325101 R 262 ld Uedy), a 003C '7B 263 ld ai ej construct set cursor cmd 003D 0E18 264 ld Cillctl; construct io addr 003F FE2Ö 265 cp 40 0041 3804 266 - j r Ci rights 0043 OU 267 inc c 0044 OC 268 inc e 0045 D623 269 sub 40> right half of line 0047 CB45 270 rights bit Oil ·; first or second line? 0049 2802 271 yr z, first 1 0043 CBF7 272 set 6i a; second line 004D CBFF 273 firstl set 7i a; signify set cursor cmd Ö04F CB4D 274 bit 11 1 »third or fourth segment? 0051 2804 275 yr z> firsts; no 0053 OC 276 inc e; yes <add 4 to io addr 0054 OC 277 inc c 0055 OC 278 inc e 0056 OC 279 inc c 0057 CDEFOO R 280 firsts call outlcd; set cursor 005A 3E0F 281 Id ai Ofh j turn cursor on 005C C3EF00 R 282 jp outlcd 283 i 284. wrl cd 285. write single char to led 286. pi z call: '287. wrlcd procedure (eh: byte) 288. asm call: 289> Id lich iascii char to write to led 290. push hi \ 291; call wrlcd 292. i \ 2 '.' 3; cursor position after this command is undefined \ g 3 η o 9 a n V -3- l „i Μ MODULE LCD UAbfc: Η». ' ill :. I ι.Ί.ιϊιΙ. ". i A H-.Hr.M! A ';: h 5. 9 “H * i 005F uDobOO R: jv5 wried cal). hour Jset cursor position 0062 El 296 pop hi »return addr 0063 Di 297 pop da; e = chsr 0064 E5 298 push hi 0065 Ob19 * 299 Id c, llctl + i; construct io addr 0067 3A5001 R 300 Id a, (Icdx) 006A FE28 301 cp 40 006C 3802 302 jr c, wrl cdl 006E Ou 303 inc c> second or fourth segment Ö06F. OC 304 i nc c 0O70 3A5I01 R 305 wrlcdl Id a, (1cdy); line 1-2 or 3-4 0073 CB4F 306 hit 1.a 0075 2304 307 yr z, wrlcd2 0077 OC 308 inc c; third or fourth segment 3073 Ou 309 inc c X> 79 OC 310 inc e X »7A Ou 311 inc c X) 7B 7B 312 wrlcd2 Id a, e Xi7C C3EF00 R 313 jp out led> write char- 314; 315. upled 316. update entire led starting at line specified by topic 317. plz call: 31.8; upled procedure 319. asm call: 320. call upled 321. cursor position after this command is undefined) 071-3A0000 X 323 upled Id a, (topled)> 082 6F 324 Id 1, a) 083 2600 325 Id h, 0; mpy by 80 (50h>> 085 29 326 add hi, hi> 036 29 327 add hi, hi) 087 29 328 add hi, hi) 033 29 329 add hi, hi, mpy by 1.6> 089 54 330 1 dd, h > 03A 5D 331 id e, 1> U8B 29 332 add hi, hi; mpy by 4 more> 08C 29 333 add hi, hi> 08D 19 334 add hi, de) 03E 110000 X 335 id de, screen; find abs addr of line '091 19 336 add hi, de) 092 0E18 337 Id c, lictl) 094 E5 338 push hi »095 CDB800 R 339 call fillseq swrite out first segment '098 El 340 pop hi) 099 i 12800 341 Id de, 40 O9C 19 342 add hi, O9D E5 343 push hi Ό9Ε 0E1A 344 Id c , 12ctl ΌΑΟ CDB800 R 345 call filleg; fill second segment ΌΑ3 El 346 pop hi oA4 117800 347 id de, 3 * 40; skip to third segment 0A7 19 348 add hi, de ΌΑ8 E5 349 push hi 0A9 0E1C 350 · Id c, 13ctlAB CDl-iSOO H 351 ca iifi H s eg; f i i 1 t h i r d s egm en t 3 0 2 2 9 0 -4- L CL * MODULE LCD l-'AGL ^ mi v 11! ·! ·.! curiE h:.> lhT yijljl ί & s'l A1 Ehl: Μ i ASM 5 v "l-'OE El 352 pop hi OOAF 11.2800 353 Id de, 40 0082 19 354 add hi, de 0ub3 OE IE 355 ld c, 14ctl 00155 C3B800 R 356 jp fillseg; fill last segment 357 j * 358. fillseg 359> fill specified led segment with data 360. reg c, = io addr specifying segment 361. reg hi = ptr to character string 362. call fillseg 363 i OOBU 3EQ0 364 fillseq Id a, 30h; home cursor OOBA CDEFOO R 365 “call outlcd OOBD OC 366 inc c.: Point to char io? OBE 0628 367 1 db, 40 OOCO 7E 363 fillsl Id a, (hi); get char 23 369 inc hi 0OLJ> CDEFOO R 370 call out lcd; put on led WL5 10F9 371 djnz fillsl 112300 372 id de, 40; skip second half of line? 0CA 19 373 addhl.de • JOCB OD 374 dec c; fOCC 3EC0 375 Id a, OcOh.fill second line CDEFOO R 376 call out LCD JODI oc. 377 inc c; 0D2 0623 373 Id b, 40 7E 379 fi 1 ls2 Ida. (hi) 23 330 inc hi jon-t CDEFOO R 381 call bulled n '10F9 332 djnz fills2 ίυϋΒ C9 333 ret 334; 385.clrcur 336 .: cl ears all cursors on led 387. no parameters) 0n '333.: p 3E0E 339 cl r cur Id a.Oeh; clear cursor cmd; -> UE 0E18 390 Id c, llctl 'CDEFOO R 391 call outlcd> output led cmd> 0E5? E1A .. 392 Id c. 12ctl CDEFOO R 393 call out LCD .clear cursor in second segment ici 0E1C 394 Id c. 13ctl \ - \ ej CDEFOO R 395 call out LCD; third segment> OELi OEiE 396 Id c, 14ctl 397> *** falls through · # · β *. fourth segment 398? 8 · $ · # · to outlcd # · # · # · C9V J 400 'a 40l; outlcd \ 402; output char or command to led \ 403; c = 10 addr% 404 .; a = data or command * 405; call out lcd 406. all reqs preserved 407; * 0E | - f.g. 403. outlcd push off ^ ED78 409 waitlcd in a. (c) .wait for busy flag off 3. rt v 0 r ή Ό 2 v L -t- v '' J '-5- t; > ·. . :! i! il.iLfc LCD PhC'E 5:. ": · ΧΧ ;. M STMT SOURCE STATE »! f A rl r ,. 9 ΟύΡ ': *: 07 410 r 1 ca OOFS 38FB 411 yr C / wai Tied 0UF5 FJ. 412 pop off '00F6 ED79 413 out <e) / a / Output o.har ÜOFS Cv 414 ret 415 * 41.6; 417. mov 418. move bytes from sre to dest 419. if fields overlap / move is performed 420. so no data is lost 421; 422. calling sequence: 423. mov procedure (sre dest byteptr; len w:: 424; 425 mov X> F9 FDE1 426 pop iy; return addr) OFB Cl 427 pop be; len X> FC D1, 428 pop de; dest> OFD El 429 pop hi; sre) OFE 78 430 1 d a, b> OFF B1 431 or e; cheek for eount = 0) 1.00 2809 432 yr z> retrn) 102 E5 433 push hi) 103 A7 434 and a> 104 ED52 435 sbe hi / de; src> dest? IJ06 El 436 pop hi> 107 3S04 437 yr czback; reverse move> J 09 EDBO 433 ldir 439 retrn> 10B FDE9 440 jp (iy) 441 back ilOD OB 442 dec be Ί0Ε 09 443 add hi / be; find end of string '1 OF EB 444 ex- de / hi 110 09 445 add hi / be J 11 EB 446 ex de, hi 112 03 447 inc be 113 EDB8 448 lddr 115 FDE9 449 jp (iy) 450 451 452 / 453. fill 454. fill memory reqion with specified data byte 455, plz call: 456. fill procedure (ptr byteptr; len word; data byt. 457. asm call: 3 458 1 d hi / [) tr 459. push hi a 460; Id hi / len \ 461; push hi a 462; Id 1 / data% 463; push hi * 464; call fi11 465; LJ7 FDE1 466 fill pop iy; return address 119 D1 467 pop de; e = data μ ϋ ί j «» -6- I! 1 ί; ’i:! 'L. |; _ LLD I "Vi μ; Λ> • i ii i. IL 1' ί ί IΤ BOURSE ST ATEMENT - .: ri -,? 'I, i ί., 1 463 pop be; bc = length (./JIB El 469 pop hi; hl = ptr O) J.Ü FUIL5 470 push iy 011E 79 471 -fillip Id a. E; check -for zero length 01 J.F BO 472 or b 0120 C8 473 ret z j done 0121 73 474 Id (hl), e 0122 23 475 ine hi OI. 23 OB 476 dec be 0124 18F8 477 jr fillip 473 4/9 430, "431. scroff 432. calculate absolute address of char in screen buffer 483. given: <and y coordinates 434. Pi 2 call: 435. scroff procedure (: ·: Y byte) returns (ptr bytef 486. asm cal 1: 437. push hi 488 »1d 1j x 439> push hi 490; 1d 1, y 491. push hi 492. call scroff 493. pop hi> h1-addr of selected char in buffer 494; 0126 1) 1 495 scroff pop de> return addr 0127 El 496 pop hi »y coordinate 0128 2600 497 Id fi, 0 012A 29 498 add hi / hi; mpy by 80 <50h) 012B 29 499 add hi.hi 012C 29 500 add hi, nl OJ. 2D 29 501 add hi, hi 012E 44 502 Id b, h 012F 40 503 Id c, l 0130 29 504 add hi, hi 0131 29 505 add hi, hi 0132 09 506 add hi, oc 0133 Cl 507 pop be; x coordinate 0134 0600 508 Id b, 0 0136 09 509 add hi, be j add in x 0137 010000 X 510 Id be, screen; make it an absolute addr 013A 09 511 add hi , be Ö13B E3 512 ex (sp), hl ireturn parameter 013C EB 513 ex de, hi 013D E9 514 jp <hl) 515 516 517 ί 518. mpy80 519. multiplies operand by 80 (screen wi.dth) 0520 i plz call: 521, mpy80 procedure (y byte) returns (off word) n 522; asm call: u 5:73, push h 1 allocate return space a 524; id 1, y; y = number to be multiplied by A 525; push hi 4 8302290 -7- r LCD MHMliLE 'LCD; : · /. E nC 't:,:. I I. i ij ifc. h: · Γ [ftT \ i! M t Ir hl ·. Ni; · *:! ·. V 526 "tall rpypyö 527. pop h L; hl = y- * 80 528 i 013E F DEI 529 mpy80 pop iy 0140 El 530 pop »hl» 1 = number to be multiplied 0J41 Ci 531 pop be »throw * away return 0142 2600 532 ld h» 0; was a byte value 0144 29 533 add hl »hi» mpy by 16 0145 29 534 add hl »hi 0146 29 535 add hl» hi 0147. 29 536 add hi. hi 0143 54 537 id d, h 0149 5D 538 ld e »1 014A 29 539 add hl» hi 014B 29 540 add hl »hi 014C 19 541 add hl» de Q14D E5 542 push hi 014E FDE9 543 jp (iy) 544 545 »546. local data used by keyboard 547» 0150 543 ledx defs 1 »x position of led cursor (0-79) 0151 549 ledy defs 1» y position of led cursor (0-3) 550; 551; 552 »null input .null input device» always. returns an EOF chara 553 i (lah) 554; 555 nullinp 1) 152 El 556 pop hi »ret> 153 D1 557 pop de> 154 D1 553 pop de» clear ram ptr> 155 0E1A 559 id e »lah .store eof> 157 C5 560 push be> 158 E9 561 jp ( hi) 562 »563» 564. nullout null output device »accept all chars 565. device is always ready 566» 567 null out. 159 El 568 pop hi; ret) 15A Cl 569 ρ »»: »ρ be ί cnar) 15B Cl 570 pop be i rant> 15C E9 571 jp (hi) 572» (.-70-u. * / *. «t) \ 574» ex edr executes special led functions 575; (ret »scroll up» scroll dn * top »bottom) 576; if received since last call 577» if 1 cdkeyO-Oi then it contains the command. 578 »calls to exlcdr should be sprinkled at major 579. entry points in the BIOS. 580, 581 exlcdr) 150 E5 582. PUSH HL Ί5Ε CDOOOO X 583 cal 1 kvalue »9th t value of lc» i key t ή o 0 Q n j -J V%, i- v v -8- LU.i MODULE LCD PACE 8 LUi. ' Ijli ·· ..! CODE: M Ή -.:01 -π $ f'ATEififï.NT · ιΊ 9 (.1 j6i i.; J. 584 pop ue; c - key 0162 79 585 ld ai c 0163 FEDO 586 cp Oduh; ret to cursor 0165 CA6E05 F <587 * jp s.snap OJ68 FED1 588 cp Odlh; scroll led up 016A CA630 ^ R 589 jp rollι roll dn O 1 6D FED2 590 cp O d2h iscroi). Led d ow n 016F -CA5605 R 591 jp z. Rollup 0172 FED3 592 cp 0d3h i disp Up or buffer 0174 CA4F05 R 598 jp z, top 0177 FED4 594 cp 0d4h; disp bottom of buff 0179 CA4305 R 595 jp Zi bottom 0J.7C OEOO 596 ld Ci O; try BREAK 017E FED5 597 cp 0d5h 0180 CAOOOO X 593 jp 2 * BREAK 0183 C9 599 ret 600; 601 i 602. ledsta determine status of led display 603. always ready 604> 605 ledsta 0184 FDEI 606 pop iy i ret 0186 Cl 607 pop bc; ram ptr 0187 El 608 pop hl; flaq 0188 2EFF 609 ld 1, Offh 018A E5 610 push hl 0188 FDE9 611 jp (iy) 612; 613-614; Lcdcon standard console out device 615 ίemulates Standard televideo 920 terminal except 616. for screen attributes and protect modes. 617. direct led functions (roll up. Roll dn. Top. Bottom, i · 613; and function key definition chars must have been trapf 6.19; 620: 621 lcdcon 513D FDEl 622 pop iy) 18F D1 623 pop de; clear stack) 190 Cl 624 pop bc; get the char) 191 FDE5 625 * push iy) J93 3A0000 X 626 Id a. (eseflg) .was escape entered previously> 196 A7 627 and a) 197 2807 628 jr z, led 10 i no) 199 C5 629 push bc; put char on stack) 19A 210D02 R 630 ld hl. ledend j ret a dr) 19D E5 631 push hi) J.9E 1875 632 jr escape .process escape 633 Icd10) 1A0 3A0Q00 X 634 Id a. (Setcfl); are we processing a set cursor) 1 A3 A7 635 and a) 1A4 2808 636 j r 2.1c d20; η o> 1A6 C5 637 push bc UA7 210D02 R 638 Id hl.lcdend; ret adr> 1AA E5 639 push hi) JAB C3C803 R 640. jp satyrs; process setcur ^ 641 lcd20 Syl3 3 0 2 2 9 0 -9- LCli MUDDLE LuD PACE 9! I · ι 'uB-.i CODE M 8TMT SüURi.E ü f A [' EivIEïJ Γ A:.; R1 5 9 (, ij AE 2 Ι.ΟΕ · 02 R 642 ld hl. * Leend> re 1, adr O! BI E5 643 push hl 01B2 CS 644 PUSH BC 01B3 CD6E05 R 645 cal1 snap «bring cursor to led 0J.B6 Cl 646 POP BC 0XB7 79 647 ld a, e iget ehr * 01B8 FE20 648 cp 20h; is it normal graphic char 01BA 3808 649 jr c, led30 i no OiBC FDR1 650 pop iy 01BE C5 651 push be; pass ehar OJ.BF. FDE5 652 push iy; rel; adr 01C1 C36402 R 653 jp puteh; disp ehar 654 1c d30 01C4 FE1B 655 ep esc; escape char 0J.C6 2007 656 jr nz «lcd40; no 0108 210000 X 657 ld hl, escflg OJ.OB 3601 658 ld (hl), l> set escape entered flag 01CD 183D 659 jr led60 660 lcd40 01 CF FEOA 661 cp lf; lir.e feed 01Dl CA2003 R 662 jp Infeed; yes 01D4 FEOD 663 cp er; carriage ret 0LD6 CA9202 R 664 jp z, ergret 01D9 FEÖ8 665 cp bs; backs space 01 DB CA8103 R 666 jp z, backsp 01DE FE1A 667 ep els ί clear led 01 EO CAAB02 R 668 jp h, dried 01E3 FEOB 669 cp »cup <cursor up 01E5 CABD02 R 670 jp 2, curup 01E8 FEOC 671 ep eur» cursor right OJEA CA7502 R 672 jp 2, curqh! 11 ED FE IE 673 cp chm 674. ; cursor home!> 1EF CAÖD03 R 675 jp z, eur hom HF2 FE1F 676 cp newln> new line> 1F4 2006 677 jr riZiledöO 51F6 CD92Ö2 Fï 6- / 8 call crqret> 1F9 C32003 R 679 jp lnfeèd 680 1c d50> 1FC FE07 681 cp bell) 1FE 200C 682 yr nz «lcd60> 2u0 Eli 683 P'opi de» 201 210 200 R 684 ld hl, tneemd> 204 E5 685 push hl> 205 0E03 686 ld c, 3> 207 C5 687 push bc> 208 D5 688 push the> 209 C30000 X 689 jp keyemd 690 1cd60 20C El 691 pop hl; clear stack 692 1c d e n d 20D 3A0000 X 693 ld a, (toplcd)> save last valid top 210 210000 X 694 ld hl.lastH 213 77 695 ld (hl), a 214 C9 696 ret 697; % 698 * y 3. u 2?. ΐ * [ί -ΙΟΙ: Ü I! ϋ μ H „| - · LCD PACE 10 ... *, ·! · .. i n: u; n stmt source statement a:; m s. 9 700. escape process tne and ** · ¥ o J. J. on »i. ng escape code 70.1; executes the function specified. if not- regoniaed 702. no un uncti οn is per Γormed. • ΤΛΟ. / VO i 704 escape 0215 FI0E1 705 ρορί iy; ret 0217 Cl 706 pop be; gel char- 0218 FDE5 70.7 push iy 021A AF 708 xor a 02IB 320 000 X 709 Id <escflg), a 02IE. 7V 710 id 3j c 021F FE2B 711 cp · '+ ·' i clear disp 0221 CAAB02 R 712 jp a, dried 0224 FE2A 713 cp · '*' '0226 CAAB02 R 714 jp 2.dried 0229 FE3B 715 cp 0.22B 287E 716 yr z # dried 022D FE3A 717 cp 022F 207A 718 yr z »dried 0231 FE3D 719 cp · '= ·' 0233 2006 720 yr na.» esc 10 0235 210000 X 721 ldhl.setcfl '; enable 1oad cursor 0233 3601 722 Id <hi) d 023A C9 723 ret 724 esc10 023B FE51 725 cp 'Q-'; chr insert 023D CA7304 R 726 jp z> chri ns 0240 FE57 727 cp 'W' 0242 CAV204 R 728 jp z> chr del; chr del> 245 FE45 729 cp; line insert 0247 CABCÖ4 R 730 jp ad ini ns> 24A FE52 731 cp 'R ·' dir.e del 024C CAP504 R 732 jp ad in del> 24F FE59 733 cp Ύ · '; screen erase> 251 CA3B04 R 734 jp z, screra> 254 FE79 735 cp 'y'> 256 CA3B04 Ft 736 jp a> screra> 259 FE54 737 cp -'Τ · 'dine erase) 25B ÜA5104 R 738 jp ad in era> 25E FE74 739 cp -'t> '260 CA5104 R 740 jp ad in era> 263 C9 741 ret 742 743; 744} 745; putch place char at current cursor position 746; led window is assumed to display cursor position 747. cursor is moved one position right 748 i 749 putch '264 FDE1 750 pop iy; ret • 266 Cl 751 pop be j char 267 FDE5 752 push iy> 269 C5 753 push be 26A C5 754 push be • 26B CD5FOO R 755 call wrlcd; disp char on screen 26E Cl 756 * pop be 26F 2A0000 X 757 Id hL (cursor) [-Π-. ,, ‘J, Γ ι <.ι |. U F- LCD 't i; -r: 1 1 •' Ui fi. h:.: 1 VF * aiUK: E 'J I Hl EMENT -' 'v. - - :: - * ί 758 Id (hi), c; wri te char to bufïer .. * / -> 1880 75 '? jr curght 760 i 761; 762; curght move cursor one position to the right 763 ίif at end of line cursor is placed at the 764. start of the next line. 765.if on bottom of leda scroll up is also performed 766 i 767 curght 275 3A0000 X 768 id a / (curx) 278 FE4F 769 cp 79; are we at end of line 27A 2yOF 770 yr z> curgiO; yes 27C 3C 771 inc a; inc cur 1 pos 27D 320000 X 772 Id (curx), a 280 CD0500 R 773 call set-cur; disp cursor 2:33 2A0000 X 774 Id hi * (cursor) 286 23 775 inc hi 237 220000 X 776 Id (cursor) / hi 28A C9 777 ret 778 curgiO 288 CD9202 R 779 call ergret; return cursor 28E CD2003 R 780 call Infeed 291 C9 781 ret 782; 783 i 784. ergret return led cursor to start of current line 785; 786 ergret 292 210000 X 787 Id hi / curx; ret to start of line 295 3600 788 Id (hi). 0 2.> 7 0EO0 789 ld C / Q; qet ptr to buff or start of lir> 99 C5 790 PUSH BC C5 791 push be 79B 3AO000 X 79Z Id a. (cury) 4F 793 Id Ci a yqc es 794 push be "üO CD2601 R 795 scroff El 79 * 'POP M 'A4 220000 X 797 Id (cursor), hi rno ^ OO R 798' -all setcur, disp cursor, λλ Cv 'fev ί ΗΗ 800 ϊ 801 ί 802. dried initialize buffer to spaces and put led 803. and cursor at top of buffer 804 j 805 dried - / 10000 X 306 ld hi, screen 007 push hi? ftE Ew · y08 Id h 1 / scrsize 2AF ^> 00/809 push hi iBZ Ej 8L0 Id c / '·' · eiB3 Ofcu. 0 011 push be R 812 call fil1 2B6 'ririn.Y-. R 813 call curhom 2S9 CDOUOo * yl4. Ral 2BC 09 81s, - 2 * Λ 2 - 5 Ö r -12- LCD MODULE' -LD I · 'Li if. '11ιΤΐίΈ Μ 8TM f SUUr-'i; ·' Γμ 'CEMENT 816; Ui7; cur up move cursor up one Line 818. ifalt ο ρ of led * led ser ο 11 sdow η one' I i ri - 819. if at top of buffer * cursor will move to last line 820 iof led buffer 0 '> I f tf.d J. t 822 curup) 2BlJ 3A0000 X 823 Id a, (cury); test for at top of disp) 2C0 4F 824 1 d e, a) 201 3A0000 X 825 Id a * (top led)) 2C4. 89 826 ep c) 205 231.4 827 yr z, curul. 0; yes> 207 210000 X 828 Id hi, eury i up one line> 2CA 35 329 dec <hi)> 2CB 2A0000 X 830 Id hi, <cursor)> 20E 015000 83i Id be, maxcol> 2D1 A7 832 and a) 2D2 ED42 333 she hi, be '2D4 220000 X 834 Id (eursor), hl) 21) 7 CD0500 R 835 call set cur' 2D A C9 836 ret 337 curuiO '2DB 3A0000 X 838 Id a, (cury); at top line of buffer 2DE A7 839 and a 2DF 2023 840 jr ns, curu20 841 curl5 2E1, 3E14 842 1 da, maxr ow-4 2E3 320000 X 843 Id (toplcd), a 2E6 3E3.7 844 Id a, max row - 1 2E8 320000 X 845 Id (cury), a 2EB 3A0000 X 346 Id a, (curx) 2EE 4F 847 1 de, a 2EF 05 848 push be 2F0 05 849 push be 2F1 3A0000 X 350 Id a, (cury) 2F4 4F. 851 1 d c, a 21-5 C5 852 push be 2F6 CD2601 R 853 CALL scroff 2F9 Ei 354 pop hi 2FA 220 000 X 855 Id (cursor), hi 2FD CD7F00 R 856 call upled 300 CD0500 R 857 call setcur 303 09 358 ret 859 curu20 304 210000 X 860 Id hi, topled> move led up one line 307 35 861 dec (hi) 862 cur u30 308 CD7F00 R 863 call upled; rewrite led 30B 13BO 864 j r c u r u p 865; 3) 66 j 867> curhorn place cursor at top or led buffer 868.put 1 cd at top>: <f buffer 869 i 870 curhorn 30U AF 871 xor a 30E 320 000 X 872Id (curx), a dll 320 000 X 373 Id (cury), a JL «302290 -13- Li-D MODULE 1 -! -: Ll} - 'fttiE 1: -; L.ifC 'ÜB..I CüDE H 31 hT - =' -.YEMENI A Oh 5. V 0314 320000 X 874 Id (topled) «a 0317 210000 X 37¾ 1 d hLscrean 031A 220000 X 876 Id (cursor), hi 03 ID C34805 R 377 jp finish 878; * 879 i 380 / Infeed move cursor doujn one line 881. if at bottom of led, led serolls up. if at bottom 832. of buffer also, buffer scrolls up 883 i 884 Infeed 0320 3A0000 X 885 Id a, (topicd) i not at bottom of disp 0323 3C 886 ine a 0824 3C 887 inc a 0325 3C 888 ine a 0326 210000 X 889 Id hi, cury 0329 96 890 sub (hi) 032A 2812 891 jr a, Inf10 032C 015000 892 Id be, maxeol 032F 2A0000 X 393 Id hi, (cursor) 0332 09 894 add hi, be 0333 220000 X 395 Id (cursor), hi, -move cursor 1 line down 0336 210000 X 896 Id hi, eury 0339 34 897 inc (hi) 033A CD0500 R 898 call seteur 033D C9 899 ret 900 Inf10 033E 3A0000 X 901 1 d a, (c u ry) 0341 0E17 902 Id e, maxrow-1 0-343 B9 903 cp c 0344 20IE 904 yr nz. Inf20 0346 215000 X 905 Id hi, screen + maxcol; scroll buffer up 0349 E5 906 push hi 034A 210 000 X 907 Id hi, screen 034D E5 908 push hi 034E 013007 '909 Id be, sersi 2 e-max col 0351 C5 910 push be 0352 CDF900 R 911 call mov 0355 0E18 912 Id e, maxrow 0357 OD 913 dec c 035 £: C5 914 push be 0359 CD2B05 R 915 call clrlin 035C 210 000 X 916 Id hi, eury 035F 35 917 dec (hi) 0360 210000 X 918 Id hi, topied 0363 35 919 dec (hi) 920 Inf20 0364 210000 X 921 Id hi, top) .cd 0367 34 922 ine (hi) 0368 210000 X 923 Id hi, cury 0368 34 924 ine (hi) 036C 3AQQ00 X 925 Id a, (curx) 036F 4F 926 1 de , a 0370 C5 927 PUSH BC 0371 C5 928 push be 0372 3A0000 X 929 Id a, (cury), 0375 4F 930.1 de, a 0376 C5 931 push be 0 ^ 2 2 9 ° -14- .1.:. 1 1: 0.111 f ”LUD RAGE 14 '' 'Μ.,'. I · '' UUF h NT b'UURi-E 'I μ I Irl'ItN'l A8M 5. V.) 37 / CD2601 ft 932 call scroff [) .: 7 ή ΙΞ1 933 μ ο μ hi.) 373 220000 X 934 Id (cursor, hi):.: 7 E Ü34805 R 935 j μ f 1 η 1 sh 936; 937} 933.backs μ. back up cursor one posi i; ion 939; if at start of line »cursor is placed on end of 940; previous line. display scrolls down if necessary 941. if cur is at first char of buffer it moves to last 942. char of last line. 943; 944 backsp) 331 3A0000 X 945 Id a, (top LCD); prev line is on disp> 384 210000 X 946 Id hi, cury) 387 96 947 sub (hi)> 388 2006 948 jr nz, bcklO) 3SA 3A0000 X 949 Id a, (curx)> 380 A7 950 and a) 33E 2821 951 yr 2, bck30 952 bcklO) 390 3A0000 X 953 Ida, (curx)> 393 A7 954 and a) 394 200C 955 yr nz, bckl.5> 396 210000 X 956 Id hi, cury> 399 35 957 dec (hi) > 39 A 3E5Ö 958 Id A, max col> 39C 3D 959 dec a> 390 320000 X 960 Id (curx), a> 3AO 1304 961 jr bck20 962 bcklS) 3A2 210000 'X 963 Id hi, curx> 3A5 35 964 dec (hi) 965. c k20> 3A6 2A0000 X 966 Id hi, (cursor)> 3A9 2B 967 dec hi> 3 AA 220 000 X 968 Id (cursor), hl> 3AD CD0500 R 969 call setcur> 380 C9 970 ret 971 be k.30> 381 3AÖ000 X 972 Ida, (topi cd)> 384 A7 973 and a> 385 2008 974 jr nz, bek35> 3B7 3E4F 975 Id a, maxcol - 1> 389 320 000 X 976 Id (curx), a> 3BC C3E102 R 977 jp cur 15 978 bck35) 3BF 3D 979 dec a> 3C0 320 000 X 980 Id <toplcd), a> 383 CD7F00 R 931 call upled> 306 1889 982 jr backsp 983) 984 i 935; setcur direct cursor addressing \ 986; if setcfl = 1, y coordinate is received 987 iif setcfl = 2, x coordinate is received 988 ·; 9! :) 9 s e t c r s 8702290 -15- .L.ii Ι'Ίΐ.ί-;:. Ü. LCD PhOL 15 L: · Γ · Μ STMT SOURCE STATEMENT A ": r <r-i ·? icCSi cu.-..-! "0!;. i R v90 call snap · m * ve ijrs cursor is displayed <3CB FDEi 991 pop iy; ref.) ..: 00 Ci 992 pop be, char> 3CE FDE5 993 push iy): .-: DO 7v 994 Id af c) 3D1 FE20 995 cp '' *) 303 3304 996 Jr c, ng; validate char> 305 FE70 997 cp 'p'> 307 3305 993 Jr c, setiO 999 ng i3D9.AF 1000 xor a '3DA 320000 X 1001 1 d <setef 1) ia 3DD C9 1002 ret 1003 setiO 3DE 0620 1004 sub 20h; normalize ptr 3E0 4F 1005 Id e. a 3E1 3A0000 X 1006 Id a, (setef l) 3E4 FE01 1007 cp 1 3E6 2034 1003 jr nz, set50 3E8 30 1009 inc a 3E9 320000 X 1010 Id (setcfl) »a; get ready Tor x coordinate 1011 set-20 3EC 79 1012 1 da, c 3ED FE18 1013 cp maxrow 3EF 30EÖ 1014 jr nc, ng 3F1 210000 X 1015 Id hi, toplcd:) F4 BE 1016 cp (hi) 3F5 3006 1017 jr ne, set.30 3F7 77 1018 Id Chi), a 3F8 C5 1019 push be CD7F00 R 1020 call upled 3FC Cl 1021 popbe 1022 set: 30 3FD 3A0000 X 1023 Id a, (toplcd) WO C603 1024 add a, 3 1-02 B9 1025 cp c ï03 300B 1026 jr nc, set40 F05 C5 1027 p ush be; move: disp down) 06 79 1023 Id a, c 1-07 D603 1029 sub 3) 09 320 000 X 1030 Id (toplcd), a MX: CD7F00 R 1031 call upled, 0F Cl 1032 pop be 1033 set-40 HO 79 1034 Id a, c • 11 320000 X 1035 Id (cury), a; set new cursor 14 3A0000 X 1036 Id a, (top), cd) • 17 320000 X 1037 Id <last * t), a 1A 1809 1033 yr set60 1039 set50 1C 210 000 X 1040 ld hl, setef1 IF 3600 1041 Id (hi ), 0 j done 21 79 1042 Id a, c 22 320000 X 1043 Id (curx), a 1044 set60 25 3A0000 X 1045 Id a, (curx) 23 4F 10461 dc, a 29 C5 1047 PUSH BC ^; J J v £ £ ~ i -16- I..I .JI hi O ii il..L. LCD PACE] .6 U ': · ί. · M STM'F SOURCE STATEMENT AUrl 0. ··· <> L:' ü = ·. ". 104c push bc 0423 3AOOOO X .1049 ld a» (cury) 0 -'2E 41- 1050 ld C; a 042F C5 .1051 push ba 0430 CD.260J. R 1052 call scroff; make sure ptrs match 0433 El 1053 pop hl 0434 220000 X 1054 ld (cursor); hl 0437 CD0500 R 1055 call setcur 043A Cv 1056 rel 1057 ί 1053; 105V; screra erase buf fr from cursor lo end of screen 1060; 1061 screra 0433 CD5.104 R 1062 call linera; erase eurr line 043E 3A0000 X 1063 ld a # (cury) 1.064 loops 0441 3C 1065 inc a 0442 OEI8 1066 ld c »maxrow 0444 BV 1067 cp c 0445 D24805 R 1068 jp na; finish icury> = maxrow 0448 4F 1069 ld C; a 0449 F5 1070 push af 044A C5 1071 push bc 0440 ÜD2B05 R 1072 call alrlin 044E F1 1073 pop off 044F 18F0 1074 yr loops 1075; 1076 i 1077; 107C; linera erase from cursor to end of line 1079; 1030 linera 0451 3A0000 X 1081 Id a; (aurx) 0454 4P 1032 Id C; 3 0455 C5 1083 PUSH BC 0456 C5 1084 push bc 0457 3A0000 X 1085 Id a; (c ury) 045A 4F 1086 Id C; a 045B C5 1087 push be 045C CD2601 R 1038 call scrof f; wi 11 ret adr f or fill rtn to 045F 3E50 1089 Id a; max col 0461 210000 X 1090 Id hi; curx 0464 96 1091 sub (hi) 0465 4F 1092 ld C; a 0466 0600 1093 Id b. 0 0463 C5 1094 push be; store length 0469 3E20 1095 Id a, 20h 046) 3 4F 1096 Id C; a 046C C5 1097 push be; char to fill 046D CD 1701 R 1098 call fill 0470 C34805 R 1099 jp finish 1100; 1101: 1102 jehrins Q1103; move line right from cursor position 1104; put a space at the cursor position \ _ 1105; \ 83 "2 290 -17- Ê L _CLf MODULE I i. Π Ph! 4) LÜC QBJ r-jj» £ M ï-; TMT '"i · - tf- · r. .Teirifi NT 'A * -; t' 1106 chrjns.) 473 2A0000 X .1107 Ld hl <(cursor) 1476 E5 1103 pusn hl> 477 23 1109 inc hl> 473 E5 1110 pusn hl> 479 215000 1111 ld hl, maxeoi *> 47C 3A0000 X 1112 Ld a # (curx)> 47F 4F 1113 ld Ci a> 430 0600 1114 ld b, O) 4SZ A7 1115 and a> 433. ED42 1116 sbc hl, bc) 485 2B 1117 deft hl> 436 E5 1118 push hl) 487 CDF900 R 1119 call rnov) 43A 2AOOOO X 1120 ld hl, (cursor)> 4SB 3620 1121 ld <hl) .20h J48F C34805 R 1122 jp finish 1123 i 1124; 1125 i chrdel delete char at cursor position 1126; move line left- to fill space 1127; 1128 chrdel 1492 2A0000 X 1129 ld hi, (cursor)> 495 23 1130 inc hi 1496 E5 1131 pusn hi> 497 28 1132 dec hi i49S E5 1133 push hi '499 215000 1134 Id hi, maxioi> 49C 3A0000 X 1135 Id a, (curx) 49F 4F 1136 Id c, a (4AO 0600 1137 1 db, 0 4A2 A7 1138 and a '4A3 ED42 1139 sbc hi, be 4A5 E5 1140 push hi' 4A6 CDF900 R1141 call mov 4A9 0E50 1142 Id c, maxcol 4AB OD 1143 dec c 4AC 05 1144 PUSH BC 4AB C5 1145 pusn be 4AE 3A0000 X 1146 Id a, (cury) 4B1 4F 1147 1 dc, a 482 05 1148 push he 4B3 CD2601 R 1149 call scroff 486 El 1150 pop hi 4B7 3620 1151 Id (hl), 20h 489 034805 R 1152 jp finish 1153, 1154; 1155 <1 ins insert blank line at cursor 1156; 1157 linins 48C 05 1158 push be 4BD OEOO 1159 1 dc, 0 4BF 05 1160 push be 4C0 3A0000 X 1161 Ld a, (cury) 4C3 4F 1162 Id e, a 404 05 1163 push be ^ 3302 230 -18- LCD MODULE LCD CAGE lu I. mC '0) ::: .. 1 OLD M STMT: F MENT ASM 5.9 0405 CD2601 R 1164 I .1 seroff (> r08 C5 1165 push be 0409 OEOO 1166 1 de, o 040B C5 1167 push be 04CC 3A0000 X 1168 Id a. (Eury) 040F 3C 11 * 69 inca 04D0 4F 1170 Id e, δ 04U1 C5 1171 push be 04D2 CD2601 R 1172 call scroff 04D5 3A0000 X 1173 Id a <(eury) 04D8 6F 1174 Id la 0409 3E18 1175 Id a, max row D4DB 95 1176 sub 1 04DC 3D 1177 dec a 04DD 4F 1.178 Id c, a 04UE 05 1179 PUSH BU 04DF C5 1180 push be 04EO CD3E01 R 1181 call mpy80 04E3 CDF900 R 1182 call rnov 04E6 3A0000 X 1183 Id a, (eury) 04E9 4F 1184 Id e, a 04EA C5 "1185 push be MEB CD2B05 R 1186 call clrlin 04EE 3E00 1187 Id a, 0 04FO 320000 X 1188 Id (eurx) .a 04F3 1853 1189 yr finish 1190: 1191; 1192 J 1 i nde 1 delete current 1. i ne. A).). Fo). 1 owi ng lines 1193; move up. a blank line is put at the bottom 1194; 1195 1 indel) 4F5 OEOO 1196 Id c, 0> 4F7 05 1197 PUSH BO) 4F8 C5 1198 push be> 4F9 3A0000 X 1199 Id a »(eury)> 4FC 3U 1200 ine a> 4FD 4F 1201 Id c. a> 4FE 05 1202 push be> 4FF CD2601 R 1203 call scroff 1502 OEOO 1204 Id oO '504 05 1205 PUSH BO 1505 05 1206 push be' 506 3A000Q X 1207 Id a, (eury) '509 4F 1208 Id c, a' 50A 05 1209 push be '50B CD2601 R 1210 cal), scroff 50E 3E18 1211 Id a »maxrow 510 210000 X 1212 Id hi, eury 513 96 1213 sub (hi) 514 3D 1214 dec a 515 4F 1215 ld e« a 516 05 1216 PUSH BO 517 05 1217 push be 518 CD3E01 R 1218 call mpySO 51B CDF900 R 1219 call mov 5 IE 0E17 1220. Id c, max row-1 520 05 1221 push be 3X ^ 83 0 2 2 9 0 -19-, ι:) ι h; nn.! I_t LüD PAUE 19 i ·. ·:., 1 iJlDt M STMT SOURCE S'iAiErILNT ACM S. 9 / - ,,: 1 tjD2BOh R 1222 call cirlin.) 524 3E0Ö 1223 Id a, 0;): ·. · Ι26 320000 X 1224 Id (curx) ia D529 181D 1225 yr finish 1226 ί 1227; 1228; clrlin clear specified line to spaces 1229; 1230 clrLin) 5213 FDEi 1231 pop iy; ret;)! ::. 2D. D1 1232 pop de jline # 352E FDE5 1233 push iy 3530 0E00 1234 Id C / 0) 532 C5 1235 PUSH BC) 533 C5 1236 push he) 534 D5 1237 push the 3535 CD260J. R 1233 cal) scroff) 538 215000 1239 Id hi, maxed 353B E5 1240 push hi) 53C 0E20 1241 Id c, 20h 353E C5 1242 push be 353F CD1701 R 1243 call fill 3542 C9 1244 ret 1245; 1246; 1247; bottom put cursor at the bottom of the buffer 1248 i 1249; 1250 bottom 3543 3E14 1251 ld a, maxrow-4 3545 320000 X 1252 Id (toplcd), a 1253 finish 3548 CD7F00 R 1254 call upled 354B CD0500 R 1255 call setcur 354E C9 1256 ret 1257; 125 £ ΐ »1259; top put led at top of buffer 1260; 1261 top 354F 210000 X 1262 Id hi, top LCD 3552 3600 1263 Id (h1), 0 3554 18F2 1264 yr finish 1265; 1266 »1267 jrollup start led on next line in buffer 1268; 1269 roYY. up 3556 3A0000 X 1270 Id a, (toplcd) 3559 0E14 1271 id c, max row-4 355B B9 1272 cp c 355C DO 1273 ret nc 355D 3C 1274 inc a 355E 320 000 X 1275 Id (toplcd) / a 3561 18E5 1276 yr finish Cl277; % 1278. ; £ 1,279; rolldn start led on previous line in buffer \ 35C228Ö -20- LCD MiJiJULi: LCD PAüE 20 U.iü '·. 's j ii :: Η': Π UT yuURuE UTATEWENT A ': <: ·· v 12Ö0; 1201 roJ.1 dn 0563 3A0000 X 1282 ld aiCU'pled) 0566 A7 1283 and a 0567 C8 1284 ret z 0563 30 1285 dec a * 0569 320000 X 1286 ld <topled) .a 056C 18DA 1237 yr finish 1288; 1239} 1290; snap pul, led back to the position it was in 1291; after the last char or function was entered 1292; 1293 snap 056E 3A00ÖÖ X 1294 Id a, (top LCD) 0571 4F 1295 Id c. a 0572 3A0000 X 1296 Id a, (last * U 0575 89 1297 cp c 0576 C8 1293 ret z 0577 320000 X 1299 Id (topled), a 057A 18CC 1300 jr finish 1301 i 1302; 1303 3 \,. 0 Λ. % 'u W i- ~ «o. -21- ι ·; ΐ: .ν PAUL i LOL' '· 1 -iflT L.UI!; · .:. f ri..r! L. i.lT A -.- iT.v 1, 2 Revision niche lory 3. dale comments 4. J./26/82 TAKE UÜT KEY TABLE 5-6; 8206L4 Initial release. 7; 3 global, keysla keycnr linxl unlnkl keyi.nl 9 global keycmd conrec endcori 10 global exlcd 11 global kvalue inloff inton 12 global Icdrec keyrec 13 GLOBAL spcchr kyodin kyodsl io KcnK 14 15 16 exlernal butibsy devlab pager iooulr baudr 17 external initky Icdcon icdsta 13 external exlcdr uarlol uarlin uarlos uarlis 19 external nulinp null out external Icdkey keydir Ickey keydir keydir keydir keydir xeycnl keycbf J} 23 EXTERNAL 3PCHAR DEF8TA KEY 1X EXERCISE DEFNUM 24 EXTERNAL DEFL3T l-CNCIR FCNPTR KEY8ÊÜ KEYOFF 25 EXTERNAL TOTLEN TRLEN FTABLN 26 EXTERNAL FGNTAB FCNBUF FCNENI) 27 EXTERNAL seldsk settrk seldina setsec read 23 EXTERNAL mov ImpnuF home 29 EXTERNAL KEYüESΓ 30 31 32 Blue. DEF. 8 210 «-LIST ON 211 * 1 BIÜ8. EOU. 8 224 «-LIST ON 225 226 i 227 Iransk equ 2 228; 229. keys la * 230 i determines if any keys are wailing 231. plz call: 232. keysla procedure returns (fig byte) TOO doen'O i 234. asm call: 235. pusn hi 236. call keysla 237. pop hi j reg 1-0, no key; Offh, key 238; • 00 L'DBFOl FT 239 keysla call exlcd '03 El 240 pop ill • 04. E3 241 ex <sp) .h). i pop of f returη ωord '05 OEOO 242 1 dc, 0 '07 2A0000 X 243 id hi, (keyin) ΌΑ ED5B0000 X 244 ld de »(keyout) ΌΕ A7 245 and a OF EÜ52 246 · sbc hi, de '11 2802 247 yr keyslr 2 9 0 SOURCE CODE I; -22 "FMUfc:«: ν: L.UC ϋΪΓΗ.1 OtuE r'l 8ΪΜ Γ SUJki: £ TA il: r! L: 'M Γ (. »01 y OfclFF 243 Id c» orfh 0015 69 249 keyslr Id lc; put fiaq on stack 16υ 16 E3 250 e: ·: (sp), hJ 0017 E9 251 .jp (hi) 252 * 253 254 i 255. keychr from buffer 256. gel next, key cl »** '257. plz call: „reduce returns (ch byte) 253. key char Ρ» ° ct- 259. asm call: 260. pusn hi 261. call keychr, ^ character 2o2 j pop hi 263; 001.3 FDE1 264 keychr pop iy 001A El 265 pop nl 00IB E5 266 uiaitky push hi! wa.i t. for a char in the buffer 001C CDOOOO R 267 call keys! »» 00IF EJ. 268 pop hi 0020 7D 269 1 da, 1 0021 A? 270 and a 0022 28F7 271 yr ZiwaitkV 0024 F3 272 dj., It) ί pointer to next char 0025 2A0000 X 273 1 d hi, <key-'u ^ '»return it to caller 0029 (..5 2/5 push be 002A 23 276 j. nc hi, ... »... j.». 0023 110000 X 277 Id de. keyend * Al -lld * f Nl, -r 0O2E E5 278 push hi 002F A7 279 and a 0030 ED52 280 sbe hi, the 0032 El 281 pop hi 0033 2008 282 it * ns, no tend 0035 21 0000 X 283 Id hi. keys t ί wrap around to start of bulie 0038 220000 X 284 no tend id (key out) / ^ Οθ8β FB 285 ei 0O3C FDL9 286 jp (iy) 287 288 289 1 290. keyemd 291. send command to keyboard subsystem 292. plz call: 293. keyemd procedure (ptr "'' byte; len byte) 294. asm cal 1: 295 ·, Id hi, ptr; points to command string 296. push hi 297. Id 1, len; length of command string 298. push hi 299. call keyemd 300 i D03E DB04 301 keyemd in a, (i. Os la).: Check if keyboard busy 5040 ÜB7F 302 bit keybsy, a 5042 2OF A 303 yr ns, keyemd 5044 3A0000 X 304 · Ida, (baudr), · check if al ready talking I- ·: · it 5047 CB6F 305 bit keymine, a 0 2 2 9 0 '-25-! ί: τ PAGE 3! · 'I * GOÜE M STMT SUUKi AgM 5. Sr, n4v ^ 0F3 306., R,;:, Kevcmd lo48 re · jo7 d: i ί mak * sur * n <: «Keybd i nterrupi-s 0040 3A0000 X 308 J. da, (KeycnU; check it · 'acli vely receiving a? 04F A7 309 and a - 99 ^ 9 4Uv jr ns, l, ryagain / yes, wail For it to Finish D052 JAOoOO X 3ii ld a, (baudr) ; make sure all is dormant 0055 CB6F 312 bit keymine, a 3-13 yr riz, tryagain 0059 oBEF 314 sal keymine, aj claim keyboard 0O5B 0305 315 out (baud), a 3 * 6 Id b, 50; wail For arbitralion OoSf * 10FE 317 kwait djnz kwait:} 9 ^ j ·? .R.2c 3 * 9 in a, (i. Os la) / check iF keyboard became busy Xïoj C. & 7F 819 bi t. Keybsy »3.) MS 2y08 820 yrs z.goUi. 067300000 X 321 Id a (baudr); keyboard nas the bus) 06A 0305 322 oul (baud) / a. 323 tryagain) 06C FB 324 'ei> 060 1 8C-F 325 yr key cm di wai t some more • K;, 6F 21U000 X 326 golil Id hi, baudr) 07z CEEE - 3Z7 set keymine, (hi) / update software reg) 074 FB_ 323 ei) 075 3E01 329 Id a, 1; sel direction Flag to sending> 077 320000 X 330 Id (keydir), a) 07A UooOO X 331 Id de, keycbF / copy cmd to command buFFer FDEi pop iy; return addr KJJF 33: ^ pop be ic = !. eii '030 Ei 334 pop hi / command string ptr 1031 0600 335 Id b, 0 '083 79 336 Id a, c / save lingtn' 994 £ DBO 337 I dir / copy siring 086 210 100 X 338 Id hi, keycbf + 1 039 2200ÖÖ X 339 Id (keyplr), hi / set up plr & length 08C 3D 340 d * ca93¾ 3 ^ 999 ° X 341 Id (keycnl), a 090 3A0UU0 X 342 Id a, (keyebf) / send off first char 9'f3 ^ '? ^ 4. 343 out (keydal), a 095 CDlOol R 344 call stbkey / interrupt keyboard subsystem 093 FDE9 345 jp (iy) 346 347 348 / 349. keyinl 350. entry on receipt oF a keyboard 3v.il / interrupt 352/353 keyint 9? A EB / 3OOO0 X 354 Id (i.nlsav), sp DyE 310O0O X 355 Id sp, intstk / switch to local stack: OAi F5 356 push aF -> Az C5 357 push oc 0A3 D5 353 push de -) A4 E5 359 push ril '.) A5 DDE5 360 push ix DA7 FDE5 361 pU3h iy. » A9 3A1C01 R 362. Id a, (ininl)> AC A7 363 and a ./:,:: -24- KEY H'H U 1: 1 4! ΙΚ: *, ί I STMT SUURCE 3 ί Α CEMENT Α:.: Μ:. i. 9 "Ά: 1: j64 yr in I ok u '-;' AF 00 365 nop '- • OHO 3E0i 366 inf, ok ld a, 1 U0 & 2 321CO1 R 367 Id (inin't), a 00 ^ 5 3A0Ö00 X 363 id a, (keydir); sending or receiving? 9033 a7 369 and a 0039 OBJ4 370 in a, (keydat) i reset, interrupt request 0033 2026 371 jr nzi sridkey »sending 372. ei. I« Η **** **** · # · * · * · # * * * # # * * # # # * - * · * · # · # - »· * · # · # · # 003D oo 373 NOR; *** *********************** · *** UOHE E60F 374 and 0 fh; receiving OOCO p5 375 push af 6F 376 id ha J0C2 CD2C01 R 377 call setkey .set- up buffer ptrs if require OOijs 3y 12 373 jr c, badch FI 379 pop af JOCQ 2A0000 X 380 id hi; (keyptr); deposit char into buffer 00C3 77 381 Id (hi)> a OOCC 23 382 inc hi OOCD 220000 X 383 Id (keyptr), hi OOUu 210000 X 384 id hi, keycnt; count byte 00D3 35 385 dec (hi),) 034 CC4801 R 386 call,:, kdspatch iif all bytes received, separa? IJD7 1801 387 yr rcvrel 001) 9 pi 388 badch pop af 389 rcvret OOÖA F3 390 di AF 391 xor a L '. ^ Dy] 4 392 out (keydat), a> send nop to key co ntroller fODE GDIDO1 R 393 call stbkey 1827 394 jr keyrtn JOEy 3AÖ000 X 395 sndkey Id a, (keycnt); any more bytes to send? JUË6 ft- /: 3,, 6 and a? Υ ^ 2010 397 jr nz, sndmore> yes X »E9 3A0000 X 398 Ld a, (baudr) j done, reset busy flag -JOEC GBAF 399 res keymine, a X) EE 320000 X 400 Id (baudr), a ^ OF10305 401 out (baud), a; relinquish control over keyboa J0F3 AF 402 xor a.> 0F4 320000 X 403 Id (keydir), a; revert to receiving character 1811 404 j r keyrtn> 0F9 2AOuOo X 405 sridmore Id hi, (keyptr); get next oyte to send to kybd K-'FC 7E 4.06 Id a, (hi)) OFD 23 407 inc hi) OFE 220000 X 408 Id (keyptr), hi) 101 D314 409 out (keydat), a) 103 CDlDOi R 410 call stbkey inform controller or byte) 106 210000 X 411 Id hi, keycnt »1.09 35 412 dec (hi)> 10A FDE1 413 keyrtn pop iy HOC AF 414 xor a HOD 321C01 R 415 Id (inint), a 11.10 DDE1 416 pop ix '112 El 417 pop en HJ.3 Dl 418 pop de 114 Cl 419 pop dc J. 15 FI 420 * pop off 116 ED7BUU0U X 421 Id sp, (intsav) "V 8302290 -25- ΚΈΥ F-'hüL JiC l.>!: ·.>. · ...: -i '.Tf'1 F SUI.K - I .Ï STATEMENT W -i'I * »'