NL8200943A - FM receiver with high signal=to=noise ratio - detects and demodulates digital-data-carrying signals having pseudo-fire-value levels - Google Patents

Abstract

This non-coherent receiver detects, demodulates and decodes FM digital data signals having pseudo-five-value signal levels. The received signal is fed to a combined frequency converting, amplifying and limiting circuit (2). The output of this circuit is fed to a frequency discriminator (3) to recover the base-band signal (4). The base-band signal is fed via a low pass filter (6) that removes all signal components with frequencies higher than the base-band to feeds a level detector circuit (7). The output of the level detector is fed to a decoder circuit (8) that produces the recovered data signals (10). Both the level detector circuit (7) and the decoder circuit (8) are synchronised by a clock pulse generator (9), which is itself triggered by the base-band signal (4).

Description

% γ \. .. _i ΕΗΝ 10,292 1 "N.V. Philips' Gloeilampenfabrieken in Eindhoven ..........)" A non-coherent receiving device for the reception of EM-modulated data signals with pseudo pentavalent signal levels "

The invention relates to a non-coherent receiver arranged for the reception of FM modulated data signals with pseudo five-valued signal levels, comprising a frequency discriminator and a detection device connected thereto. A receiver adapted for the detection of EM modulated data signals with pseudo five-valued signal levels are known from the article "On the application of Tamed Frequency Modulation to various fields of digital transmission via radio" by CB Dekker published in "Intern. Zurich Seminar on Digital Communications, 10 Digital Transmission in Wireless Systems" Zurich, 4-6 March 1980 (IEEE 1980). The coherent receiver described there has a carrier regenerator. During the capture time of this generator, the receiver does not work coherently.

For radio communication systems, carrier modulation systems which deliver a modulated signal with constant envelope signal are preferred because of their high efficiency obtained by the possibility of applying non-linear amplification. This has led to a widespread use of FM modulation. The spectrum of EM modulated signals is quite wide. To narrow this spectrum for digital signal transmission, the data signals were pre-processed by applying a certain intersymbol interference, thereby obtaining signals with pseudo multivalent signal levels before feeding them to the frequency modulator. For example, it is from the article "Tames Frequency Modulation, A Novel method to 25 Achieve Spectrum Economy in Digital Transmission" by F. de Jager and C.B. Dekker published in IEEE Transactions on Communications,

Full. CQM-26, No. 5, May 1978, known to compose a pseudo pentavalent signal according to the encoding rule 7C / 2 (an_f / 4 + a ^ / 2 + an + ^ / 4) where nth is binary bit etc. and then filtering with a Nyquist III filter. "

Furthermore, it is from the article "G.M.S.K. Modulation for digital Mobile Radio Telephony" by Kazuaki Mirota and Kenkichi Hirade, published in IEEE Transaction on Cmmmunications Vol. CQM-29, No. 7, 8200943

Sr J

PHN 10,292 2 July 1981, pages 1044-1050, known to compose a pseudo downward signal by filtering using a low-pass fliter with a Gauss characteristic.

From the article "On a class of generalized MSK" by 5 P. Gaiko and S. Pasupathy, qp presented the conference ICC '81

Denver June 1981, pages 1-6, it is known to compose a multivalent signal according to the down-generalized encoding rule for 2 MSK nml. (1 + KD + D) / (2 + K) where K ^ O and D is the delay over 1 bit period and then filterable using a Nyquist III 10 filter.

In order to recover the data signals from the carrier signals which have been modulated in frequency by means of these multivalent signals, it is known from the above publications to use coherent detection. However, coherent detection has the drawback that a certain time is required to capture a carrier regenerator on a received carrier signal, which for the above signal lesson is approximately 100 bit times.

However, this is not permitted in mobile radio applications.

On the one hand due to the fact that when the so-called "spread spectrum technique" (spread spectrum technique) is used, the transmitted carrier frequency is switched between a large number of different values and on the other hand that with a varying signal-to-noise ratio of the received signals, for example as a result of Fading 25 series of errors due to the slow regeneration control are introduced. To this end, the article of C.B. Dekker, published in "IEEE Trans, on May 1978, disclosed a coherent receiver of a frequency discriminator provided with a detector connected thereto which acts as a non-coherent signal receiver during the capture time of the carrier wave regenerator. From the output at the output of the frequency discriminator The pentavalent signal obtained is recovered in a detection device suitable for this pentavalent signal.

The object of the invention is to realize a new concept for a non-coherent receiver for pseudo pentavalent signals, wherein a simple signal detector will suffice and which generally has a better signal-to-noise ratio.

The receiver of the type mentioned in the preamble is characterized in that the detection device is arranged for detecting the data signal qp the moments in the pseudo-output produced by the frequency discriminator, according to the invention. pentavalent signal, essentially three signal levels occur.

A signal having substantially three signal levels is here understood to mean a signal in which the broadening of the levels due to intersymbol interference are not counted as separate levels, but are considered to belong to those levels.

According to a further measure, the non-coherent receiver is characterized in that the detection device comprises an EU filter connected to the frequency discriminator, a level detector coupled to the filter and a decoder connected to the level detector.

A very simple non-coherent receiver is characterized in that the level detector is connected via a double-sided rectifying circuit to the filter, the level detector has a single detection level and the decoder is a pulse generator.

A receiver which can be realized almost entirely digitally is characterized in that the detection device comprises an analog-digital trigger connected to the frequency-20 di-inverter, and a first adder connected to the analog-digital converter for adding the digital signal output by each converter. a negative number of a given value, a second adder connected to the analog digital converter, for adding a positive number with a value equal to the absolute value of the determined negative number to each digital signal output by this converter, contains a three-tooth switch, the switching arm of which is connected to a first register, a first contact is connected to the first adder, a second contact is connected to the second adder and of which the output of the first register is connected to the third contact via a s signal inverting device is connected, a third adder device connected qp the first adder and qp the first register for adding the signals output from these devices, a fourth adder 35 comprising connected qp the second adder and the first register for adding the signals output by these devices, a qp contains the first register and logic circuit connected to the third and fourth adder, which via a first control conductor 8200943 EHN 10.292 4

• I

*> ------- cp the three-position switch is connected to jumper the first contact to the first register if the signals output from the third and fourth counters are greater than or equal to zero, to jumper the second contact with the first register if the signals output by the third and fourth adders are less than zero and for connecting the third contact to the first register if the signal output by the third adder is less than zero and the output by the fourth adder signal is greater than or equal to zero and the detection device is provided with a decoder comprising a first and a second shift register, a logic signal "1" being continuously supplied to the first stage of the first shift register and the first stage of the second shift register is continuously supplied with a logic signal "0", the corresponding 15 steps of both the shift registers are connected together and the logic circuit with a control conductor is connected to control terminals of the shift registers for the signals supplied under the control of these control circuits of the signal contents of one of the shift registers in the other shift register, comprising a two-position switch of which a first contact is connected to the output of the first shift register and the second contact is connected to the output of the second shift register and of which the switch is connected to an output register, the logic circuit is connected to the two-position switch via a third control conductor for connecting the output of the second shift register to the output register if the output of the third adder is greater than or equal to zero and if the output of the first register is greater than or equal to zero and also the output of the third adder less than zero and the output of the fourth adder is greater than zero and for connecting the output of the third shift register to the output register if the output of the fourth adder is less than zero and if the output of the third first register is less than zero and also the output of the third cptel-35 device is less than zero and the output of the fourth adder is greater than zero.

With this receiver a very good S / N noise ratio is obtained for the detected pseudo, multi-valued frequency modulated. 8200943 i ESN 10.292 5

«I

Learned signals. ____

The invention and its advantages will be further elucidated on the basis of the exemplary embodiments shown in the figures, wherein corresponding parts are indicated in the different figures with the same reference signs / showing:

Figure 1 shows an embodiment of a receiver according to the invention.

Figure 2 the impulse response of a TEM pre-modulation filter.

10 Figure 3 the eye pattern of a TEM signal.

Figure 4 a table.

Figure 5 shows another embodiment of a receiver according to the invention.

Figure 6 shows the spectrum of a demodulated and rectified TEM signal.

Figure 7 shows a clock pulse regenerator for use in the exemplary embodiment according to Figure 5.

Figure 8 is a graph plotting the error probability Ep versus the S / N ratio for asynchronous five- and three-twenty-valued signals.

Figure 9 the eye pattern of a GMSK signal.

Figure 10 the eye pattern of a Modified Gauss ion MSK

signal.

Figure 11 shows the impulse response of a generalized TEM pre-modulation filter to obtain an optimal three-eye view.

Figure 12 shows the eye pattern associated with the GTEM pre-modulation filter with response according to figure 10.

Figures 13, 14, 15a and 15b, signal grating networks which occur upon detection according to the maximum probability method.

Figure 16 shows an exemplary embodiment of s = maximum decoder probability.

Figure 17 shows an embodiment of a logic circuit and two switches for use in a decoder according to Figure 16 and

Figure 18 is a graph plotting the error probability Ep against the S / N ratio for various modes of trivalent signal detection of a TEM signal.

8200943 * i EHN 10.292 6 ....._ The non-coherent receiver shown in figure 1 contains an input terminal 1 to which, for example, an antenna (not shown) is connected. The signal supplied by the antenna of the input terminal is an EM modulated signal of the type S (t) = sin (cj t + 0 (t) 5 where <JL is the carrier angular frequency and n 0 (t) the information carrying v with the time varying phase angle.

This signal is optionally transposed, amplified and limited in the receiver stage 2 in a known manner before it is applied to the frequency discriminator 3 for the recovery of the baseband signal from the signal S (t). This baseband signal is supplied to a detection device 5 for recovering the original data signal from this baseband signal.

The qp output terminal 4 output baseband signal U (t) is equal to the time derivative of the instantaneous angular frequency of the signal S (t) and thus equal to: «D (t) = ω + -312- v 'c dt

The detection device 5 is adapted to detect those phase-modulated signals, wherein the data signals are pre-filtered in the transmitter in order to obtain a narrow bandwidth of the transmission signal cp before modulation.

The signal generated by such a pre-modulation filter can be written as: 25 j- -η r Γ <22_

0 (t) = K an. g (r-nT) d? * + C

J ~ go Ln = - <s> _ where an is the binary input signal, n is an integer, 30 9 (t) is the impulse response of the TEM pre-modulation filter, K the sensitivity to the deviation in frequency of the filter resonance frequency is expressed in rad./Volt/second, T is the signal period of the bit time of the input signal and C is a constant.

The signal U (t) output by the frequency discriminator 3 is therefore equal to: <50 U (t) = COc + K an. g (t - nT) n = -c? e 8200943 X 4 EHN 10.292 7 -------- The ideal output signal of the frequency discriminator for a transmitted data bit is therefore equal to K. g (t), where a value "1" of the data bit corresponds to a positive polarity of g (t) and for a transmitted data bit net value "0" corresponds to a negative polarity of g (t).

The operation of the receiver is further explained first on the basis of a specific frequency-modulated signal, although the receiver is also arranged for processing other types of frequency-modulated signals with pseudo multivalent signals.

? 0 A TEM signal was chosen as the specific signal, which signal is described in detail in the article "Tamed Frequency Modulation, a novel method to Achieve Spectrum Economy in Digital Transmission" by F. de Jager and C.B. Dekker published in TEER Transactions on Ccmramications, Vol. CQM.-26, No. May 5, 1978.

From this article it is known that the pre-modulation filter used in the transmitter is built up from the series connection of a non-recursive second-order digital filter with weighting factors of 1/4, 1/2 and 1/4, respectively, and a Nyquist III filter.

Figure 2 shows the pulse response ± ejg. (±) of this pre-modulation filter. Due to the fact that the filter is of the second order, the ürpulsr espons ie extends over a period of 4T.

This figure 2 shows that at time t = 0 the impulse response g (0) has the value V and at times t = T the impulse

P

Response g (T) has the value V ^ / 2. Since the data bits are transmitted at regular intervals of T, the consecutive transmitted data bits overlap. This intersymbol interference gives a pseudo pentavalent signal, which 'gives a gradual change of the instantaneous phase 0 (t) of the FM modulated signal, thereby achieving the intended bandwidth reduction. Furthermore, the presence of a Nyquist III filter in the pre-modulation filter indicates that the phase 0 (t) at times t == nT, where n is a natural number, passes through predetermined points.

The eye pattern of the signals output by the frequency discriminator 2 therefore has the form shown in Figure 3. This figure 3 shows the pseudo pentavalent character of the TFM signal, represented by the five signal levels 5-N at the scan times t = nT with n = 0, 1, 2, etc.

8200943 ΕΉΝ 10,292 8. These five signal levels also follow directly from the impulse response of the pre-modulation filter shown in Figure 2. The expression representing the phase difference between two consecutive scanning elements of a TEM, pre-modulated signal is 5 according to the said article of the Hunter, and Dekker is equal to: POUT + T) - Pm = 7Γ / 2 (aa_1 / 4; + a ^ / 2 + a ^ / 4) (1)

If all possible bit combinations of three to ten consecutive bits are substituted herein, which are shown in column 1 of the table in figure 4, the signal levels S (Q) shown in column 2 are obtained therefrom according to the relationship: S (0) = a ^ g (T) + aQ g (0) + a + 1 g (-T) (2) where a_ ^, a ^ and a + ^ have the values shown in column 1 of Table 4 and where g (0) is the value of the impulse response shown in Figure 2 at time t = 0 and g (+ T) has the value of the impulse response at times t = + T.

The values shown in column 2 are standardized qp V ^.

For example, for a_ <| = aQ = a + 1 - 1 that S (0) =% + l +% = s2 and applies for example to a. = an = 0 and a ,. = 1 that 25 '1 ^ +1 S (0) = -½ - 1 + ½ = -1 etc.

Because the data coded in this way for the bit sequences ..., 1, 0, 1, 0, ... and ...., 0, 1, 0, 1, ....

30 have the same value 0, the data cannot be directly recovered from this. To overcome this drawback, it is known to pre-process the data in the transmitter by means of a differential coding. The rule for this differential coding gives that dfc = ak with a ^ = + 1 is the input data and d ^ and d ^ is the 35 different coded data.

It is possible with data pre-coded in the transmitter in this way to recover the data directly from the eye pattern shown in figure 1 by decoding bit by bit at times t = nT

3200943 X a EHN 10.292 9 __________ using four nievaji detectors, soot the respective levels .....

+ E ^ and + E2.

Because the eye pattern is a pseudo pentavalent signal, the two inner eyes contain enough information to decode the signal with two level detectors + E ^.

However, it is also possible to detect the received signals qp in a different manner, whereby simpler realization of the receiver is obtained and the S / N ratio can be improved.

For this purpose, the detection device 5 of the receiver shown in Figure 1 comprises a low-pass filter 6 connected to the frequency discriminator 3 for suppressing frequency components located outside the baseband, a level detector 7 connected thereto and a decoder 8. As a low-pass filter, an 8th order maximum flat filter with the -3 dB point located at the 15 frequencies, where the bit rate is.

The low-pass filter significantly reduces the noise at the input of the level detector.

Furthermore, the receiver contains a clock pulse regenerator 9 connected to the level detector 7 and the decoder 8. This clock pulse regenerator 9 delivers clock pulses whose transitions at times t = (2mr1). T / 2, with m = 0, 1, ... etc. are located.

The pseudo pentavalent signal delivered by the frequency discriminator 2 is therefore scanned qp at times t = -T / 2, t = T / 2, t = 3T / 2, etc.

The impulse response shown in Figure 2 has the value p V ^ at moments t = T / 2 and t = -T / 2, qp at time t = 3T / 2 the value q V and at the other times a value substantially ir equal to zero. For all possible combinations of three consecutive bits, as in column 1 of the table shown in figure 4, the signal levels S (T / 2) can be determined in a similar manner as described above for the signal levels S (0). All times in formula (2) must be shifted by a value T / 2. This gives that S (T / 2) = a - g (3T / 2) + aQ g (T / 2) + a - g (-T / 2) (3)

For the qp Vp normalized values of g (t) it follows from figure 2 that g ("T / 2) = g (T / 2) = p and g (3T / 2) = q.

35 8200943 PHN 10.292 10 _____ We choose a_ | = aQ = a + 1 = 1 then S {T / 2) = p + p + g = 2p + g and we choose a_ ^ = a + 1 = 1 and aQ = O then S (T / 2) = p-p + g = g etc.

5

The results thus obtained are shown in column 3 of Table 1 shown in Figure 4.

This column shows that if g = 0 instead of 10 there are only three levels, +2, -2 and 0.

If g is not equal to zero, then these levels are shifted both downwards and upwards over the value f qj, so that the above three levels are each situated in an area of 2q.

These three levels and the surrounding areas are also directly visible from the eye pattern shown in figure 3, namely at times t = T / 2 and T = 3T / 2. etc.

This Figure 3 clearly shows that as long as p can recover the data from the trivalent eye pattern using a receiver equipped with only two level detectors with levels approximately equal to + E and -E. If we apply this detection "" rule to any set of input data, assuming for the simplicity of the example q equaling zero and p equal to one, we obtain the values given in Table 2 below.

Table 2

Input data ak 1, 1, 1, 0, 0, 1, 1, 0, 1, 0, 1, 1, 1, ...

Received levels S (T / 2) 2, 2, 0, -2, 0, 2, 0, 0, 0, 0, 0, .....

30 Decoded data 1, 1, x, 0, x, 1, x, x, x, x, x, .....

In addition, the received levels from the input data are obtained by using famule (3) and the decoded data is derived from the received 35 'levels by a data bit with value "1" when the signal value of the level + E = 1 is exceeded. and to assign the data bit the value "0" when lifting a signal level with a value less than + E = -1. The received zero 8200943 * f EHN 10.292 11 Λ '___ levels are not unambiguous, however, and are indicated with an X in the said decoded______ data bits.

An additional decoding rule is required to resolve this ambiguity.

5 It reads as follows: if S (T / 2) = 0 then the detected data bit has the value "1" if the previously detected level S (3T / 2) was detected as a "0" and the detected data bit has the value "0" as the previously detected level S (3T / 2) as a "1" was detected.

However, the receiver required for this detection contains neither two level detectors 7 and a complicated decoder 8.

A highly simplified receiver is obtained if the data in the transmitter is differentially encoded before it is modulated to obtain a multivalent signal using a pre-modulation filter. As described herein, this differential decoding is common.

Table 3 shows this differential coding and the decoding from the trivalent signal levels at times T / 2 for the same input data as in Table 2.

Table 3

Input data a ^ 1, 1, 1, 0, 0, 1, 1, 0, 1, 0, 1, 1, 1, ...

Differentially coded d, ° '°' ° '°' 1 '°' ° '°' 1 '1' ° '°' ° '°' *** 25 h 1, 1/1, 0, 1, 1, 1 , 0, 0, 1, 1, 1, 1, ...

Levels received -2, -2, -2, 0, 0, -2, -2, 0, 2, 0, -2, -2, -2, ...

2, 2, 2, 0, 0, 2, 2, 0, -2, 0, 2, 2, 2, ...

Decoded data 1, 1, 1, 0, 0, 1, 1, 0, 1, 0, 1, 1, ...

30

The differentially encoded data is derived from the input data according to the rule d ^ = a ^. + d ^ just the two possible initial conditions d ^ _. j = 0 or dj, _. j = 1 which yields inverse sequences to each other. The received levels S (T / 2) are derived therefrom by means of formula (3).

The decoding is with the help of a level detector. . with levels + E and -E. From this decoded data it follows that due to the differential coding in the transmitter, the ambiguity of the 8200943

* V

EHN 10,292 12 ___ receiver has been canceled.

Furthermore, it follows that a received zero level corresponds to a value "0" of the data bit and a received level of plus or minus two units corresponds to the value "1" of the 5 data bit. Thus, instead of two detectors, it is possible To first align the received signal and apply a single level of E for detection.

The detection device 5 of the receiver shown in Figure 5 differs from that shown in Figure 1 in that the level detector 7 comprises a double-sided rectifying circuit 11 and a detector 12 with one single level equal to E.

The decoder 8 is designed as a pulse regenerator at the times (2m-1). T / 2 outputs a signal "1" if the level E of the detector 12 is exceeded by the rectified signal and outputs a signal "0" if the level E of the detector 12 is not exceeded. For an inverse differential coding in the transmitter, the output signals "1" and "0" of the pulse generator must also be inverted.

The clock signal required for this detection can be easily recovered from the received signals. The spectrum of the output signal from the double-sided rectifier 11 for a received TEM modulated signal is shown in Figure 6. In this figure the signal level is plotted in steps of 10 dB against the qp the bit frequency fg normalized spectrum f.

This figure shows that this spectrum has a strong component for the bit signal frequency. In order to recover the clock signal therefrom, the clock signal generator 9 shown in Figure 5 is constructed in accordance with Figure 7. Using an bandpass filter 14, an symmetrical part of the spectrum is filtered out, the clock signal being in the center. As filter, for example, an combination of a 4th order Butterworth high and low pass filter with active components can be used. This filtered signal is then applied to a phase-locked loop (phase locked loop) for suppressing the jitter occurring in the filtered signal. From the clock signal thus regenerated, a clock signal is derived, with the aid of a suitably chosen delay, whose transitions qp times t = (2m-1) T / 2 are located.

8200943, ΕΗΝ 10,292 13.

______ · It appears from the eye pattern shown in figure 3 that the ___________ opening of the trivalent eye qp at times t = (2mr1) T / 2 is slightly larger than the openings of the pentavalent eye at times t = it £ T. This means that the signal to noise ratio S / N of the signal detected at times t = (2m-1) T / 2 is better than that detected at times t = irff.

In Figure 8, for a TEM signal, the calculated bit error probability pF is plotted against the signal-to-noise ratio S / N with a bandwidth equal to f ^ in asynchronous detection.

10 Curve a) is calculated for a pentavalent signal detection 5N, so when scanning at the times nfl? with m = 1, 2, 3, ... and curve b) for a trivalent signal detection, i.e. when scanning at times (2m-1) T / 2 with m = 1, 2, 3, ... etc. The less error probability for signal-to-zero ratio values from four is significant for trivalent signal detection.

The receiver shown in Figure 5 is not limited to the reception of TEM modulated signals, but is suitable for the reception of all EM modulated signals where the instantaneous angle deviation is given by a pseudo pentavalent signal. Another example of such a signal is a GMSK signal (Gaussian Minimum Shift Keying). The eye pattern of the signal for a bandwidth bit time product of 0.19 is shown in Figure 9. This figure shows on the one hand that detection of the signal qp at the times t = (2m-1) T / 2 is possible with the receiver described above and on the other hand that the trivalent view of the times t = (2m-1) T / 2 is much greater. is then the pentavalent eye at the times t = itff. Therefore, the S / N ratio is correspondingly greater than detection qp at times t = nfT for signal detection qp at times t = (2m-1) T / 2.

Moreover, the S / N ratio at detection qp at the times 30 t = (2mKl) T / 2 is better than for a TEM signal.

Yet another example shows the eye pattern of the M5MSK signal (Modified Gaussian Minirrum Shift Keying) shown in Figure 10 as described by the applicant in the not yet prepublished Dutch patent application 8101611 for the product bandwidth of a Gaussian filter times bit time BT = 0.19 and A (D = + 2T) = 0.02 being the outer tap coefficients of the non recursive correction filter. The same considerations apply as given for the OMSK modulated signal.

8200943 EHN 10.292 14 ____ The eye patterns shown in Figures 3, 9 and 10 further show that at times t - (2m-1) T / 2 the trivalent eyes are not optimally open.

To enhance this eye pattern, the per se known method of including an equalization filter after the frequency discriminator in the receiver can be used to reduce the intersymbol interference of the signal at the scan time points (2mr1) T / 2 .

However, such an equalization filter is difficult to implement and adds extra noise to the signal.

However, an optimal trivalent eye can be easily obtained with a Generalized Tamed Frequency Modulation pre-mud filter in the transmitter. Such a filter is understood to mean a three-branch transverse filter with a transfer characteristic characterized by: / T / 2 (ÖCAn_ ^ + \ + oc An +> J) where 20t + / 3 = 1, followed by a Nyquist III fliter realized with a Nyquist-I lifted cosine filter (raised cosine).

The weighting factors of the non-recursive second order digital filter must be equal to β - 0.62 and the Nyquist Ill / must have a waste parameter (roll off factor) r equal to 0.36. "" - -

The impulse response of that filter is shown in Figure 11.

As this figure clearly shows, the pulse response value for t greater than 3T / 2 is very small, giving negligible undesired interference. This figure also shows that for t = 3T / 2 the value of the Pulse response is almost equal to zero. The approximation of the value of q, which has been set equal to zero, has been fully satisfied by such a pre-modulation filter.

The eye pattern obtained with the aid of this pre-modulation is shown in Figure 12. This figure shows the optimal eye pattern for the scan times t = (2m-1) T / 2 and the resulting optimal S / N ratio with respect to a signal detection 35 cp the scan times t = ntT.

In addition to the methods mentioned above to reduce the number of incorrectly detected signal values, it is also possible to reduce that number by using the redundancy 8200943. 4 - · EHN 10.292 15 ------- of said signals. A decoding method of this redundancy.

Maximum-likehood decoding.

A three-level TEM signal at the output of the 5-frequency discriminator · 3 can be accurately approximated by the symmetrical son signal S '(t) of four consecutive pulse responses of the cJIIM pre-modulation filter, where S' (t - -Iff— ) = ak-2. g (t- (k-2) T) + ak_1. g (t- (ki) T) + ak g (t-kT) + 10 + ak + 1 g (t- (k + 1) T) (4) where a ^, and a ^ are binary data bits with = + 1 and k = 1, 2, 3, ...

The signal S '(t) is scanned every bit interval at the • * »times t = (2k-1) T / 2. The signal amplitude given at the k scanning moment has the value s'k = \ -2 g (3T / 2) + ak-i g (T / 2) + + ak + 1 gf-) (5) 20 We choose the unwanted intersymbol interference equal to zero by neglecting the influence of g (t) for t ^ (3T / 2), which is approximated by an equalization filter or by the impulse response of the above-described specific modulation filter GTFM and assumes no distortion here. Equation (5) can then be written as ^ = V1 + hfc (6) in which and = + p and in which p is the magnitude of the 30 pulse pulse response at times t1 + T / 2. the signal shown in expression (6) is a pure trivalent signal, which can be represented by the grating network signal shown in figure 13. Herein the two possible signal signals are indicated by + p, the nodes by a "dot" and the scanning time-35 dots indicated with the running parameter k. As this figure shows, there are two possible signal paths to and from each node.

The length of the signal paths between successive nodes is indicated by "-2p", "0" and "+ 2p" respectively. Thus the path length 8200943 PHN 10,292 16 --- between the states b ^ - p and b ^ = p is equal to "2 p", the road length between b ^ = - p and = - p equal to "-2 p" and the road length between = + p and b ^ = + p equal to "0". It was shown that the probability of erroneously detecting a known signal in the presence of a Gaussian noise to minimize the natural logarithm of the maximum probability function Γ _ ^ -2 "] 2 V * iSk Sx '" "+ 7J (7) 10 i = 0 should be optimized, as can be seen from chapter 6 of the book "Signal Processing" by Mischa Schwartz and Leonard

Shaw, published by McGraw-Hill.

- ds 15 Herein = S + ni the i received signal value in J.

presence of Gaussian noise n., S. is the expected value of S.

1 1 _ _ X

given by relation (6), so that S. = b._1 + b. where (8) i 1 i jL 2. b. 1 and b. the expectations of b. - and B. and is (j J · 'I 1 X I X »a noise term.

Standardization of equation 7 by the signal value gives · V (9) i = 0

2P

The term ^ ^ - is equal to S / N, while the term brackets is independent of the applied signal.

To optimize (9), it is split into two sums and equation (8) is also substituted. , fj- r 7 ë '2 - r F ê 2Ί \ \ x.S. S. X x.S. S. / 3o 1 = (1 ^), - ^ 2. · ¥ -J + ΣΙ ^ J rii = 0 i = n + 1 \ ΓΧΑ-1 + bj> _ Vl + \> 21 (0-2 / L 2p 4 p 35 i— ~ 1 = 0 t ^ iyiük ^. (Vi * siL2]! (10) er2 Z_L 2p «p J 1 'I i = n + 1 y 8200943 EHN 10.292 17 ------- --- Since in the first son of this equation the satmation from i = 0 to i = n contains the terms R of the signals received up to cp at a given moment, equation (10) requires optimization to that particular narent by sequential optimization of these first 5 son.

The signal grating network of equation (10) is shown in Figure 14. The value of the signal path corresponds to the contribution of that signal path to the first sum in equation (10), as shown in the table below.

10

Table

Signal road Contribution to the first node b. node b. .. sum of clarification (10) x i-Ki 15 P P "xi + 1 -p" -p -p ', "" xi + 1 "P" P - P "0"

- P P IIQII

20

Optimization of equation (10) is obtained by choosing the path leading to a node k, which makes the maximum contribution to the first son of equation (10).

25 We define the best way that leads to the node b. = p as the way (i = 0

30 J

and the best way leading to the node = - / 3 if fr r x.s. s.2 ij

Yfe = ^:) 2J -% r] (12) 35 I i = 0 then there are four possible paths on each narent that lead from node i = k to node i = k + 1. These paths are shown in Figures 15a and 15b 8200943 H3N 10,292 18 -. ____

As shown in Figure 15a, the most likely paths leading to the node = p are given by 3 (Yk + xk + l ~ p -P (13.1)

Ykf1 = IIBX_ / Yk + 0 from b ^. = -p (13.2) and fig. 15b shows that the most probable roads to the node. b ^ + 1 = -p data are passed through

Yk + 0 from b ^. = p (14.1) Y “+1 = max. ^

Yk “^ k + i - P \ = -p (14.2)

15 L.

The best path contributing to the first son of formula (10) is therefore given by the maximum of Yk + ^ and Y ^ written as: 20 \ = Y ++ 1, γ- + 1 I (15)

Now follows: from (13) for a path from b ^ = p to b ^ + 1 = p that ^ + ¾ -P> \ or 25 4 - \ * - p 06) so equal to a positive number ü. and for a path from = - p to t ^ + 1 = p that is 30

Yk - Yk + xk + 1 - P (17) and out (14) for a path from = - p to = - p that 36 YkYk + Xk + 1 + P <0 (18)

so equal to a negative number V.

8200943 <HM 10.292 19 ________en for a path of _ ^. = p to ^. + 1 = -p, which is s Yk * Yk + \ +1 + P> ° <19>

Equations (16) to (19) cannot be met at the same time.

We distinguish three possibilities: 10 1 * If equation (16) is true, equation (19) is where equation p is a positive number. This means that = + p leads to = p and £> k = + p leads to = - p

Conversely, this means that if equations (16) and (19) are satisfied, the most probable expectation value is that the data bit transmitted from the k equals b ^ = p.

20 So if y £ - Y ^. + χ ^ + ι - p ^ Q therefore has a value U, then according to (13-1) resp. (14-1) that

Yk + 1 “Yk + \ + i - p - + 25 = Y ^ so that a quantity Z defined as - Y ^ equals Z = x ^ + 1 - p (20) II. If equation (18) is true, then equation 30 (17) is also true, because p is a positive number.

This means that b ^. = - p leads to b ^ = + Ρ and

1¾. = - P leads to I ^ + q = - P

35 the most probable expectation value of the bit transmitted k is equal to - p.

8200943 ΪΉΝ 10.292 20 ____ The necessary condition for this is dar \ - Yk + * k + 1 + p ^ Q '5 so has a value V, then it follows from (13-2) and (14-2) respectively that

Yk + 1 Yk «

, 0 i + 1 "\ \ + i · P

Z = + \ + 1 + P (21) III. Neither equation (16) nor equation (18) is true.

Then equation (17) and equation (19) must be true.

This means that = p leads to = - p and \ - “P leads to b ^ + 1 = p 20

In this case, no clear maximum probable expectation value of the kth element b ^ can be determined.

According to (13-2) and (14-1) it holds that 25 Cl \

Yk + 1 = Yk Z = - (Yk 'Yk> (22) 30 In summary, it holds that according to equations (16), (18), (20), (21) and (22) that r XJcf1 -p for U ^ 0 and 0

Yk + 1 "YkH = 2 = 1 + P for U <0 and V <0 (23) 35, / ~ (ï £" Yk) for U <0 and V ^ 0

A maximum probability detector based on these comparisons is shown in FIG. The signal output by the frequency discriminator 8200943 * -9 a ESN 10.292 21 _____3 at output 4 is fed to an analog-digital ...

converter 17 issued. This converter converts analog input signals cm into, for example, six bit digital signals.

cis

Thus, the signal received at the (k + 1) time is converted into the digital signal x ^. This. signal is supplied to both a first adder 18 and a second adder 19 to which a digital signal of a determined value p from a device 120 is also applied. In the adder 18, by adding the negative number-p to the received signal, the difference signal Z-x-p is determined, as shown by equation (20), which signal is applied to a third adder 20.

Likewise, in adder 19, the sum signal Z - + p is determined, as given by equation (21), which signal is applied to a fourth adder 21.

A first register 22 is also connected to the adders 20 and 21, in which at the time of receipt of

(5.6 M

the (k + 1) bit signal the signal -Z = Yk - is stored, as given by equation (22).

In the adder 20, by adding the + input signals, the signal Yfc - Y ^ + x ^ - p is composed to obtain the signal U given by equation (16).

Likewise, in the adder 21, the signal 4- - Y ^ - Yk + x ^ -j + P is compounded by addition, to obtain the signal V given in equation (18). On outputs 23 and 24 of the adders 20 and 21 a logic circuit 25 is connected.

This logic circuit determines, in a manner to be described in more detail later, from the values of the signals V and V occurring on the outputs 23 and 24 which of the conditions given in equation (23) are presently qp-30.

The detection device comprises a three-tooth switch 27, which is controlled by the logic circuit 25 via a first control conductor 26.

If the logic circuit 25 detects that U ^ 0 and 35 V>; 0, then switch 27 is set to position I via control conductor 26.

In this position, in accordance with the conditions given in equation (23), as a new signal Z, the signal x ^ - p occurring on input terminal 28 is written into register 22 via input 32.

8200943 EHN 10.292 22 _________ However, detects the logic circuit 25 that .........

ü <0 and V <O, then switch 27 is set to position II via control conductor 26. In this mode, in accordance with the conditions given in equation (23), as new signal Z, it becomes. signal x ^ + p occurring on input terminal 29 is entered in register 22 via input 32.

If the logic circuit 24 detects that U <0 and V <0, then switch 27 is set to position III via control conductor 26. At input 30 of switch 27, the output signal multiplied by minus one in the signal-inverting device 31 is at output 43 of register 22. According to equation (23), the signal - (Y ^ - YjJ) present at input 30 is therefore written in register 22. After that, the next received input signal xk + 2 can be processed etc.

The detection device 5 further comprises a data decoding device 48, which contains two shift registers 34 and 35, a logic signal with the value "1" being continuously applied to input 36 of the first shift register 34 and to input 37 of the second shift register 35 continuously provides a logic signal with value "0".

In order to transfer the contents of register 34 to register 35, the logic circuit 25 is connected via a second control conductor 33 to a control input 38 of shift register 34 and shift register 34 is connected to shift register 35 via conductor 40. Likewise, to transfer the contents of register 35 to register 34, the logic circuit 25 is connected via second control conductor 33 to a control input 39 of shift register 35, and shift register 35 is connected to shift register 34 via conductor 40.

The outputs 43 and 44 of the shift registers 34 and 35 are connected to a two-position switch 42, which is controlled by the logic circuit 25 via a third control conductor 45.

The output 46 of this two-position switch 42 is connected to an output register 47 containing two stages. The output 20 can be used to take the decoded data signal.

35 The operation is as follows:

If the logic circuit 25 detects that U ^ 0 and V ^ .0, then the most probable expectation value of the k received data bit is equal to = p as explained above under possibility I in detail 8200943 ESN 10.292 23 -------. The logic circuit 25 instructs via control conductor 33____ and control terminal 38 to feed register 34. the contents of this register via conductor 40 to register 35, which takes this content. The contents of register 34, where a logical value "1" was written in the previous bit time 5, are therefore confirmed as true and entered in both registers.

Thereafter, the contents of both registers are shifted one place, the expectation value "1" being written in the first element of register 34 and the expectation value "0" in the first element of register 35. The switch 42 is also set to position I via control conductor 45, the signal content of the last element of register 34 being written into input 47 via input terminal 46 and the content of this register being shifted one place.

If the logic circuit 25 detects that U <0 and V <0 then 15, the most likely expectation value of the k received data bit is equal to b ^ = -p as explained in detail under possibility II previously. The logic circuit instructs register 35 via control conductor 33 and control terminal 39 to supply register 35 with the content of this register via conductor 41 to "register 34", which takes over this content. The contents of register 35, where a logical value "0" had been entered in the previous bit time, are therefore confirmed as true and appear in both registers. Thereafter, the contents of both shift registers are shifted one place, with the expectation value "1" in the first element of register 34 and the expectation value "0" in the first element of register 35.

Switch 42 is further set to position II via control conductor 45:. wherein the signal content of the last element of register 35 is written into the output register 47 via input terminal 46, the content of this register being shifted one place.

30 Is detected by the logic circuit 25 that

U <0 and V ^ 0 then it is according to the previously described possibility III

it is not possible to determine a clear maximum probable expected value for the k element b ^. In accordance with the equations described therein, the logic circuit 25 instructs both registers 34 and 35 via control conductor 33 35 via control terminal 38 as well as via control terminal 39 to supply their contents via the conductors 40 and 41, respectively, to these contents. The contents of the registers were then exchanged. This means that both possibilities were assumed to be true. Subsequently, the contents of both registers are shifted one place and a value "1" is entered as the most probable expected value in register 34 and a value "0" in register 35. The decision as to which expectation value was correct is therefore shifted a bit time. When determining which of the two registers to read, the logic circuit 25 determines whether Z = Yk + ^ - Y ^ + 1 ^ 0 or <^ 0.

Since this value is stored in register 22 after the switch 27 has been set to position II, the output of 43 of this register is also connected to the logic circuit 25.

If the value of Z is greater than or equal to zero, the logic circuit via control conductor 45 sets the switch 42 to position I. The signal content of the last element of register 34 is then written via input terminal 46 into register 47, the already present content a unit is passed on.

However, if the value of Z is less than zero, the logic circuit 25 sets the switch 42 to position II via control conductor 45. The signal content of the last element of register 35 is then written via input terminal 46 into register 47, whereby the content already present is shifted through one unit.

This decoding process is repeated every bit time.

The data signal thus decoded can be taken from output terminal 10.

The described maximum probability detector 48 is applicable for data not differentially encoded in the transmitter.

For differential coded data, a differential decoder must then be connected to the maximum sensing detector 48. This must be arranged in such a way that 30 b ^ = "1" as dQ = d1 and \ = "O" as dQ φ d1

A logic circuit 25 and electronic switches 27 and 42 connected thereto are shown in Figure 17.

The signals U, V and Z present on the output terminals 23, 24 and 43 are applied to level detectors 48, 49 and 50, which .... determining whether the signals ü, Ven Z applied to them are greater than or equal to 8200943 'I - EHN 10,292 25 ___ to zero or less than zero. If the signals ür V and z __________ are greater than or equal to zero, these level detectors output the logic signal values "1", otherwise the logic signal value "0". From these signals the control-5 signals for switch 27 are derived by the AND-gate circuits 52, 52 and 53. For example, if φ0 and V0 the signal on output 26-1 will be high. If U <0 and V <0 the signal qp output 26-2 are high and if U <0 and V) 0 it. signal on output 26-3 are high. The switch 27 comprises three AND gate circuits 54, 55 and 56, of which first inputs are connected qp the outputs 26-1, 10 26-2 and 26-3 and of which second inputs are connected to the terminals 28, 29 and 30 The outputs of AND gate circuit 54, 55 and 56 are connected via a QF gate circuit 57 to input terminal 32 of register 22. Therefore, this input terminal 32 is supplied with that signal from terminals 28, 29 and 30 whose signal 15 is the corresponding output 26-1, 26-2 or 26-3 is high, in accordance with the previously described operation of logic circuit 25 and switch 27.

From the signal output by level detector 48, a high signal is supplied to terminal 20-1 as U ^ 0 by means of an OR gate 60 and is output from the level detectors 48, 49 and 50 signals via an AND gate circuit 58 and OR- '----. .... gate circuit 60 supplies a high signal to 45-1 if Z> 0, ü <0 and V> 0.

Likewise, via an OR gate 61, a high signal is supplied to terminal 45-2 as V <0, and an AND gate 59 and OR gate 61 provide a high signal to 45-2 as Z <0, U <0 and V> 0.

The switch 42 includes two AND gate circuits 62 and 63, the first inputs of which are connected to the terminals 30 45-1 and 45-2 and the second input terminals of which are connected to the output terminals 43 and 44. The outputs of the AND gate circuits 26 and 63 the input terminal 46 of register 47 is connected via a QF gate circuit 64 qp. Therefore, this input terminal 46 is supplied with that signal from terminals 43 and 44 whose signal qp is the corresponding output 45-1 or 45-2 high, in accordance with the above-described operation of logic circuit 25 and switch 42.

On the outputs of AND gate circuits 51 and 53 8200943 EHN 10.292 26 _____ an OR gate circuit 65 is connected for connecting to control terminal 38 ... _.

supplying a high control signal as either U ^ -0 and V) .0 or as U <0 and v} 0 and the AND gate circuits 52 and 53 have an OR gate circuit 66 connected to the control terminal 39 to supply a high control-5, signal if either V <0 and U <0 or if U <0 and V> 0, according to the above control signals for overwriting and changing / changing the contents of shift registers 34 and 35 .

In view of the digital nature of the exemplary embodiment of the maximum probability detector 10 shown in Figure 16, it is also possible to realize it with the aid of a u-processor.

The improvement of the trivalent signal detection of a TEM modulated signal obtained using the maximum probability detection circuit described in Figure 16 relative to the detection circuit described in Figure 5 which detects "bit by bit" 15 can be read from Figure 18.

In this figure, the bit error probability is plotted as a function of the signal to noise ratio S / N with a bandwidth equal to f ^ with the maximum probability detection represented by curve c) and the "bit-for-bit" detection by curve d). This figure shows that at about two dB in signal-to-noise ratio worse input signal for the maximum probability detection relative to the "bit-for-bit" detection, the same error probability is obtained, from which preference is given for a receiver provided with such a detection method. turns out.

25 30 35 8200943

Claims (7)

A non-coherent receiver according to claim 1, characterized in that the detection device comprises a filter connected to the discrimination discriminator, a level detector coupled to the filter and a decoder connected to the level detector. A non-coherent receiver according to claim 2, characterized in that the filter is an equalizing filter. A non-coherent receiver according to claim 2, characterized in that the filter is a low-pass filter. A non-coherent receiver according to claim 4, characterized in that the level detector is connected to the filter via a double-sided rectifying circuit, the level detector having a single detection level, the decoder is a pulse generator. A non-coherent receiver according to claim 2, comprising a clock pulse regenerator characterized in that the clock pulse regenerator is coupled to the output of the discrimination discriminator for generating a regenerated clock signal output from the discrimination discriminator and is connected to the level detector and 25 the decoder for scanning the filtered signal at times t = (2m - 1). T / 2, where T is the bit time and m is 1, 2, ... etc. A non-coherent receiver according to claim 5, comprising a clock pulse regenerator, characterized in that the clock pulse regenerator 30 has a band-pass filter; connected to the double-sided rectifying circuit and a qp connected to the band-pass filter phase loop and wherein the phase loop is connected to the level detector and the decoder for scanning the rectified signal at times t = (2m - 1). where T is the bit time and m is equal to 35 1f 2, 3, .... etc. A non-coherent receiver according to claim 1, characterized in that the detection device comprises an analog-digital converter connected to the freguity discriminator, a first addition device 8200943 V ΕΗΝ 10.292 28 Λ k ------- connected to the analog. -digital converter for adding a negative number of a certain value to each digital signal delivered by this converter, a second counting device connected to qp contains the analog-digital converter for adding to each am-5 setter digital signal output adding a positive number with a value equal to the absolute value of the determined negative number, comprising a three-tooth switch, the switching arm of which is connected to a first register, a first contact is connected to the first counting device, a second contact is connected to the second counting device and the third contact of which the output of the first register is inverted via a signal device is connected, a third counting device is connected to the first adder and qp contains the first register for adding the signals output from these devices, a fourth counting device is connected to the second counting device and the first register for adding the signals these devices output signals, one on the first register and on the third and fourth counters. connected logic circuit which is connected via a first control conductor to the three-position switch for connecting the first contact to the first register if the signals output by the third and fourth adders are greater or equal to zero, for connecting the second contact with the first register if the signals output by the third and fourth adder are less than zero, and for connecting the third contact with the first register if the signal output by the third adder is less than zero and also the the fourth counting device has a signal of greater than or equal to zero and that the detection device comprises a decoding device comprising a first and a two shift register, a logic signal "1" being continuously supplied to the first stage of the first shift register, and wherein a log is continuously applied to the first stage of the second shift register The signal "0" is applied, the corresponding stages of both shift registers are connected to each other and the logic circuit with a control conductor qp are control terminals of the shift registers. connected for the other 35 control of signals supplied to these control terminals of the signal content of one of the shift registers in the other shift register, comprising a two-position switch, a first contact of which is connected to the output of the first shift register and the 8200943 EHN 10.292 29 * V f! *> f * second contact qp the output of the second shift register is connected ........... and whose switching arm is on one. output register is connected, the logic circuit is connected via a third control conductor on the two-position switch for connecting the output of the second shift register to the output register if the output signal of the third counting device is greater than or equal to zero. output of the first register is greater than or equal to zero and also the output of the third adder is less than zero and the output of the fourth adder is greater than zero and for connecting the output of the third shift register to the output register if the output of the fourth adder is less than zero and if the output of the first register is less than zero and also the output of the third adder is less than zero and the output of the fourth adder is greater than zero. 20 25 30 35 8200943