NL8101410A - Multi processor system with units cooperating on common memory - has interactive system of connections for addresses, data, control data etc. - Google Patents

Abstract

A multi-processor system consists of a number of co-operating processors using a common memory. The memory is supplied with a logic circuit which has the authority to make decisions. The memory system has a number of normal memory positions with conventional reading and writing operations. The intelligent system has connections for addresses, data, control data, etc. It also has addressable bits fulfilling the function of semaphores. The choice of a normal memory address or a semaphores address is carried out by a select semaphore line.

Description

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PHN 9987 1 N.V. Philips' Incandescent lamp factories in Eindhoven.

Intelligent shared memory (s) in a multi-processor system.

The invention relates to a mlti processor system consisting of a number of cooperating processors and a common memory.

Communication between processors can be accomplished in many ways, however the currently available components (eg, microprocessors and peripheral LSI) require additional hardware and software. At the moment, there is not a single LSI component, which apart from as common memory also serves for the integrity of the common data without any additional hardware and software and without unnecessary occupation of the bus, over which the communication with the common memory runs , ensures. The object of the invention is to eliminate the above-mentioned defect.

To this end, the multi-processor system as mentioned in the preamble has the feature that the shared memory is equipped with a device which has decision-making authority ("intelligence").

15 The key point is that the common memory is equipped with at least some intelligence. This is why this memory is referred to as "intelligent shared memory". Abbreviated ISM ("intelligent shared memory").

The invention will be explained in more detail in the following description. The following figures are used for this:

Fig. 1 is the structure of a muiti processor system with an ISM.

Fig. 2 is the functional connection of the ISM in the system of Figure 1.

Fig. 3 shows a test (check) and sets command function diagram.

FIG. 4 shows a move command function diagram.

Fig. 5 shows a function diagram of access to a memory location from a processor.

Fig. 6 shows a function diagram of a convert command of a processor.

In a multi-processor system, the cooperating processors may contain a common memory, optionally in association with a local memory for each separate processor.

Figure 1 shows an example of such a system. Separate bunches are provided for the shared memory ISM and for the local memory 8101410 m * PHN 9987 2 memories IM for each separate processor P1 to Pn. However, it is not important whether the data transmission between a processor and its local memory and the processor and the common memory takes place via the same bus or via separate buses.

The use of the so-called intelligent common memory ISM has a number of advantages and especially a much greater efficiency.

1st Proposal: Intelligent shared memory (ISM).

The connections of the ISM in the system are shown in FIG. 2 is shown.

In principle, the ISM first of all contains a number of normal memory locations, in which the read and write operations take place in the usual manner. For this purpose, the ISM contains connections for addresses, data and control information (write / read, address / valid data). Furthermore, the ISM has 15 m addressable bits, which perform the function of semaphors. The choice of a normal memory address or a semaphore address can be made with a so-called Select Semapbore line (SESE). Finally, n pins Pause (1) to Pause (n) are provided, which can be connected to the corresponding pause pins of n microprocessor chips. Through these 20 pause lines, the ISM has the option of putting a particular processor in pause mode or releasing it from this mode. In addition to the normal write and read kandos, there are 2 more kotmandos, which are sent by the microprocessor to the ISM and can be executed by the ISM, namely: 25 1) Check and move s (i) 2) Move s (i) (where s (i) = semaphore bit with address i).

After these commands have been executed, the ISM can return status information to the microprocessor which executed the commands, so that this microprocessor can check whether the konmando has been properly executed by the ISM. The konmando can reach the ISM via the address lines, the data lines or separate control lines. Together with the kcmmando, the address of the microprocessor that gave the karmando must be issued via address or data lines.

Example: Suppose the ISM has 1024 normal memory locations, which require 10 address lines. However, if SESE = high, the meaning of these address lines is different. At n = 16 2 (maximum number of processors in the systems) and m = 3 (number of semaphore bits) the information on the address lines can be as follows 8101410 EHN 9987 3: 4-SESE (high) type kcranando 4-address 0 ' <- 1 5 processor address ^ 2 <- 3. <- 4 f <- 5 1 <- 6 10 semaphore address / {- 7 4-— 8 <- 9

To clarify the operation of the "check and set" and "set" commands, it is assumed that a FiFO buffer (i) (FiPO = 15 first in, first out) with each semaphore s (i), i = 1 , 2 ..... m, samsnwerkt.

2 operations are possible in this buffer:

FiPO (i): = j: Load the value j into the buffer, j: = FiPO (i): The value of the last element in FiPO (i) belongs to j.

The function diagrams for the Kormandos "check and set" and "set" are shown in Figures 3 and 4. The text in Figures 3 and 4 further speaks for itself.

The possibilities of the intelligent common memory ISM can be extended with a third kotimando: check S (i).

This kcranando tests only the flag S (i) and returns the contents of S (i) to the processor that issued the kcranando.

2nd Proposal: Highly intelligent shared memory (VISM). In the intelligent shared memory ISM it was possible to achieve and modify a memory location without first checking whether that memory location had been used by another processor in a critical section.

In the highly intelligent common memory VISM, a "check and move" command will be executed automatically before access to a normal memory location can be released.

35 The highly intelligent common memory, instead of the flag bits, contains a number of registers: LA. (i), i = 1 ........... m: low address.

HA (i), i = 1, .......... m: high address.

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98 9987 4 PA (i), i = 1, ... ..... M: processor address.

Before the VISM can be applied, it must go through a configuration phase in which these registers can be initialized. It is not important how this configuration takes place; its design 5 may, for example, be indicated by a special corabination of signals on the control lines (Figure 2). In the configuration phase, registers LA (i) and HA (i) with the first resp. last address of an area filled with consecutive memory locations. The registers PA (i) can be filled in the configuration phase with a specific processor address or with a specific code with the meaning "empty".

Each access to a normal memory location is now preceded by certain operations of Figure 4 showing a function diagram of accessing a memory location "a" from a processor j.

A separate koirmando "check and move", r is not necessary, but can be included. The necessary operations for the koimando "move" are shown in Figure 6.

Finally, the CISM also has the ability to perform a "put" kanmando, which returns the contents of PA (i) to the processor that issued the command.

Figure 5 shows that it is first determined whether there is an i for which it holds that the memory location a lies in the region between the high and low addresses HA (i) and LA (i). If such an i cannot be found, access to the memory takes place immediately, or the status information is returned to the processor j.

Figure 6 shows the function diagram of the move (i) bowl mando from processor j. The execution of this command can be protected such that "move i" is only executed if PA (i) = j; otherwise an error condition is returned.

3rd Proposal: Super intelligent, shared memory (UISM).

The VISM allows only one processor to access a critical path. In the UISM, a memory area between LA (i) and HA (i), i = 1 ..... m, can be specified in the channel configuration as follows; (multiple processors, _,, ,, ', can access) .

- dead memory (read only). 3 - a read memory or a write memory (such as VISM).

35 - a write memory or various read memories.

Registers PA (i), HA (i) and LA (i) additionally require a 2-bit descriptor, which can be coded as follows: 00; fixed value.

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PHN 9987 5 01: 1 read memory or 2 write memory.

11: 1 write memory or different read memories.

Furthermore, a 1-bit semaphore WRT (i) is needed, which signals whether a write memory occupies the area, and a general multi-bit semaphore 5 KEftD (i), which indicates the number of write memories qp at a given time.

4th Proposal: Changed waiting mode enter ISM, VISM.

If a processor executes a "check and set" karmando for the ISM and the VISM (explicit for ISM, implicit for VISM), this processor enters the waiting state at a signal qp the PAUSE line. In a system with iris process mode this is not allowed Instead of sending a signal to the PAUSE pen on the microprocessor, the result always consists of only returning state information, so that the local system of the processor ensures that the desired task or procedure is put on hold.

15 20 25 30 35 8 101 410

Claims (1)

EHN 9987 6 Moltiprocessor system consisting of a number of co-operating processors and a common use memory, characterized in that the shared memory is equipped with a device having decision-making power ("intelligence"). 5 10 15 20 25 30 35 8 101 410