NL8004857A - NON-VOLATILE, STATIC, FREE ACCESSORY MEMORY. - Google Patents

Description

-y * * VO 862 i

Non-volatile, static, freely accessible memory system.

The invention generally relates to the field of freely accessible memory systems with metal oxide semiconductor CMOS RAMs, and more particularly to non-volatile static RAM systems comprising a floating gate integrated circuit element 5, in rHt. ·. The context is read as being contained in the Dutch patent applications Nos. 8000 ^ 35 en In fatal static RAMs, bistable semiconductor chains such as flip-flop chains are used as memory cells for storing binary data (ones and zeros). In order for such static 2q memory cells to store information, an electric current from an electric power source must be continuous in one of the two cross-coupled chain branch currents, and relatively absent from the other branch. Two Cbinary distinguishable memory states for information storage are thus provided depending on which branch is conductive and which branch is accordingly non-conductive. Such semiconductor memory cells are therefore considered "volatile" because if the electrical energy is withdrawn, the current for discriminating the memory state ceases to flow in the current carrying 2q branch, and the information in the cell is lost accordingly.

Such volatility is a significant drawback of conventional semiconductor memory systems, and a considerable effort has been made in this area to develop Heten elements and structures to provide non-volatility to semiconductor chains when the energy has been dissipated (E.Harari , et al., "A 256-bit Nonvolatile Static RAM", 1978, IEEE International Solid State Circuits Conference Digest, bl2.l08-1Q9j F. Berenga, et al., "E ^ PROM TV Synthesizer", 1978, IEEE International Solid State Circuits Conference Digest, 196 - 197j M. Horne, et al.,

-Q "A Military Grade 1024-bit Nonvolatile Semiconductor RAM", IEEE

Trans. Electron Devices, Vol. ED-25. No. 8 (1978), biz.1061-1065, ö η nl or 7 "2 ~ Y, Uchida, et al.," 1K Nonvolatile Semiconductor Read / Write RAM ", IEEE Trans, Electron Devices, Vol. ED- 25, No. 8 (1978), biz.1065 -1Q70; D.Frohmann, "A Fully-Decoded 2048-bit Electrically Programmable MOS-ROM", 1971, IEEE International Solid State Circuits 5 Conference Digest, biz, 80 - 81j U.S. Patents 3,660,819, 4,099,196, 3,500,142j Dimaria et al., "Interface Effects and High Conductivity in Oxides Grown from Polycrystalline Silicon", Applied Phys, Letters (1975), biz.505-5Q7j RM, Anderson et al., " Evidence for Surface Asperity Mechanism of Conductivity 10 in Oxide Grown on Polycrystalline Silicon ", J, or Appl. Phys ,,

Full. 48, No. 11 (1977), biz. 4834-4836).

Devices based on the MOS floating gate structure are commonly used for long term data retention systems. A floating gate is an island of conductive material, electrically insulated from the substrate but capacitively coupled to the substrate to form the gate of an MOS transistor. Depending on the presence or absence of charge on this floating gate, the MOS transistor is made conductive (turned on) or non-conducting (turned off), thus forming the ground for storing binary "1" in a memory device "0" data, corresponding to the presence or absence of a floating gate charge. Various means of applying and removing the signal charge from the floating gate are known. When the charge is on port 25, it remains permanently held because the floating gate is completely surrounded by an insulating material, which acts as a barrier against discharging the floating gate. A charge can be loaded onto the floating gate using hot electron injection and / or scavenging mechanisms. Charge can be removed from the floating gate by exposure to radiation (UV light, X-rays), avalanche injection or by so-called scavenging effects. The term "scavenging" is used in a broad sense to include the emission of an electron from the surface of a conductor (including semiconductors) through the energy barrier in an adjacent insulator.

8004857 - 3 -

Non-volatile static RAM memories are known which include a floating gate non-volatile element using a very thin gate oxide, however, these devices have a number of drawbacks. For the charge, a path is made to and from a two-way floating gate element by a relatively thin (5-20 nm) oxide, whose manufacture with sufficient purity can be reliable. Due to the bi-directional action of the very thin roadway oxide, the non-volatile RAM cell may be subject to possible disturbance difficulties which cause fat memory to lose its contents. In particular, such difficulties may include limitations in the number of read cycles and disturbances in a cell's memory contents caused by the operation of adjacent cells. Other non-volatile RAM-15 devices do not use floating gates but instead use a metal nitride oxide semiconductor structure in which charge is retained on a silicon nitride silicon dioxide interface. However, such MNOS devices may also have disturbance difficulties, which not only limit the 20 write cycles as well as the read cycles, causing limitations for the widespread use of MNOS devices,

It is desirable to couple a non-volatile element to a RAM circuit to provide non-volatility in a semiconductor memory array. However, known coupled devices have several important drawbacks. Such a coupling can e.g. are performed by entering a conductivity imbalance caused by the non-volatile element being placed directly between the two branches of a cross-coupled static RAM cell. Such a conductivity imbalance, however, causes the cross-coupled static RAM cell to carry a DC offset current, which must be overcome when the cell is in the usual RAM operation, such imbalances leading to read and write disturbances. general memory chain. Furthermore, such 8 0 0 4 8 5 7 -4-.

marginal phenomena, limitations on production yield and testing difficulties.

Another important factor in coupling the non-volatile elements to static RAM cells is to provide squatness and simplicity to the device design, because these factors affect the size and cabinets of the chain. . Unfortunately, conventional coupling systems tend to require a complicated coupling in control signals and additional transistors, resulting in a large size of the non-volatile static RAM chain and correspondingly high costs.

Several common non-volatile static RAM devices also tend to have the drawback of needing large power requirements and high voltages for operation. These requirements place practical limits on the power and speed of the device, and complicate the chain design. Several known non-volatile static RAM devices also tend to use the semiconductor substrate as the main element in programming the non-volatile memory components, which may include the application of high voltages and strong currents to the RAM line of force to accomplish the non-volatile storage of data so that it is difficult to independently optimize the RAM system design and manufacturing method and separate it from the non-volatile memory system design and manufacturing method. The requirement for an external high voltage power source and strong currents adversely affects the cost, ease of use and general applicability of such conventional, non-volatile RAM memory systems.

When data placed in the non-volatile storage element is recalled to the RAM cell, the data may be further in a complementary or opposite state to that in which the data was originally written in the non-volatile element, to the RAM cell. Such a recall in a complementary state rather than a recall in a direct state is a significant inconvenience that 8004857 * + r - 5 - i must be handled by additional circuitry or otherwise taken into account by the memory system user, The combination of tall cabinets and being difficult to use such conventional, non-volatile RAM memory set has limited the use of non-volatile, static, freely accessible memory systems.

Accordingly, it is an object of the invention to provide improved non-volatile, electrically modifiable, static, RAM integrated circuits, which do not require an external high voltage source or strong current source. It is a further object to provide such non-volatile, integrated, freely accessible memory circuits, which can be configured to use only conventional external transistor transistor controllers with logic level CTTLj.

Another purpose is non-volatile static RAM

which can be performed to draw substantially no DC current from an internally generated high voltage source during programming. It is a further object to provide non-volatile, static RAM chains, containing means for preventing accidental operation of the non-volatile memory during the loading and unloading of a block.

It is yet another object to provide non-volatile static RAM arrays comprising means for selectively transferring data from an entire non-volatile memory array of the integrated circuit array to an associated volatile static RAM array or for transmitting from a single data bit from a predetermined location of the non-volatile memory to a predetermined corresponding location of the RAM on a single logic level command.

The invention is further elucidated on the basis of the designation, in which:

Fig. 1 is a bio-diagram of an embodiment of the present, 1024-bit, non-volatile, electrically modifiable, static, freely accessible memory sequence, * 35 Fig. 2 is a logical accuracy table for the logic control element 8004857 i - 6 of the embodiment shown in Fig. 1;

Figure 3 is a circuit diagram showing the memory chain arrangement of the freely accessible memory array of Figure 1;

Fig. 4 depicts one of the non-volatile, static, freely accessible memory cells of the freely accessible memory array of Fig. 1;

Figure 5 is a circuit diagram of the high voltage generator circuit for the non-volatile memory elements of the memory array of Figure 1; Fig. S is a circuit diagram of the storage control circuit for controlling the high voltage generator circuit of Fig. 5 using the non-volatile memory elements of the memory array of Fig. 1;

Fig. 7 is a circuit diagram of the power source sensing circuit 15 of the memory device of Fig. 1;

Fig. 8 is a circuit diagram of the internal power switch circuit of the memory device of Fig. 1;

Fig. 9 is a circuit diagram of the circuit for generating a bias voltage on a block of the memory device.

20 of FIG. 1;

Fig. 10 is a circuit diagram of the circuit for generating a multiphase signal on a block of the memory device of Fig. 1 together with an illustration of input and output signal waveforms of the circuit; Fig. 11 is a circuit diagram of the output circuit of the memory device of Fig. 1;

Fig. 12 is a circuit diagram of the buffer circuit for selecting a block of the memory device of Fig. 1 *, which circuit is gate-controlled by the power source sensing circuit of Fig. 7;

Fig. 13 is a circuit diagram of the recall buffer circuit of the memory device of Fig. 1;

Fig. 14 is a circuit diagram of another embodiment of a portion of the high voltage generator circuit of Fig. 5; Fig. 15 is a circuit diagram of another embodiment 8004857

* -V

Of the high voltage generator circuit for the non-volatile memory elements of the memory array of FIG.

Fig. 16 is a Circuit diagram of the non-selecting X generator for the memory circuit shown in Fig. 3; Fig. 17 is a circuit diagram of the data buffer / write encoder of the memory device of Fig. 1j

Fig. 1S is a circuit diagram of the write support buffer of the memory device of Fig. 1j

Figure 19 is a circuit diagram of the output-pressurizing generator for the output circuit of Figure 11j.

Fig. 20 is a circuit diagram of a Y-doder, column circuit for the memory circuits terminated in Fig. 3

Fig. 2i is a circuit diagram of the X input buffer circuit for the memory circuit of Fig. 3j and Fig. 22 is a circuit diagram of the Y input buffer circuit for the memory circuit of Fig. 3j.

In general, according to the invention, there are provided non-volatile, electrically changeable, integrated circuit memory devices, which include an addressable volatile memory portion and a non-volatile memory portion associated with the volatile memory portion. The volatile memory portion may include a number of addressable, volatile, freely accessible memory cells for storing binary data.

The non-volatile memory portion may include a number of non-volatile memory cells associated with the volatile memory cells for substantially permanently storing data from the volatile memory cells as a stored charge state upon application of an appropriate storage signal. The non-volatile memory cells and the addressable freely accessible memory cells 30 are cooperatively connected such that upon the application of energy to the freely accessible memory cells, the memory states, represented by the stored charge states of the relevant non-volatile memory cells, are transferred to the Associated volatile memory cells. The freely accessible memory cells and the associated non-volatile memory elements are further connected in a cooperative manner so that upon storage of first memory state data from the volatile memory cells in the associated non-volatile memory cells, and subsequent transfer of the memory states from the non-volatile memory cells to the corresponding volatile memory cells, the volatile cells are returned to their respective initial memory states,

The volatile, addressable, freely accessible memory cells preferably consist of static 4 or 6 transistors 10 transversely coupled flip-flop MQS circuit elements using a relatively low level power source voltage to maintain a desired memory state. The transfer of the memory states from the freely accessible memory cells to the associated non-volatile memory cells is generally accomplished by applying a relatively high voltage control signal to the desired non-volatile memory cell components. This control signal voltage is generally larger and usually considerably greater than the operating voltage applied to the freely accessible memory cells for maintaining the data storage therein. According to the invention, an internal means on the blocks for generating the relatively high voltage storage control signal for the freely accessible memory for transferring to the non-volatile memory is provided, which means is implemented for applying input voltage signals with a relatively low level, such as TTL level signals, to provide the higher voltage control signals used in the non-volatile memory system.

The memory devices further include circuitry means for determining whether externally and internally generated power sources of the memory devices are within a predetermined operating range, and for preventing the application of a storage control signal voltage to the non-volatile memory elements if the external and internal power voltages are not within these ranges. Such agents are effective in preventing loss of non-volatile data due to accidental non-volatile storage operation. In this manner, loss of non-volatile stored data by an unwanted storage signal laying on the non-volatile memory cells is prevented before the correct, effective power source levels are reached or may be insufficient, such as during charging or unloading a block. Such a switching means is an important element in maintaining the accuracy and purity of non-volatile data storage, and the associated reliability and operability of operation compared to external devices.

The memory devices further comprise selectively operable means for automatically transferring non-volatile data from the non-volatile means to the static free access memory in a predetermined manner. Such selectively operable transfer may be performed on a plurality of memory locations or may be arranged to transfer a single selected non-volatile memory cell to the associated addressable freely accessible memory cell. The use of such means in the memory device may be adapted to provide for transferring an entire set or block of memory addresses with data from the non-volatile event to the freely accessible memory under an external operation or program control. Likewise, such selectively operable means may be configured to transfer a single non-volatile data bit from a selected non-volatile memory cell to the associated freely accessible memory cell. Multiple means may be provided for selectively transferring blocks of data or individual data bits 30 other an external control.

The integrated circuit devices generally contain I / Q connection means for resp. input and output of data to sn from the devices. Preferably, such I / O means comprise separate input connection terminals for external electrical connection to the integrated circuit, which may be 8004857 i - 10 in the form of a separate device block, although shared Cdw, multiplexed I / O means. can be used. Instead of including one or more external pin connections, such I / O means may further include means for internally communicating with other integrated circuit elements when the present devices are manufactured with other integrated circuit elements, such as microprocessors, etc. The devices include further, power source terminals for providing a low level potential power source to the device. By "low level" is meant a power source with MOS, ECL or TTL level, which generally does not exceed about 12 V and preferably does not exceed about 5 V in potential. The power source connection means preferably comprise an externally grounded connection terminal with directionally earthed potential conductors, and an external DC power terminal for applying an appropriate operating DC voltage mBt low level for operating the device For devices manufactured according to the n-channel MÜS design using a substrate of mono-20 crystalline silicon eg, preferably a grounded pin and a +5 V DC power source pin are used.

The integrated memory devices may further include a bias power source terminal or an internal bias generating circuit for generating a bias and operating the circuit of the memory device, which may reduce the pin voltage power requirement for the integrated circuit memory device.

As mentioned, transferring the memory state from a volatile memory cell to a corresponding associated non-volatile memory cell as a charge storage state of the non-volatile cell includes applying a signal pulse with a potential which may be significantly more than that of the low-level power source supplied to the integrated chain device.

In this regard, the device further includes high voltage generator-35 means for applying the low level power source for 8004857 * 3 »- π - generating a high voltage signal pulse to effect data transfer from the volatile memory cells from memory to non-volatile cells of memory. The non-volatile memory cells store information as a charge Cof potential state on a dielectrically isolated floating gate structure, the high voltage provided by the generator means being used in transferring charge to or from the floating gate across the di Electric barrier. The present devices are also provided with connection means for providing an external control signal for starting the transfer of data to the non-volatile cells from the volatile cells, whereby the high voltage generator can be made responsive to an appropriate signal which is applied to such a terminal for generating a high voltage pulse for transmitting data with an appropriate command signal applied thereto.

However, the high voltage generator means is further preferably responsive to the power source sensing means, so that the generator means does not provide a high voltage pulse to the non-volatile memory cells when the external power source is not in a predetermined operating range.

It is clear that according to the invention a substantially self-operating, reliable, non-volatile memory device is provided, wherein all external control signals may be relatively low level power and logic signals, such as conventional CTTL1 logic and power sources for transistor to transistor.

In accordance with the invention, a series of non-volatile electrically changeable elements can be provided in a single integrated circuit, which can be fully controlled by logic level signals, and which does not require external high voltage power sources or control signals. In this connection, according to the invention, fully electrically changeable, non-volatile memory devices operating exclusively from external control signals having a TTL level (e.g.

8004857 - 12 -

J

0.8 - 2.2 V), an ECL level Cb.v. 2.1 0.7 V) or a high level MOS Cb.v. 0 - 5 V or 0 - 12 V], The integrated, freely accessible memory circuit (RAM) may be designed to in particular recall any single bit selected from the integrated non-volatile memory CE PROM) or the entire 2 string of the non-volatile E PROM memory can be transferred to the RAM on a single command with TTL or other low level. Furthermore, as mentioned, the RAM of the self-acting memory chain is configured to always charge the contents of the non-volatile E PROM upon application of force to the block. Furthermore, in accordance with the invention, the integrated memory chain is protected from an unintended change of the non-volatile data by a chain means, which excludes memory operation unless externally applied power sources and internally generated power sources have reached appropriate predetermined levels to ensure proper operation. controlled operation. This excludes non-volatile memory loss when e.g. charging or unintentional or unintentional) discharge.

«

The high voltage generator control circuits and internal protection circuits can be used in applications other than RAMs, such as non-volatile electrically changeable ROM devices, memory devices and microcomputers, as will become apparent from the following Description.

Turning now to the drawing, the invention will be further described with respect to embodiments 10 shown in FIGS. 1-22. In this connection, FIG. 1 is a block diagram of the integrated circuit embodiment 10 of the present 1024-hit static , non-volatile, electrically changeable vjpij accessible memory (RAM). The device 10 is an integrated circuit with a plurality of memory locations, and I / O means for addressing the memory locations for data input and output. In this connection, the embodiment 10 comprises a memory array 12 having 32 rows and 32 columns of static, volatile addressable, freely accessible memory cells and associated non-volatile memory cells. The device 10 also has a row of 8004857 - 13 -

Chain means 14 for activating conductive connection to a selected row of the memory string 12, determined by the binary 5-digit number formed by the inputs Ag, A ^, A ^, A0, A ^, and column selection chain means 16 for activating conductive connection to a selected column of the memory string 12, determined by the binary 5-digit number formed by the column selection inputs Ag,

Ag, A7, Ag and Ag. Therefore, the inputs AQ - Ag are memory address lines, which are input connections to the integrated circuit 10. The drive circuit and the column select circuit may have a design common in the IQ and need not be described further. It should be noted, however, that while the illustrated embodiment 10 has five row select and five column select address lines to form a 32 x 32 bit array, other memory sizes can be easily provided. Thus, a 12 x 128 15 bit C16,384 bit] string may e.g. according to the invention are provided using a 7-bit row selection chain architecture and a 7-bit column selection architecture with 14 address lines A0 "A13"

The integrated circuit 10 is further provided with means for 20 hst input and output of data to and from resp. the memory cells of the memory array 12 selected by the row and column select circuit 14, 16. In the illustrated embodiment, these I / O means are in the form of a column I / O circuit 20, which operate is in conjunction with the column selection circuit 16, and may also be of a conventional design. The data input terminal or pin D ^ n provides binary input data to the column I / O circuit 20, wherein the output data terminal Duit provides the output of data from the memory sequence 12 addressed by the row and column selection circuit.

The device 10 further includes logic control means 22, which is provided with block dial, write support, recall storage input signals. Data in CDir |], data from (D block selector CCS], and write support CWVJ are common external I / D control signals for RAM circuits and are associated with external 35Ι / 0 pins of the device. STQRE ^ 8004857 - 14 - input (STO) controls the interaction of the static, freely accessible memory and the non-volatile electrically changeable portion of the device 10, as described more fully below. Recall (RCL) is a signal which can be used to bring a single selected bit from the non-volatile memory to the RAM portion of the memory 12, or to display the entire data contents of the non-volatile memory portion of the memory 12 in the RAM portion of memory Furthermore, both full and selected bitters can be made available to the same integrated chain by simply adding an additional control line. The pin inputs to the device 10 are the grounded pin "GND C which provides an internally grounded voltage Vss] and the power source input voltage pin Vcc having a conventional block TTL level. It is important to note that all the signals described above are logic signals with TT1 level. These are the only input signals to the device 10, which do not require time-generated high voltages and strong currents on one of the control pins of the device 10. More particularly, in this connection, the STORE input (STO] to the logic control means 22, a stem that stores the contained contents of the volatile RAM portion of the memory sequence 12 in the non-volatile portion of the memory sequence device 10. The STORE input may be a low level TTL input signal before starting 25 of the changing the content of the non-volatile memory.

The logic accuracy table for the operation of the logic control means in effecting operation of the device 10 is shown in detail in FIG. 2 with respect to pin inputs with a high (HI or low CL] level, and the operating state of The Apparatus In the conventional RAM circuit for performing the conventional write supports clock dialing operations of RAM systems, the logic control circuit 22 includes means for generating a high voltage pulse, which is particularly suitable for transmission. from 35 the static RAM memory content to the non-volatile memory, 8004857-15 * and means for testing the internal and external power sources, as described in more detail below.

The detailed implementation of the memory sequence aspects of the device 10. showing the cell shape, decoding structure, placement of essential internal signals and I / D circuits, is shown in FIG. 3, The Y decoding, column transfer circuit of the memory array of FIG. 3 is further shown in FIG. .20, wherein the X 'input buffer circuit and the Y input buffer circuit to the array 12 of the row and column I / O circuit 14, 20 and 20, respectively. 10 are shown in FIGS. 21 and 22. The data output circuit of

the memory sequence is shown in FIG. 11, and the data input circuit for the sequence in FIG. Similarly, the control and input circuitry of the logic control means 22 is shown in several of these figures. In this connection, the buffer is for selecting a block for the input signal CS

shown in FIG. 12, the recall buffer for the input signal RCL in FIG. 13, the storage input buffer for the input signal STO in FIG. 6, the X-generator for dialing in FIG. 16, the write-back buffer in FIG. 16 and the output seal pressure generator in fig 20. The power source circuit 24, which is intimately related to the logic control means 22, is also shown in detail in several of these figures. An embodiment of the high voltage generator of the power source circuit 24 is shown in FIG. 5, further preferred embodiments of the high T 25 voltage generator circuit for the device 10 are shown in FIGS. 14 and 15, a reverse bias generator circuit and a circuit for driving of the high voltage generator are shown in Figures 9 and 10, respectively, with a power source sensing circuit and an internal power source switch circuit 30 similarly shown in Figures 7 and 3,

The drawing shows the connection to the ground potential Vss of the external GND pin with a triangular chain, where at the operating input force with low TTL level, direct or indi; rut provided by the Vcc input terminal with a T is shown, with the positive input potential applied when the T. MOSwermeerr and -reducers are distinguished, - 16 -

J

in that the reducing members have a rectangular sign opposite the device gate.

As shown in Fig. 3, the memory array of the device 10 is divided into a right plane 32 and a left plane 34, 5, which planes are substantially two-sided symmetrical, the left plane being shown in more detail in the figure. The left and right planes each contain 16 "columns" with 32 composite memory cells. The row circuit 14 is in the form of a conventional X address circuit 36 for each of the X address lines, operable by applying address inputs Ag - A ^ to the respective inputs Xg - X ^, where Χ ^ 5 is an address signal for excluding any of the X rows from the entire sequence from selection.

An X input buffer circuit 2100 for monitoring and temporarily storing one of the external address inputs Ag - A ^ 15 and providing the associated internal input signals

Xg - X ^, 3Tg-X ^ on the X address circuit 36 is shown in Figure 21. Each of the external address inputs Ag - A ^ is provided with a circuit 2100 for proper connection to the X address lines 370, as shown in Figure 3. Similarly, the external Y address inputs Ag - Ag are each passed through an associated Y input buffer circuit 2200, as shown in Fig. 22, which similarly temporarily stores and conditions the external control signal, and the associated internal address input signals YQ - Y4, YQ - T4 provided for the Y decoders. The column I / 0-25 circuit 20 is implemented in the left and right I / O manifolds 38, 39, respectively. address the memory cells of the right and left memory planes 32, 34. The column selector 16 is implemented in a number of Y decoders, i.e., one for each column, operative in applying address signals Yg-30 from the respective external inputs AQ-A ^. The Y decoder 2000 at the end of the sequence] is shown in FIG. 2Q and includes the gated column pullers 910, the column transfer member 96Q, an inverter 2002 for the gated column pulls, and inverted OR decoder controllers of conventional 35. five-input design, driving about 0.36 pF to 5 V in 6004857 * - 17 - about 40 ns and about 55 yA, and TREK Cin total 1.8 yA). During writing to the addressable volatile memory cell or a "bitter recall" (as described in more detail below) from a selected non-volatile data bit to the addressed volatile memory cell, the column transmitters 960 provide a series resistance of approximately 350 µ from the column 330 to the I / O manifold 38. The gate 2000 inverter turns gate 910 off when the columns are selected to provide a low current and low voltage level (usually less than 0.25 V on both columns and less than 400 yA current from the column withdrawals during the bitter group operation].

The memory string is "separated by the center X decoder 36 into two planes, each containing 16 x 32 cells. The X decoder 36 selects a 32 cell row from 32 rows by increasing cell transfer ports 950 to 5 V , which couples cells 40 to their associated columns. The array similarly includes a number of Y decoders 2000, which members select a pair of columns from the 32 pairs by increasing the column transfer gates 960 to 5 V, which couples columns with their associated Ι / 0 lines.As already indicated, the Y decoder 2000 also turns off the column ramp transistors 910 on the selected columns except for smaller ramps 905 at the top of the string for 25 to a minimum flow limitation The verzam / 0 manifold ± ng retractions 915 in operation replace the column retracts 910, because the columns are electrically coupled to the Ι / 0 manifold through the cooling lom transfer ports 960. The I / O Manifold ·? transmissions 912 are selected by resp. the internal control 30 ports Y4 and ~ 4 for coupling the right or left I / O? bus 38, 39 with the output buffer 1100 · (fig. 11l. The power source voltage in the sequence, shown as Vcca 310, is turned on by a large pull-up device in the Vccar switch circuit 800 (fig. 8i during transfer of memory data from the non-volatile memory to the RAM cells, ZDals is described more fully Dual set of writers 902, 904 receive the write control signals W, W and are used for the left and right I / O bus lines 38 respectively. .39 for reducing the series resistance, especially during the operation of the bitter group and data transferring. The inverters of the members 902, 904 gate the I / O manifold pull-ups on the manifolds which are low which pulls serve as the column pulls for the selected columns C whose pullers were gated off by the Y decoder 10 2000) as well as the write recovery means. During the operation of recalling a selected bit and transferring data, the members 903 pull the I / O bus lines to less than 0.08 V, which increases to about 0.25 V when it is the columns come as a result of the connected resistor C100.CU and the already mentioned organ resistor (350 £ 11, which voltage is still below the 0.3 V series earth potential of the memory series 12.

As indicated and shown in the top left portion of Figure 3, the memory array 12 of the device IQ includes a number of 20 composite memory cells 40, each containing a volatile, addressable, static RAM cell and a non-volatile memory cell , which is related to this in data transmission,

Appropriate, composite, non-volatile, electrically modifiable, static RAM cells are described in Dutch patent application no. 80.00435. A suitable non-volatile RAM cell 40 is shown schematically in Figure 4, and comprises two sections: a non-volatile, electrically changeable section -2 at 42 (E PR0M) and a static RAM section 44. The sectioned RAflr section 44 includes a conventional static memory cell with six transistors in the form of a transverse-coupled flip-flop circuit with two transfer ports for substantially unlimited, directly 2 addressable read / write circuits. The E PROM data is transferred to the RAN cell 44 by a driven capacitive imbalance at the internal flip-flop branch points N1 and N2, which does not cause a difference in the rise time on N1 and N2 during a recall or charge cycle. The rise difference causes the 8004857 i-19 flip-flap circuit to set in a preferred state.

The capacitive imbalance is controlled by the floating gate transistor T1, which switches on or off the capacitor C1 of N1 through gate operation.

2 5 For "recalling" E PROM data, the RAM cell branch points N1 and N2 are grounded, balanced and then released to rise at a rate determined by the current of the reducers and the capacity of the branch points N1 and N2 . In the illustrated embodiment 10, the reduction current can usually be about 7 µm. Similarly, in the illustrated embodiment, the approximate capacitance at the branch point N2 is about 0.1 pF, the capacitance at the branch point N1 being about 0.05 pF without the capacitor C1 and about 0.15 pF if the capacitor C1 with gate operation is connected at branch point N1. Since one of the branch points N2 or N1 rises faster in voltage depending on which branch point has the smaller load, the static RAM cell 44 locks the branch points N2 and N1 in complementary states (high and low voltage), determined by the mutual voltage -20 'difference from N1 and N2.

2

The depicted non-volatile E PROM memory cell is capacitively coupled to the RAM cell 44, and can store data as a charge state on a dielectrically isolated floating gate electrode 46. The depicted non-volatile cell 42 has a three- Polysilicon layer construction overlying the monocrystalline silicon block substrate includes a programming gate 4fl, the floating gate 46, a storage / erase gate 50 and a pn junction in the form of an insulated diffusion plate 52 in the silicon block under the floating gate 46, 30 which is driven by a iiOS organ transistor T2.

2

Erasing and programming the E PROM cells 42 from the device 10 is accomplished by ramping up the "storage" lines 320 by applying an internally generated voltage of about 20 - 40 V in about one ms .

It should be noted that this internal STORE signal, applied to storage block 320 of the memory sequence on the block, is generated when applying the logic signal STO with TTL level to the integrated text 10. The STORE impulse is specially shaped and custom made by a high voltage generator on power unit block S and control circuit 24, a more detailed one. the chain is shown schematically in fig. 5.

The transistor T2, whose gate is directly connected to the branching point N2 of the static RAM cell 44, determines whether the 2ND PROM cell 42 is erased or programmed during a 10 STORE cycle. programming the E PRDM cell 42 the branch point N2 is low (ie a binary zero), the diffusion plate 52, which capacitively coupled to the storage line 320, floats upward and carries the floating gate 46 when the STORE pulse from the power source means 24 15 causes the STORE / ERASE gate 50 to rise. The field of programming gate 48 builds up to the point where electrons travel away from programming gate 48 to floating gate 46, increasing the threshold of transistor T1. Since the cell 42 is capacitively coupled to the RAM cell 44, the programmed, negatively charged 20 'floating gate can be "read" or transferred to the RAM cell 44 as a binary zero. During such transfer, the capacitor C1 decoupled from the branch point N1, allowing the N1 to rise faster than the branch point N2, so that a binary zero is read from the E PROM-25 cell 42 by the RAM cell 44. As mentioned, a binary zero is a low voltage Cb, for example about 0 V) at the branch point N2.

Similarly, the non-volatile memory cell 42 can be "erased" to represent a binary "one". In this regard, when the ram N2 branch point of the RAM cell is at a high TTL voltage (eg about +5 VJ representing a binary "one", the large diffusion plate 52 is held to ground when the STORE pulse is upward, which also capacitively couples the floating gate 46 to substantially ground due to the strong capacitive coupling. When the field 35 between the erase gate 50 and the floating gate 46 sufficiently apologizes, 8004857 r - 21 -} electrons path from the floating gate to the erase / storage gate 50, the threshold of transistor T1 going negative so as to become highly conductive or strongly turned on with respect to the ground voltage supplied to the device 5 through the GND pin input, in a similar interacting manner of capacitive relationship between the non-volatile cell 42 and the addressable static RAM cell 44 is the capacitor C1 during the. re-transferring the "erased" memory state from cell 42 back to cell 44 coupled to branch point N1, allowing N2 to rise faster than branch point N1, and RAM flip-flop memory cell 44 in counter set state relative to that previously described with respect to retransmitting a negatively charged floating gate state. Thus, a binary "one" is read from the E PROM and provides a relatively high voltage at the branch point N2, compared to the corresponding value, which represents a binary zero.

As a result, it is understood that binary data, represented in the conductive form of the RAM cell 44, can be transferred to the non-volatile cell 44, as represented by a charge state of the cell 42, and then immediately returned. are transferred to the cell 44 from the cell 42 to return the cell 42 to its original state when the binary data was originally transferred to the cell 42 from the cell 44. It should also be noted that the memory state of the cell 42 or 44 from which data is transferred or retransmitted is not affected by the transfer or retransmission.

The contents of the static RAM appear on the column lines 30 of the memory array, as shown in FIGS. 1 and 3 after an X selection is made, as is usually accomplished in a six-transistors static RAM cell design.

While the data transfer between the non-volatile cell 42 and the volatile RAM cell 44 has been described with respect to a single memory cell 40 of the memory string 12, it is clear that such data transfer operations can be performed with respect to any of the cells 40 in the series. Thus, data can be fed into the RAM portion of the memory 12, transferred to the non-volatile portion of the memory 5 for substantially persistent non-volatile storage, and transferred back to the RAM portion for reading and application. -sing as desired. In the meantime, the RAM can be used as a conventional addressable RAM. If desired . however, the device 10 may be configured to recall data by transferring the entire E PROM string to the static RAM or by transferring a single selected bit 2 from the E PROM into the associated static RAM memory cell. These different modes of operation can be determined by the means by which the branch points Nt and N2 of the assembled memory cells 40 are grounded in the cell. In this regard, branch points N1 and N2 can be grounded in two ways. According to the first way, the power source Vcca is brought to ground potential to the memory array 12 (Fig. 3), then quickly turned back on C 1 compared to the rise times of the branching points N1 and N2 of the memory cells 40 of the array 121 for 2 recalling the E PRQM data in all composite cells 40 in the sequence 12. The capacitive imbalance between the branch points N1 and N2 then determines the state of the static RAM cell. When the integrated circuit 10 is loaded, it always automatically performs 25 such full data calls and thus has "streams" the data "in the static RAM portion of the memory 12, 2 corresponding to the last one in the E PROM- part written.

In a second mode of operation, the X and Y decoders can select a cell, and both columns 330 adjacent 30 on either side of the selected cell (Fig. 3, 4}) can be brought to earth potential. The X decoder 370 can then be controlled to turn off this cell of its neighboring column 330 by turning off the MOS transistor members 950 so that the branch points N1 and N2 then rise at their proper rates for the recall of the E PROM data in that cell. Thus, in such a mode of operation, data from only one selected cell is transferred from the non-volatile to the volatile portion of the cell.

The Vcca power source 310 and the X-Y decoders 5 are controlled by additional circuits on the block, which circuits are well known simple logic circuits and therefore need not be described further. Certain particular features, however, associated with the Vcca power source and control circuit, are described in more detail with respect to the cycle of the device 10.

As mentioned, the device 10 includes means for generating and controlling various power sources including a relatively high voltage pulse driven to operate the series 12 non-volatile memory cells. In this context, the ones shown in FIG. and 10 illustrated circuits 50, 100 a system for generating and controlling the high voltages used in operating the non-volatile electrically changeable memory cells 42.

The high voltage generator circuit, formed by the circuits 50, 20, 100 of FIGS. 5, 10, provides means for generating a rise-time controlled and level-driven high-voltage impulse which can be easily realized as part of the integrated circuit 10. Such as shown in FIG. 5, the high voltage pulse is generated by a set of diode link stages 52, 25 driven by capacitively coupled low voltage claps 01, 02,

The maximum output voltage is set by a gated diode reference 990, which provides a reference voltage independent of the supplied block voltage GND, Vcc. A feedback circuit 54 is provided which controls the rise time of the high voltage 30 by modulating the active low voltage clock amplitude driving the high voltage generator. A logic level coupling circuit 56 is also provided to detect that the final high voltage level has been reached.

%

In the illustrated embodiment 10, the high voltage generator 35 is driven by non-overlapping biphasic clock signal q η η A q% 7 - 24-

J

Len 01, 02, which are provided by a biphasic clock generator 100, shown in Fig. 10. The biphasic Clock generator 100, in turn, is driven by the overlapping clock signals oi, / & provided by the back bias generator 90 of FIG. 9. The wave-5 shapes of the overlapping input signals ot, to the generator 100 and the non-overlapping output signals 01, 02 are also generally shown in FIG. 10.

As mentioned, the clock signals 01, 02 are used to drive a charge pump oscillator 52 of the generator 50, 10 which includes a plurality of series-connected diode members, which are capacitively coupled to the 01, 02 signals to provide a relatively high voltage output STORE signal 320. In the generator 50, a gated diode is used as a voltage reference source, a feedback circuit is used for controlling pulse rise times, and a high impedance means for detecting a high voltage reference is used for detecting the desired end of the signal. high voltage impulse states. A special feature of the general high-voltage pulse generator chain circuit is that it can record relatively long time constants (~ 1 ms).

The importance of the high voltage generator circuit 50 is that it allows a generally integrated circuit which does not require an external high voltage source. When used as a source in the 2 non-volatile E PROM / RAM device 10, it further provides a shaped and controlled STORE signal level 320. In addition, the circuit makes a simple, non-critical time-driven, compatible logic TTL signal possible to control non-volatile memory operation.

As noted, the illustrated high voltage generator shackles 50 include a 16-stage charge pump oscillator 52 driven by two non-overlapping clocks 01, 02. The illustrated series-connected charge pump positioner slider of FIG. 5 is split three stages from the end, using three minor stages to generate a high voltage control signal HVC, which charges for a certain output impedance prior to high 8004857 - 25 - voltage output signal HV at the output end of the slide row • 52, due to its small load, until it is restored by ·. ' a gated diode 990,

The charging speed of the charging pump oscillator 50 is proportional to the frequency Cf}, the effective build-up ratio Cb.v, 0.35} times 01.02 voltage swing C / \ V] and the ratio of the load capacity on the high voltage output signal to the capacity ^ • value of the pump oscillating capacitor.

It is clear that relatively high voltages C25 - 50 10 V} can in practice be generated from clocks 01, 02 with a relatively low voltage Cb.v. 5 V or less}. Furthermore, the use of simple non-overlapping clock signals 01, 02 provides a simple low voltage means for controlling the charge pump operation and rise time of the high voltage generator 50.

In this connection, the rise time of the output potential becomes HV

sensed, and it generates a control voltage Vp ^ to the clock generator 100, which modulates the amplitude of the charge pump oscillator during signal 01, 02. The fork-shaped split-slide charge pump oscillator design allows the generation of two high voltage signals, HV and HVC , which address different load states for determining desired output voltage states, wherein another output voltage sensing circuit may be provided. In this regard, another circuit design 51 is shown in FIG. 14, using a predetermined capacitive load instead of the split slide charge pump oscillator design in determining a desired output voltage.

While the generator 50 can be used to drive both high and low impedance loads, the generator size is particularly small for high impedance capacitive loads, and particularly suitable as part of the integrated circuit 10. As already mentioned the device 10 contains different power source sensing circuits for controlling the memory operation. Data is stored in the non-volatile 2 35 E PRQM whenever the high voltage STORE signal 32Q is internally generated. During charging or discharging the in-O Λ Λ / nc τ 4> - 26 - direction 10 or in the presence of changing power source voltages, a state may exist in which the input drivers and source voltages are not of sufficient value to unambiguously to be interpreted by the integrated circuit 10, 5 Ambiguous electrical states can occur when a device is outside its usual operating voltages, such as when a device is only turned on or charged or discharged. In a conventional volatile memory device, such states occur when the contents of the memory are in an indefinite state, and must be started during the usual operation of the device, however, in the device 10, the possibility has a direct interaction between its non-volatile memory component. and its volatile, freely accessible memory string-15 component, it is desirable to prevent such interaction during the charge or discharge states of the device for excluding potentially invalid data storage.

In this regard, the device 10 includes circuit means for preventing accidental starting of the STDRE signal in order to prevent accidental storage of invalid data in the E PRQM portion of the memory with an associated loss of the fixed memory during power fluctuations or charging or discharging ·? states.

Such circuit means comprise a power source sensing circuit 24, which includes a logic circuit operative to prevent the storage of data in the non-volatile E PROM portion of the device unless the externally and internally generated force is is in an acceptable, defined area. The logic circuit also provides signals which, when combined with other circuit signals to be described below, are effective for automatically transferring the data in the 2 non-volatile E PROM series to the static volatile RAM portion at lift trays. or falling of the power sources beyond the acceptable certain range.

35 The power source sensing circuit 24 thus makes it possible to charge or discharge 8004857 - 27 - the integrated circuit 10 at any time.

Neatly Chosen Mode Yet Retaining The Non-Volatile E PROM Data, And Restarting The Static RAM At Each Of These Cycles By Automatically Transferring The. 2 5 E PRQM data to the volatile RAM memory devices of the device.

A circuit diagram of a portion 70 of the power sensing circuit 24 with associated logic circuitry is shown in FIG. 7. The Chain 70 includes means 72 for sensing the internal reverse bias potential Vbb of the Chain 10, further means 74 for sensing the external Power Source Vcc provided to the Chain 10 and means 78 for generating logic control signals CPUC ', . PÜlT and PUL2) for controlling the transfer of data from the non-volatile to the volatile. The means 78 also receives a temporarily stored string recall signal CAR) for starting the transfer of data from E PR0M to the RAM.

When the correct voltage levels for the operation of the Chain are satisfied during the operation of the Chain 70, the branch point 71 is high, whereby the logic signals PUL, PUL2 and PUL1 reach levels, which the integrated Chain 10 automatically complete recall when loading the total non-volatile memory data to the volatile static RAM component of the Chain. However, if one of the internal Ex.

25 external Vcc power sources are outside of a predetermined range, which is suitable for reliable operation of the device, the integrated circuit ignores all commands for executing a non-volatile data storage cycle, which converts the 2 data into the non-volatile E PRDM memory part would be different,

Having described Chain 70 in general, its operation is now described in more detail. As mentioned, the external power source Vcc is sensed by the five transistor network 74, provided with an output branch point 35 73. As shown, the Chain 74 includes four MOS attenuator transisto 8004857 - 28 - rsn, which in the illustrated embodiment have nominal width to length ratios. have 6/13, 6/24, 10/6 and 6/20, and a multiplier transistor with a ratio of 30/5, whose output branch 73 has the multiplier transistor with a ratio of 5/5 gate, and the branch point 75 controls. The indicative parameters of the device can be selected to provide correct observation of the input potential Vcc superimposed on the members and the ground potential, as noted. The branch point 75 is located on two inverters from the branch point 71, which is the input of the logic controller 78,

The branch point 75 is also controlled by the Vbb sensing network 72, which consists of two reduction transistors with length / width ratios of resp. 7/5, 75/5. Although the power source potential Vbb may be an external power source, it may also be an internally generated source, such as in the illustrated embodiment 10. In this case, more particularly, it is a source with an opposite polarity of Vcc generated at a block through the circuit 90 of FIG. 9, and is commonly known as the counter-bias source. Generating the counter-bias source on a block eliminates the need for an external source.

Regardless of whether it is generated on a block or provided by an external source, the potential Vbb is applied to the circuit 72 for sensing it. Branch point 75 is accordingly controlled by both power sources Vbb and Vcc 25 in the inverting OR gate shape shown there. The circuit components may be selected to provide desired potential sensing ranges. By way of example, the illustrated transistors are sized so that the logic control input 71 is set when the states of both being greater than about 3.5 V of Vcc are satisfied and being less than about -1.5 V from Vbb.

As mentioned, the logic control input 71 is set when the states of both greater than 3.5V of Vcc and less than -1.5V of Vbb are satisfied, When Vbb goes below -1.5V , the decreasing pull-down transistor 72a 8004857 - 29 -> (75/5) of the Vbb sensing circuit 72 and the adjacent diminishing transistor 72b (7/5) pulls up to the 1.5 V switching point to the next stage (the brackets proportions shown represent examples of the ratios of width to length of 5 members in ym). It is to be recognized, however, that while certain organ parameters may be given, other size ranges and voltage control ranges may be used, as usual for 5 V MQS manufacturing methods using an oxide thickness in the range of 40-100 nm. Similarly, serial reducers 74a (6/13) and 74b (6/24) require the

Vcc sensing circuit 74 a state of greater than 3.5V of Vcc for exceeding liftcl, 6V switching point of the in-digester of the Vcc sensing circuit 74 formed by transistors 74c (10/6) and 74d (30/5) When Vbb is less than -1.5 V 15 and Vcc is greater than 3.5 V, the branch point 75 is high whereby the branch point 71 is high through two inverter stages formed by the members 71a (10/6), 71b (3Q / 5), 71c (10/61 and 71d (30/5), and the logic controller 78 is set to initiate an automatic "SERIES recall" transfer of all 20 memory contents from the non-volatile memory to the corresponding static RAM components of the device 10, followed by a conventional operation of the memory device as long as the correct voltage of Vbb, Vcc is maintained.

In order to ensure clean operation even with relatively slow rise times of the applied potentials Vbb and Vcc, and to ensure significant insensitivity to noise, hysteresis is provided to the two Vbb and Vcc sensing chains 72, 74. When in this regard the branch point 71 of the sensing circuit 70 goes high, the transistor 72c (6/10) shifts from the cut-off Vbb sensing circuit 72 the switching point from -1.5 V to -1.2 V. Similarly, the transistor 74c (6/201 from the Vcc sensing circuit 74 which interacts with members 74c (30/5), 74d (10/6) and 74f (35/51) and which is driven by the branch point 76, the upper switching point from 1.4 to 2.2 V.

This hysteresis prevents frequent repetition of turn-on 8004857-30 and turn-off of the sensing circuit when the system potentials Vcc and Vfab rise slowly through the sensing points of circuit 70.

The logic controller 78 shown is also inverted, so that when the potential of Vcc drops below about 2.8 V, logic control input 71 is reset, which activates automatic "SERIES recall" transfer of the non volatile memory contents to the volatile RAM memory when the potential Vcc rises again, and prevents an unintended attempt to transfer data from the volatile static RAM portion to the non-volatile memory portion of the memory device 12. In this connection, the logic outputs PUL, PUL1 and PUL2 of the power source sensing circuit 70 are provided as various direct or indirect input drivers to the logic control circuit Fig. 1], which includes the buffer 1200 for selecting a block Fig. 121, the recall buffer 1300 Fig. 13), the circuit 80 for controlling the charge storage Fig. 61 and the internal power switch 80 Fig. 8],

Before the logic control input 71 is set in this connection, the logic level output control PUL2 of the displayed logic control circuit 78 is in a high logic state. The high logic state of the logic signal PÜL2 is applied as an input signal to the buffer circuit 1200 for selecting the block Cfig.12], which forms part of the logic control circuit 22 Cfig.I] of the memory device B,

Another input to block selection buffer 1200 is the block selection external signal CS applied from an external terminal of device 10. Applying the high PUL2 logic signal 30 from the logic control circuit 78 of the power source monitors to the logical buffer 1200 for selecting a block squeezes the CS input signal. In the event that the potential Vcc is too low or the potential Vbb is too high, an external RCL signal applied to the device 10, therefore has no effect because the internal CS signal input to the 8004857 - 31 - recall huffer 1300 is high, so that the recall buffer 1300 is closed.

Provided that the internal and external power sources Vbb, Vcc are in operational ranges, the operation of the device 10 is controlled by an external signal to the logic control circuit Fig. 1], the operation of the remote device 10 correspondingly is the accuracy table shown in Figure 2. The input signals include the usual input data signal D i, the signal CS * for selecting a block, and the write support signal W W of a RAM together with the recall signal RCL and the storage signal STO, which are the recall and transfer of storage data start between the volatile and non-volatile parts of the memory sequence 12.

The data input signal Din is supplied to the device 10 via a data buffer, write decoding circuit 1700, using a conventional TTL input stage. The data buffer 1700 is also supplied with internal control signals WE from the WE buffer 1800, and RCL from the recall buffer 1300,

The buffered input data signals D, Ë are directly connected to a write decoder to provide signals W »w * which are also controlled by an internal write support signal WËI. The internal write support signal WE must be low, which occurs during a write command. or bit callback command to enable the write support signals W or W.

25 to go high. During a bitter group operation from non-volatile to volatile data transfer (RCL = high], both D and 0 were drawn low and both W and W went high for writing zeros on both addressed columns.

The external write support signal WE is also applied to a WE buffer 1800 FIG. 18], which has a conventional, compatible TTL input stage and write operation of the volatile memory. section used. Also, the block selection external signal CE is applied to the block selection buffer 1200 to generate internal CS, CS control signals. If the "block" 10 is selected (CS = low] and the WE-on η λ q ς 7 - 32 input is low, the buffered output WE of the circuit 1800 closes the write decode and buffered output WE for activation. of the output blanking generator 1900 Fig. 191 for resetting the output Efet RCL signal from the callback • muffler 1300 is usually low During a recall operation, however, WE is drawn low and WE goes high for writing zeros on opposite columns and Bet resetting the device output In the usual RAM ^ BU.okjekias and write support operations, the control logic of the device ICt 10 is operative to send the data transfer from Set non-volatile to the volatile memory Bctj an external RCL The external RCL signal is applied to the tern group buffer 1300, which generates a logic output signal AR or a logic output signal RCL, depending on the mas reverse logic, used in the manufacture of the Buffer 130Ü. The output logic signals AR and RCL are internal logic signals, respectively. causing all data to be transferred from the non-volatile memory to the static RAM (series recall) or the transfer of a selected [addressed by Ag - Ag in-20 passes) bit of the data to a selected recipient RAM memory cell from its associated non-volatile memory cell (bitter group operation). Furthermore, in this regard, before the logic control input 71 is set, the logic output PUL1 is high, which signal when applied to the logic charge control circuit 60 resets the storage latch 62 of the circuit 60 [to ensure that the block 10 does not rise in the STORE operation), excludes the X-select lines of the memory string 12 via the X-exclude generator 1600 ifig.163 and turns off the internal Vcca power switch 80 [fig. 8].

When the correct Vcc and Vbb force levels are set, when the logic controller 71 of the force sensing circuit 70 [Fig. 7] is set, the output signals PUL2 and PUT go low to activate the device 10. The output signal PUL similarly goes high for activating the Vcca-35 switch 80 Figure 8). The signals PUL, PUL1, PUL2 can then be used with other logic signals to control or exclude different signals until the correct voltages are present, as shown in the drawing.

In this regard, the block selection buffer 1200 shown in FIG. 12 receives the PUL2 input signal, and its operation illustrates some of the features of the integrated circuit 10 and the manner in which the output of the power source sensing circuit 70 can be used.

As mentioned, during charging, the logic output 10 signal PUL2 from the circuit 70 is high until a potential of more than 3.5 V on the power source Vcc and a back bias potential Vbb of less than 1.5 V both are reached. Furthermore, in this connection, the buffer 1200 for selecting a block as logical input signals receives the external CS signal, the STC storage signal. 15 sewing the logic storage circuit 60 (FIG. 6) and the PUL2 signal generated by the power source sensing circuit 70 (FIG. 73). The block selection buffer 1200 outputs internal signals CS and CS for selection. of a block, which signals actually control the selection of the block, the block is accordingly automatically excluded by the buffer 1200 for selecting the block during charging or discharging by means of the high PUL2 signal, as can be seen from a consideration of the buffer circuit 1200 for selecting the block. Similarly, during a STORE operation, the control signal STC of the circuit 60 Cfig.Sj is also high, which also completely excludes the block or device 10.

As indicated, the "lockout" of the device 10v is performed under the control of the internal control signals CS and Tis "generated by the buffer to select a block.

In this connection, the internal block selection signal CS generated by the block selection buffer 1200 in turn forms an input signal to the recall buffer 1300 as does the external input recall signal RCL. When the block is excluded, close the CS (high) sig ^ -35 and sew the WE buffer 1800 (Fig. 18) and the recall buffer 1300 Cfig.

13), and activates the output squeezing generator 1900> - 34 - (Fig. 191 for resetting (ie placing in high impedance operation) the output circuit 1100 (Fig. 11J. The other internal control signal CS for selecting a block generated by the block selection buffer 1200 is similarly used to control the selection of a block je In this connection, the internal signal CS (low) is prevented by the connection to the various internal buffers start a STORE operation, where CS (high] allows the start of a STORE operation.

In FIG. 13, the recall buffer 1300 is shown, indicating how a series recall or bitter recall operates.

As already mentioned, the external RCL logic signal (FIG. 11) can be used to cause a call-back transfer of all non-volatile data to the static RAM from a bitter-group transfer from a non-volatile data bit to a selected RAM cell When only an external RCL input signal is used, the device 10 can be easily fabricated to effect a selected type of transmission, depending on a simple metal masking choice, as indicated by reference numerals 1302, 1304 , wherein the unselected option, as shown, is shorted to ground potential. Recall buffer 1300 may accordingly serve to generate an internal callback call control signal (RCLI or an internal series callback input control signal (AR), however it is also possible to provide both features by simply adding two separate outlets appropriate control signals (e.g. an external stem for a bit recall signal BRCL and an external stem for a series recall signal ARCL) and providing appropriate, two-prong internal logic circuits, such as that of FIG. 13 for each of the external control pins involved.

If the block 10 is selected (ie through the external input CS * = low and RCL * low], the output of the circuit 35 1300 is equal to RCL * high for starting a bitter group 8004857 - 35 * data transfer or AR = high to initiate a series recall data transmission A metal jumper to ground blocks the unused operation of the MASSAGE 13Q2 or 1304.

As mentioned, AR and RCL are the internal control signals generated by the recall buffer 1300, when it is desired to perform a bit recall data transfer operation using the device 10, prior to the recall buffer 1300, which is an operable RCL internal circuit element. contains, Selected by a ·. masRerGiant, the internal bitter group RCL signal of the 10 Reten 1300 is used as an input to the data huffer '1700 Cfig.173 to equalize and internalize the internal data signals D and D, and "write" through the WER buffer 1800 (Fig. 183 of a W * W® 1 on both columns, e.g. columns 330 of cell 40 of Fig. 41 on either side of a selected memory cell, when the applied internal control signal RCL = high The X-lock generator 1600 Cfig.161 is then triggered to generate an appropriate internal X-lock control signal X ^ to lock-out the gate lines of the RAIV memory string Cfig.31 after approximately 20 70 ns, which causes all cells 40 of turns off the column lines 33Q.

In this way, data is transferred [recalled to a selected RAM memory cell from its associated non-volatile memory cell.

When it is desired to perform a sequence recall data transfer operation using the device IQ, for? seeing the recall buffer 1300, which contains an operable internal AR signal generating circuit (by appropriate marking selection as described above, an external RCL signal Claagl is applied to the recall buffer 1300. The internal ARL logir 30 signal, which is thereby provided, is applied as a logic input control signal to the force sensing circuit 7Q, as shown in FIG. 7, to turn off the internal array power source Vcca FIG. 8I to block the start of a STORE for resetting the output of the output switch?

35 1100 1100 Fig. 113 via the output pressing generator 19.QQ

Cfig.191 and for triggering the X-lock? ο η n / q R 7 - 36 - generator 1600 (fig. 161 After about 100 na, the entire event sequence 12 of the illustrated embodiment 10 is at ground potential, and the external control signal RÜL can go high, so that the potential Vcca rises and a sequence recall data transfer 5 - is performed from all non-volatile memory portion data to the associated RAPK memory cells Furthermore, in this regard, the power source sensing circuit 70 (Fig. 71 generates internal logic signals PUL and PUL! Which address the internal sequence recall). signal AR, and in turn drive the Vcca series power source switching circuit 60 (FIG. 8I. Sending the power source Vcca to the event series 12 is the method of ensuring that the non-volatile E PROMr data is properly transferred in Bet

volatile, static RAM ~ memory portion of the device. I.Q

for a charge operation and sequence recall data transfer operations.

The imaged Vcca circuit circuit 60 is designed to draw the entire memory string '12 to above about 2 M in less than about 30 ns, the external power source potential Vcc equal to 3.5 V, and the back bias potential

Vbb is equal to ^ 1.5 V. "The potential Vcca, provided by the 20 switching circuit 80, must rise faster than both the branch r

point IM1 as the branch point N2 in the series of cells 4Q (Fig. 4I

for ensuring the correct return rudder as reliably as possible.

2 pen the data from the non-volatile E PROHr portion to the volatile RAM portion of the memory array 12 of the device 10. In the illustrated embodiment 80, this rise time is achieved by building up the gate of the device 7QQ via a build-up capacitor 710. A further feature of this switch 80 is the intermediate circuit 82, which consists of a small charge pump posillar column circuit driven by a periodic signal waveform, such as a signal A from the generator 100 (Fig. 1Q] to maintain a Relatively high voltage on the gate 70Q even after the dynamic build-up action decreases, hv, when the usual junction leakage occurs, The net result Ia, that the circuit 80 appears to be substantially purely static in operation than dynamic, which is important in providing the antlers 8004857 - 37 -

the relatively fast rise time with respect to the branch points N1 and N2 of the memory cells 40 FIG. 4K

As mentioned, an internal power source for providing a negative bias potential Vbb is provided in the device 10, although this power may also be provided as an external power source, The potential Vbb is applied to the semiconductor (silicon) substrate as a counter bias potential according to usual practice. The Vbb generator 90 of the device 10 is shown in FIG. 9, and includes a three-stage 10 oscillator 92, a large charge pump capacitor capacitor 605, and two diode-connected drivers for effecting charge electron transfer in one direction to the substrate. of the integrated circuit device 10. Two delay elements 660, 650, each with a delay of about 100 ns, are used to set the vibration frequency of the ring ** oscillator 92. of the cut-off member 90 at about 5 MHz.

A driven pull-up stage 500 charges the top plate of the capacitor 605 to a potential of about 5 V, with the "diode" connected member 610 restoring the source / drain diffusions of the circuit 20 to about 1 V. When the output member 620 top plate of capacitor 605 pulls at ground potential, are the source / off? feed diffusions driven to -4 V, If the Vbb output potential is greater than -3 V, the top diode member 615 shown switches on between the integrated circuit backsheet and the reverse bias generator 90, allowing electrons to flow in the backsheet before thus keeping Vbb at a negative voltage.

The illustrated counter-bias generator usually pumps the silicon substrate to a potential of about * 3 V, and draws a current of about 0.5 mA. The (5 MHz) vibration characteristic.

of the three-stage ring oscillator 92 of the bias generator 90 is also used in circuit 10 for operation other than driving the bias biasing of the Vbb po tentially. The illustrated ring oscillator circuit 92 is provided with output lines, originating from points, respectively. between the three oscillator 8004857-38 stages, which accordingly provide two-phase overlapping clock signals cx and .d with the frequency of the oscillator 92.

The biphasic overlapping clock signals oc and / & are applied as input clock signals to the non-overlapping clock generator circuit 5 100 shown in FIG. 10, which provides the non-overlapping clock signals 01 and 02 used by the high voltage pulse generating circuit 50 (FIG. 5, 14 and 15), for generating the high voltage STORE pulse used to transfer data from the 2 volatile RAM memory portion to the non-volatile E PROM memory portion associated therewith.

The 01.02 generator 100 uses the OC and / 3 signals from the Vbb generator 90 to generate non-overlapping 01.02 clock signals for the high voltage generator 50, where the phase relationship is, as shown in general, graphically by fig. 10.

The driver 100 includes two substantially equal intermediate circuits 1002, 1004, for the resp. providing the non-overlapping 01 and 02 clock signals, and two inverters 1006, 1008 for generating inverted C and / 3 signals, respectively. A 20 and B. As already mentioned, the signal A is used to drive the charge pump oscillator intermediate circuit 82 of the Vcca switch 80 Fig. 8]. The B signal shown there is not used in the certain device 10 of FIG. 1, but may be used in place of the A signal or in an additional circuit, if necessary. During a storage operation for writing RAM data 2 into the non-volatile E PROM memory, the 01 and 02 drivers 1002, 1004 each drive an impedance load of about 3.5 pF. The total voltage swing of the 01.02 signals is controlled by the feedback potential signal Vfb of the HV feedback intermediate circuit of the high voltage generator 50, as shown in Fig. 5. The operation of the generator is more particularly described in the Dutch patent application no. 8ΟΟ4852, Qe high voltage generator 50 addresses the external STO input signal, being this external signal which is used to start the STORE operation of the device 10. The external STO input signal is applied to the 8004857 - 39 - STORE buffer circuit 60, which also receives PUL1 and STGRE-HV sensing input signals for generating internal control signals STL, STC, STC for driving the high voltage generator circuit 50 (Cof 1400 or 1500).

5. A particularly preferred embodiment of the high voltage generator charge pump oscillator circuit is shown in FIG. 15, which circuit is similar to circuit 15 of FIG. 5 but includes 32 charge pump oscillator stages 1502, further including a capacitive voltage sense circuit embodiment such as that of FIG. .14 and means 1504 for controlling the voltage of the branch point Na of the gated diode repair circuit 990. The means 1504 is an equated inverter circuit, which provides "tuning" the voltage of the branch point Na of the gated diode repair circuit. 990, which accordingly controls the voltage at which the diode 990 restores and hence the output voltage of the high voltage STORE pulse 320. One end of the inverter circuit 1504 has masking selections 1506, 1500 which shift the recovery voltage. selection 1506 is approximately 31 V, with the recovery voltage of choice 1506 approx if it is 38 V. In manufacturing, one of choices 1506, 1508 is selected to provide the most desired output voltage for the particular device being manufactured.

As already mentioned, the output means of the device containing the column-/ 0 circuit includes means for providing three output states for the device 10. This is accomplished in the illustrated embodiment by means of an output buffer circuit 1100, as shown in fig.

The illustrated output buffer 1100 provides means for placing the output of the direction of the earth at earth potential away from the potential of the external power source Vcc in a high impedance state. The output buffer accordingly provides three states. The output buffer 1100 shown goes to the high impedance state when the signal 0D [pressing the: output-35 output) of the output pressing generator 1900 Cfig. 191 goes high, The signals J, J of the column-/ 0 circuit Fig. 1, 31 - 40 -> are input as signals to the output buffer 1100. The output buffer shown 1100 is a five-stage output buffer circuit, as shown in the drawing, in which the data input signals J, 7 are applied to the stage I of the buffer 1100. The J / overgang transition point usually takes place at 3.5 V, approximately 100 ns after an X address transition in the operation of the device (Figure 3).

Stage I and Stage II of the Device 10 are differential stages, which give a usual small signal gain of about 6 at each stage, and a level shift down about 0.25 V at each stage.

Stage III of the output buffer 1100 primarily shifts the low side level from 2.0 V usually to 0.25 V, and boosts the high side from 3.5 V to 4.9 V. Steps IV and V 15 of the output buffer are "driven" force ramp-down stages to provide good flotation for the large output members.

The data output signal D1 is provided at the output of the stage V of the output circuit 1100, and can be provided at a data output pin or terminal of the integrated circuit 10.

Accordingly, it is clear that an integrated, addressable RAM memory system is provided, which, upon proper command, is capable of reliably and permanently storing volatile, freely accessible memory data in a non-volatile memory array without an external high voltage power source.

The non-volatile stored memory content of the system is automatically and reliably transferred to the volatile, freely accessible memory upon charging of the device or an adjusted external command.

The non-volatile electrically erasable / programmable system is divided with reference to a particular embodiment of the 1024-bit E PROM static RAM device 10 by way of example, involving various changes, modifications and changes of the scheme is clear from the present application. Devices e.g. with a large bit capacity, can be easily provided by expanding the size of the memory array, although the scaled device is particularly adapted to be manufactured in n-channel MOS design guises, using Further, when made of a silicon backing and nominal adhesive minimum design control parameters, other design guises can be used in shaping operating devices comprising several of the present aspects. It is hvv. also 1G capable of producing devices using many of the well known semiconductor methods, such as p-channel SOS Silicon on sapphire or spinel manufacturing and design parameters. Furthermore, although the illustrated embodiment has a single bit bit address or embodiment, it is also clear that the input / output signals of the device can be easily output in a word arrangement (eg 4 or 8 bits wide) as opposed to a single I / O structure A single addressable word recall data transfer operation and transferring the non-volatile data from the associated non-volatile memory cells to one addressed word can be conveniently provided in place of or in addition to the In addition, although the illustrated device 10 is an integrated circuit memory block, further integrated circuits according to the invention may also be used as an intermediate portion of other integrated circuits.

A particularly useful application is as part of a micro-campervan chain, and as a means of replenishing fault-tolerant memory devices. When used as a part of a fun ·? Integrated microcomputer chain provides the non-volatile RAM with a

V

A particular component that can be used in many ways or can improve existing devices. An important use with an integrated microcomputer circuit includes storing system state during discharge to allow restarting operation when charging, and storing of 35 electrically changeable build-up programs for starting the an after a *; 7 2 - 42 system. Another use of the E PROM / RAM chain is in fault-tolerant system or chain designs for adding or omitting parts or for providing a non-volatile map with right and wrong organs.

Although the invention has been described in particular with reference to a particular circuit embodiment, which itself uses argent parameters, which are conventional for a 5 V n-channel MOS device, and designed to provide a prescribed 25 V pulse with a controlled rise time of about 1 ms, 10, many changes, adaptations and modifications are apparent from the present description which are considered to be within the scope and scope of the invention as defined by the claims.

8004857

Claims (12)

1. Non-volatile, electrically changeable, integrated circuit memory device, characterized by means for receiving low level power supply for the device, by recall command connection means for receiving an external recall command signal, by storage command connection means for receiving an external storage command signal, by memory sequence means for storing data, which means comprises a number of addressable, volatile memory cells for storing binary data, and a number of non-volatile, memory cells, associated with the freely accessible memory cells, which are non-volatile memory cells can transmit data from the associated volatile cells upon applying a high voltage storage signal, wherein the volatile memory cells can transmit data from the 15 resp. associated non-volatile memory cells when applying a low-level power source potential to the volatile memory cells, by high voltage generator means responsive to a signal applied to the storage command terminal means for using the low-level power source to generate a high voltage impulse signal for effecting the transfer of data from the volatile to the non-volatile memory cells, by recall means responsive to a signal applied to the recall command connection means for transferring data from at least one of the non-volatile cells to at least one of the volatile cells, and by power source switching means for sensing the low level power source potential and preventing the operation of the recall means, preventing applying a high voltage pulse from the generator means to the memory array means part n and providing a low level potential to the memory sequence means only when the potentials are within a predetermined operating range. The device according to claim 1, characterized in that the ft η n 4 ft ς 7 - 44 power source means provide potential to the device of about 5 V or less, the high voltage generator means providing a high voltage pulse of at least about 20 V . Device as claimed in claim 1, characterized by means 5 for recalling a single addressed bit of the non-volatile memory in the associated freely accessible memory cell. Device as claimed in claim 1, characterized in that the 1/0 connection means comprise an input connection for input of data, and an output connection for output of data from the device, Device according to claim 1, characterized in that the external power source parts comprise an earth connection for receiving an earth potential, and a positive potential connection for receiving a potential with a low voltage level relative to the earth potential. Device according to claim 1, characterized in that the integrated circuit is manufactured on a p * silicon substrate in an n * channel MOS shape. The device of claim 1, characterized by means for generating a bias potential for negative biasing the bottom layer of the device. 8. Device as claimed in claim 7, characterized in that the counter-voltage generator means provide an oscillating multiphase output for generating clock signals for driving the high-voltage generator means, Device according to claim 1, characterized in that the device is designed for receiving external TTLt, 30 high level ECL * or MOS external control signals. Device according to claim 1, characterized in that the memory sequence means have an embodiment with an addressable bit width of 1, 4, 8, 16 or 32 bits, 11. Device according to claim 1, characterized in that the external power supply connection means comprise a counter-bias connection for providing an externally supplied counter-bias potential for the substrate. 8004857