NL7609507A - PROCEDURE FOR APPLYING SUITABLE SEMICONDUCTOR MEMORY BUILDINGS IN A WORK MEMORY MODULE FOR A SUB-FUNCTION, AND DEVICE FOR IMPLEMENTING THIS PROCEDURE. - Google Patents

PROCEDURE FOR APPLYING SUITABLE SEMICONDUCTOR MEMORY BUILDINGS IN A WORK MEMORY MODULE FOR A SUB-FUNCTION, AND DEVICE FOR IMPLEMENTING THIS PROCEDURE.

Info

Publication number
NL7609507A
NL7609507A NL7609507A NL7609507A NL7609507A NL 7609507 A NL7609507 A NL 7609507A NL 7609507 A NL7609507 A NL 7609507A NL 7609507 A NL7609507 A NL 7609507A NL 7609507 A NL7609507 A NL 7609507A
Authority
NL
Netherlands
Prior art keywords
procedure
buildings
implementing
sub
function
Prior art date
Application number
NL7609507A
Other languages
Dutch (nl)
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of NL7609507A publication Critical patent/NL7609507A/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
NL7609507A 1975-08-29 1976-08-26 PROCEDURE FOR APPLYING SUITABLE SEMICONDUCTOR MEMORY BUILDINGS IN A WORK MEMORY MODULE FOR A SUB-FUNCTION, AND DEVICE FOR IMPLEMENTING THIS PROCEDURE. NL7609507A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19752538579 DE2538579B2 (en) 1975-08-29 1975-08-29 PROCESS FOR ENABLING THE USE OF SEMI-FUNCTIONAL SEMICONDUCTOR MEMORY COMPONENTS IN A WORKING MEMORY MODULE AND ARRANGEMENT FOR ITS PERFORMANCE

Publications (1)

Publication Number Publication Date
NL7609507A true NL7609507A (en) 1977-03-02

Family

ID=5955182

Family Applications (1)

Application Number Title Priority Date Filing Date
NL7609507A NL7609507A (en) 1975-08-29 1976-08-26 PROCEDURE FOR APPLYING SUITABLE SEMICONDUCTOR MEMORY BUILDINGS IN A WORK MEMORY MODULE FOR A SUB-FUNCTION, AND DEVICE FOR IMPLEMENTING THIS PROCEDURE.

Country Status (3)

Country Link
DE (1) DE2538579B2 (en)
FR (1) FR2322427A1 (en)
NL (1) NL7609507A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4485471A (en) * 1982-06-01 1984-11-27 International Business Machines Corporation Method of memory reconfiguration for fault tolerant memory

Also Published As

Publication number Publication date
DE2538579A1 (en) 1977-03-03
FR2322427B3 (en) 1979-05-11
FR2322427A1 (en) 1977-03-25
DE2538579B2 (en) 1977-09-29

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Legal Events

Date Code Title Description
BV The patent application has lapsed