NL7108657A - - Google Patents

Info

Publication number
NL7108657A
NL7108657A NL7108657A NL7108657A NL7108657A NL 7108657 A NL7108657 A NL 7108657A NL 7108657 A NL7108657 A NL 7108657A NL 7108657 A NL7108657 A NL 7108657A NL 7108657 A NL7108657 A NL 7108657A
Authority
NL
Netherlands
Application number
NL7108657A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of NL7108657A publication Critical patent/NL7108657A/xx

Links

Classifications

    • H10W20/069
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00Subject matter not provided for in other groups of this subclass
    • H10P95/00
    • H10W20/40
NL7108657A 1970-06-29 1971-06-23 NL7108657A (en:Method)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US050779A US3865624A (en) 1970-06-29 1970-06-29 Interconnection of electrical devices

Publications (1)

Publication Number Publication Date
NL7108657A true NL7108657A (en:Method) 1971-12-31

Family

ID=21967376

Family Applications (1)

Application Number Title Priority Date Filing Date
NL7108657A NL7108657A (en:Method) 1970-06-29 1971-06-23

Country Status (8)

Country Link
US (1) US3865624A (en:Method)
BE (1) BE769050A (en:Method)
CA (1) CA922426A (en:Method)
DE (1) DE2132034A1 (en:Method)
FR (1) FR2096565B1 (en:Method)
GB (1) GB1347410A (en:Method)
NL (1) NL7108657A (en:Method)
SE (1) SE364396B (en:Method)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL166156C (nl) * 1971-05-22 1981-06-15 Philips Nv Halfgeleiderinrichting bevattende ten minste een op een halfgeleidersubstraatlichaam aangebrachte halfge- leiderlaag met ten minste een isolatiezone, welke een in de halfgeleiderlaag verzonken isolatielaag uit door plaatselijke thermische oxydatie van het half- geleidermateriaal van de halfgeleiderlaag gevormd isolerend materiaal bevat en een werkwijze voor het vervaardigen daarvan.
JPS59220952A (ja) * 1983-05-31 1984-12-12 Toshiba Corp 半導体装置の製造方法
US4400867A (en) * 1982-04-26 1983-08-30 Bell Telephone Laboratories, Incorporated High conductivity metallization for semiconductor integrated circuits
JPH06314687A (ja) * 1993-04-30 1994-11-08 Sony Corp 多層配線構造の半導体装置およびその製造方法
US5736457A (en) 1994-12-09 1998-04-07 Sematech Method of making a damascene metallization
US8361856B2 (en) 2010-11-01 2013-01-29 Micron Technology, Inc. Memory cells, arrays of memory cells, and methods of forming memory cells
US8329567B2 (en) 2010-11-03 2012-12-11 Micron Technology, Inc. Methods of forming doped regions in semiconductor substrates
US8431458B2 (en) 2010-12-27 2013-04-30 Micron Technology, Inc. Methods of forming a nonvolatile memory cell and methods of forming an array of nonvolatile memory cells
US8450175B2 (en) 2011-02-22 2013-05-28 Micron Technology, Inc. Methods of forming a vertical transistor and at least a conductive line electrically coupled therewith
US8569831B2 (en) 2011-05-27 2013-10-29 Micron Technology, Inc. Integrated circuit arrays and semiconductor constructions
US9036391B2 (en) 2012-03-06 2015-05-19 Micron Technology, Inc. Arrays of vertically-oriented transistors, memory arrays including vertically-oriented transistors, and memory cells
US9006060B2 (en) 2012-08-21 2015-04-14 Micron Technology, Inc. N-type field effect transistors, arrays comprising N-type vertically-oriented transistors, methods of forming an N-type field effect transistor, and methods of forming an array comprising vertically-oriented N-type transistors
US9129896B2 (en) 2012-08-21 2015-09-08 Micron Technology, Inc. Arrays comprising vertically-oriented transistors, integrated circuitry comprising a conductive line buried in silicon-comprising semiconductor material, methods of forming a plurality of conductive lines buried in silicon-comprising semiconductor material, and methods of forming an array comprising vertically-oriented transistors
US9478550B2 (en) 2012-08-27 2016-10-25 Micron Technology, Inc. Arrays of vertically-oriented transistors, and memory arrays including vertically-oriented transistors
US9111853B2 (en) 2013-03-15 2015-08-18 Micron Technology, Inc. Methods of forming doped elements of semiconductor device structures
US11259402B1 (en) 2020-09-08 2022-02-22 United States Of America As Represented By The Secretary Of The Air Force Fabrication of electrical and/or optical crossover signal lines through direct write deposition techniques

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3386894A (en) * 1964-09-28 1968-06-04 Northern Electric Co Formation of metallic contacts
US3436611A (en) * 1965-01-25 1969-04-01 Texas Instruments Inc Insulation structure for crossover leads in integrated circuitry
US3442701A (en) * 1965-05-19 1969-05-06 Bell Telephone Labor Inc Method of fabricating semiconductor contacts
DE1564705A1 (de) * 1966-09-12 1970-05-14 Siemens Ag Halbleiteranordnung mit mindestens einem in Emitterschaltung betriebenen Transistor
NL161617C (nl) * 1968-06-17 1980-02-15 Nippon Electric Co Halfgeleiderinrichting met vlak oppervlak en werkwijze voor het vervaardigen daarvan.

Also Published As

Publication number Publication date
US3865624A (en) 1975-02-11
DE2132034A1 (de) 1972-01-05
FR2096565A1 (en:Method) 1972-02-18
CA922426A (en) 1973-03-06
BE769050A (fr) 1971-11-03
GB1347410A (en) 1974-02-27
FR2096565B1 (en:Method) 1974-05-31
SE364396B (en:Method) 1974-02-18

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