NL7010211A - - Google Patents

Info

Publication number
NL7010211A
NL7010211A NL7010211A NL7010211A NL7010211A NL 7010211 A NL7010211 A NL 7010211A NL 7010211 A NL7010211 A NL 7010211A NL 7010211 A NL7010211 A NL 7010211A NL 7010211 A NL7010211 A NL 7010211A
Authority
NL
Netherlands
Application number
NL7010211A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of NL7010211A publication Critical patent/NL7010211A/xx

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291Oxides or nitrides or carbides, e.g. ceramics, glass
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
NL7010211A 1969-07-12 1970-07-10 NL7010211A (xx)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5482269 1969-07-12

Publications (1)

Publication Number Publication Date
NL7010211A true NL7010211A (xx) 1971-01-14

Family

ID=12981364

Family Applications (1)

Application Number Title Priority Date Filing Date
NL7010211A NL7010211A (xx) 1969-07-12 1970-07-10

Country Status (3)

Country Link
DE (1) DE2034371A1 (xx)
FR (1) FR2051714A1 (xx)
NL (1) NL7010211A (xx)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4058419A (en) * 1974-12-27 1977-11-15 Tokyo Shibaura Electric, Co., Ltd. Method of manufacturing integrated injection logic semiconductor devices utilizing self-aligned double-diffusion techniques

Also Published As

Publication number Publication date
DE2034371A1 (de) 1971-01-28
FR2051714A1 (en) 1971-04-09

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