NL295627A - - Google Patents

Info

Publication number
NL295627A
NL295627A NL295627DA NL295627A NL 295627 A NL295627 A NL 295627A NL 295627D A NL295627D A NL 295627DA NL 295627 A NL295627 A NL 295627A
Authority
NL
Netherlands
Application number
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Publication of NL295627A publication Critical patent/NL295627A/xx

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K9/00—Demodulating pulses which have been modulated with a continuously-variable signal
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
    • G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
NL295627D 1962-07-23 NL295627A (en:Method)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US211699A US3191013A (en) 1962-07-23 1962-07-23 Phase modulation read out circuit

Publications (1)

Publication Number Publication Date
NL295627A true NL295627A (en:Method)

Family

ID=22787992

Family Applications (1)

Application Number Title Priority Date Filing Date
NL295627D NL295627A (en:Method) 1962-07-23

Country Status (5)

Country Link
US (1) US3191013A (en:Method)
BE (1) BE634316A (en:Method)
DE (1) DE1449427C3 (en:Method)
GB (1) GB1010639A (en:Method)
NL (1) NL295627A (en:Method)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3331051A (en) * 1963-09-30 1967-07-11 Sperry Rand Corp Error detection and correction circuits
US3395355A (en) * 1964-04-16 1968-07-30 Potter Instrument Co Inc Variable time discriminator for double frequency encoded information
US3390284A (en) * 1965-01-22 1968-06-25 Ibm Double frequency detection system
US3418585A (en) * 1965-12-28 1968-12-24 Ibm Circuit for detecting the presence of a special character in phase-encoded binary data
US3670249A (en) * 1971-05-06 1972-06-13 Rca Corp Sampling decoder for delay modulation signals

Also Published As

Publication number Publication date
DE1449427A1 (de) 1969-08-07
BE634316A (en:Method)
GB1010639A (en) 1965-11-24
DE1449427B2 (de) 1973-06-28
DE1449427C3 (de) 1974-01-31
US3191013A (en) 1965-06-22

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