NL292619A - - Google Patents
Info
- Publication number
- NL292619A NL292619A NL292619DA NL292619A NL 292619 A NL292619 A NL 292619A NL 292619D A NL292619D A NL 292619DA NL 292619 A NL292619 A NL 292619A
- Authority
- NL
- Netherlands
- Prior art keywords
- lines
- address
- modulo
- sum
- selecting
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0763—Error or fault detection not based on redundancy by bit configuration check, e.g. of formats or tags
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
- G06F11/104—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error using arithmetic codes, i.e. codes which are preserved during operation, e.g. modulo 9 or 11 check
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/024—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
Abstract
977,134. Error detecting arrangements for matrix stores. MULLARD Ltd. Feb. 11,1963 [May 18, 1962], No. 19287/62. Heading G4C. Error in address-selecting in a matrix store is detected by storing at each word position a set of bits representing the modulo-N sum of the address-selector switch positions, where N is the largest number of positions of any switch. As shown a 12 bit address entered into an address register energizes one out of eight output lines of each of two X and two Y selectors, thus selecting one out of 64 X lines and one out of 64 Y lines. In addition to the data planes, three check planes are provided for storing the modu-8 sum of the four addressing numbers (0-7) and this stored check number is read out on lines S for comparison with the computer modulo-8 sum derived from the address register. A modulo-8 adder built up from half and full adders is illustrated schematically in Fig. 2 (not shown).
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1928762A GB977134A (en) | 1962-05-18 | 1962-05-18 | Improvements in or relating to information storage systems |
Publications (1)
Publication Number | Publication Date |
---|---|
NL292619A true NL292619A (en) |
Family
ID=10126893
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
NL292619D NL292619A (en) | 1962-05-18 |
Country Status (4)
Country | Link |
---|---|
DE (1) | DE1199324B (en) |
FR (1) | FR1357930A (en) |
GB (1) | GB977134A (en) |
NL (1) | NL292619A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3460093A (en) * | 1965-03-31 | 1969-08-05 | Bell Telephone Labor Inc | Selector matrix check circuit |
JPS601639A (en) * | 1983-06-18 | 1985-01-07 | Sony Corp | Signal reproducer |
-
0
- NL NL292619D patent/NL292619A/xx unknown
-
1962
- 1962-05-18 GB GB1928762A patent/GB977134A/en not_active Expired
-
1963
- 1963-05-14 DE DEN23167A patent/DE1199324B/en active Pending
- 1963-05-15 FR FR934906A patent/FR1357930A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
DE1199324B (en) | 1965-08-26 |
GB977134A (en) | 1964-12-02 |
FR1357930A (en) | 1964-04-10 |
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