NL265998A - - Google Patents
Info
- Publication number
- NL265998A NL265998A NL265998DA NL265998A NL 265998 A NL265998 A NL 265998A NL 265998D A NL265998D A NL 265998DA NL 265998 A NL265998 A NL 265998A
- Authority
- NL
- Netherlands
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/504—Adding; Subtracting in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Pure & Applied Mathematics (AREA)
- Mathematical Analysis (AREA)
- Computational Mathematics (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
- Digital Magnetic Recording (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US42114A US3209131A (en) | 1960-07-11 | 1960-07-11 | Computer circuit for performing serial addition and subtraction |
| DEJ0020205 | 1961-07-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| NL265998A true NL265998A (en:Method) |
Family
ID=25982313
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| NL265998D NL265998A (en:Method) | 1960-07-11 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US3209131A (en:Method) |
| DE (1) | DE1302504B (en:Method) |
| GB (1) | GB975958A (en:Method) |
| NL (1) | NL265998A (en:Method) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4380051A (en) * | 1980-11-28 | 1983-04-12 | Motorola, Inc. | High speed digital divider having normalizing circuitry |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US2346616A (en) * | 1940-05-13 | 1944-04-11 | Ncr Co | Multiplying machine |
| NL76345C (en:Method) * | 1947-03-25 | |||
| FR1041729A (fr) * | 1951-04-17 | 1953-10-26 | Electronique & Automatisme Sa | Perfectionnements aux circuits pour l'addition et la soustraction de nombres |
| GB738269A (en) * | 1952-04-16 | 1955-10-12 | British Tabulating Mach Co Ltd | Improvements in or relating to electronic calculating apparatus |
| FR1077056A (fr) * | 1953-03-19 | 1954-11-04 | Electronique & Automatisme Sa | Convertisseur algébrique perfectionné |
| US2962214A (en) * | 1955-11-28 | 1960-11-29 | Epsco Inc | Function generating apparatus |
-
0
- NL NL265998D patent/NL265998A/xx unknown
-
1960
- 1960-07-11 US US42114A patent/US3209131A/en not_active Expired - Lifetime
-
1961
- 1961-06-22 GB GB22583/61A patent/GB975958A/en not_active Expired
- 1961-07-10 DE DE19611302504D patent/DE1302504B/de active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| US3209131A (en) | 1965-09-28 |
| DE1302504B (en:Method) | 1970-10-22 |
| GB975958A (en) | 1964-11-25 |