NL252942A - - Google Patents

Info

Publication number
NL252942A
NL252942A NL252942DA NL252942A NL 252942 A NL252942 A NL 252942A NL 252942D A NL252942D A NL 252942DA NL 252942 A NL252942 A NL 252942A
Authority
NL
Netherlands
Application number
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Publication of NL252942A publication Critical patent/NL252942A/xx

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/14Digital recording or reproducing using self-clocking codes
    • G11B20/1403Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1407Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
    • G11B20/1419Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01Shaping pulses
    • H03K5/04Shaping pulses by increasing duration; by decreasing duration
    • H03K5/05Shaping pulses by increasing duration; by decreasing duration by the use of clock signals or other time reference signals
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/38Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40Transmitting circuits; Receiving circuits
    • H04L25/49Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4904Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Nonlinear Science (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Control Of Electric Motors In General (AREA)
NL252942D 1959-07-01 NL252942A (xx)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US824380A US3114109A (en) 1959-07-01 1959-07-01 Self-clocking system for binary data signal

Publications (1)

Publication Number Publication Date
NL252942A true NL252942A (xx)

Family

ID=25241249

Family Applications (1)

Application Number Title Priority Date Filing Date
NL252942D NL252942A (xx) 1959-07-01

Country Status (6)

Country Link
US (1) US3114109A (xx)
CH (1) CH393420A (xx)
DE (1) DE1127117B (xx)
ES (1) ES259305A1 (xx)
GB (1) GB902450A (xx)
NL (1) NL252942A (xx)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3270288A (en) * 1963-09-18 1966-08-30 Ball Brothers Res Corp System for reshaping and retiming a digital signal
US3488526A (en) * 1966-08-17 1970-01-06 Sylvania Electric Prod Bit synchronizer
US3488478A (en) * 1967-04-11 1970-01-06 Applied Dynamics Inc Gating circuit for hybrid computer apparatus
US3683288A (en) * 1970-07-31 1972-08-08 Texas Instruments Inc Frequency modulation demodulator
US3764920A (en) * 1972-06-15 1973-10-09 Honeywell Inf Systems Apparatus for sampling an asynchronous signal by a synchronous signal
US3935475A (en) * 1974-08-27 1976-01-27 Gte Laboratories Incorporated Two-phase MOS synchronizer
US3959730A (en) * 1974-09-16 1976-05-25 Rockwell International Corporation Digital hysteresis circuit
US4308472A (en) * 1979-12-03 1981-12-29 Gte Automatic Electric Labs Inc. Clock check circuit
US6002280A (en) * 1997-04-24 1999-12-14 Mitsubishi Semiconductor America, Inc. Adaptable output phase delay compensation circuit and method thereof

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2912684A (en) * 1953-01-23 1959-11-10 Digital Control Systems Inc Single channel transmission system
US2714705A (en) * 1953-03-05 1955-08-02 Rca Corp Electronic phase shifting system
US2883525A (en) * 1954-12-10 1959-04-21 Hughes Aircraft Co Flip-flop for generating voltagecouple signals
NL113935C (xx) * 1955-02-23
US2892936A (en) * 1955-11-04 1959-06-30 Burroughs Corp Delay circuit
US2923820A (en) * 1956-10-16 1960-02-02 Rca Corp Phasing system
US2892943A (en) * 1958-03-14 1959-06-30 Robert D Tollefson Multi-pulse synchronizer
NL245387A (xx) * 1958-11-20

Also Published As

Publication number Publication date
US3114109A (en) 1963-12-10
DE1127117B (de) 1962-04-05
ES259305A1 (es) 1960-10-01
CH393420A (de) 1965-06-15
GB902450A (en) 1962-08-01

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