NL2032758B1 - Reducing DFE-induced error propagation impact on soft-input decoding - Google Patents

Abstract

A method for reducing DFE-induced error propagation impact on soft-input decoding; the method comprising: obtaining a sequence of DFE-equalized symbols, the sequence comprising a first symbol and a plurality of following symbols; for each symbol of the plurality of following symbols, determining at least one probability of at least one error state occurring for said symbol, based on an output of the DFE; and demapping the sequence of DFE-equalized symbols, taking into account the determined at least one probability for each symbol of the plurality of following symbols.

Description

Reducing DFE-induced error propagation impact on soft-input decoding

TECHNICAL FIELD

The present disclosure generally relates to reducing decision-feedback equalizer,

DFE,-induced error propagation impact on soft-input decoding. Particular embodiments according to the present disclosure relate to a method and a processing module for reducing DFE-induced error propagation impact on soft-input decoding, and to a related receiver and a related computer program.

BACKGROUND

Increasing bandwidth demands have driven passive optical networks (PON) systems to pursue higher speed. Data centre interconnects are important PON systems, which are currently undergoing a transition from 400Gb/s to 800Gb/s. To achieve data rate 800Gb/s, spectral-efficiency 4-ary pulse amplitude modulation (PAM) along with powerful soft-input forward error correction codes (FEC) such as low-density parity- check (LDPC) codes are crucial elements in the systems [1]. However, the high data rates imply worse inter-symbol interference (ISI). Currently, although simple equalization-scheme decision-feedback equalizers (DFE) can cancel ISI, it inevitably causes error propagation, leading to residual distortions in the equalized 4-PAM signal

[2]. Consequently, error propagation affects the log-likelihood ratio (LLR) distribution which strongly impairs the soft-input FEC decoding performance [3], and thus limits the data rate.

In the presence of DFE, conventional LLR computation assumes only additive white

Gaussian noise (AWGN) imposed on the equalized symbols, and thus result in mismatched LLR. Alternatively, the detrimental impact of mismatched LLR on soft- input FEC decoding can be alleviated by using (1) bit-interleaving or (2) precoding, as is done, for instance, in the IEEE 802.3ca standard [4]. However both of these techniques have drawbacks: interleaving increases latency [5], whilst typically no soft- output is available with a precoding scheme. If not using conventional LLR computation, more accurate LLR computation can be obtained by more sophisticated techniques such as the Bahl-Cocke-Jelinek-Raviv algorithm [6] or the soft-output

Viterbi algorithm [7], but at the cost of high complexity.

[1] V. Gaudet, “A survey and tutorial on contemporary aspects of multiple-valued logic and its application to miscroelectronic circuits”, IEEE Journal on Emerging and

Selected Topics in Circuits and Systems, vol. 6, no. 1, pp. 5-12, Mar. 2016.

[2] R. Narasimha, N. Warke, and N. Shanbhag, “Impact of DFE error propagation on

FEC-based high-speed I/O links”, in Procedings IEEE Global Telecommunications

Conference, Honolulu, HI, USA, Nov./Dec. 2009, pp. 1-8.

[3] A. Mahadevan, Y. Lefevre, W. Lanneer, et al., “Impact of DFE on soft-input LDPC decoding for 50G PON”, in Optical Fiber Communication Conference, San Diego, CA,

USA, Mar. 2021, Paper M3G.5.

[4] “Standard for ethernet amendment 9: Physical layer specifications and management parameters for 25 Gb/s and 50 Gb/s passive optical networks”, IEEE

P802.3ca (2020).

[5] A. Mahadevan, Y. Lefevre, W. Lanneer, et al., “Impact of DFE on soft-input LDPC decoding for 50G PON”, in Optical Fiber Communication Conference, San Diego, CA,

USA, Mar. 2021, Paper M3G.5.

[6] L. Bahl, J. Cocke, F. Jelinek, and J. Raviv, “Optimal de- coding of linear codes for minimizing symbol error rate”, IEEE Transactions on Information Theory, vol. 20, no. 2, pp. 284-287, Mar. 1974.

[7] L. Gong, W. Xiaofu, and Y. Xiaoxin, “On SOVA for non-binary codes”, IEEE

Communications Letters, vol. 3, no. 12, pp. 335-337, 1999.

SUMMARY

It is an aim of at least some embodiments according to the present disclosure to improve the LLR calculation accuracy for decision feedback equalizer (DFE)-equalized channels, and thus increase the system performance significantly.

In a first aspect of the present disclosure, there is provided a method for reducing decision-feedback equalizer, DFE,-induced error propagation impact on soft-input decoding. The method comprises the following steps:

- obtaining a sequence of DFE-equalized symbols, the sequence comprising a first symbol and a plurality of following symbols; - for each symbol of the plurality of following symbols, determining at least one probability of at least one error state occurring for said symbol, based on an output of the DFE; and - demapping the sequence of DFE-equalized symbols, taking into account the determined at least one probability for each symbol of the plurality of following symbols.

In an embodiment, the at least one error state comprises three error states. In a further developed embodiment, the three error states comprise: left-biased, centred, and right-biased.

In an embodiment, the at least one probability comprises a plurality of conditional probabilities corresponding with state transitions between the at least one error state.

In an embodiment, the step of taking into account the determined at least one probability for each symbol of the plurality of following symbols comprises modifying a log-likelihood ratio value corresponding to said symbol.

In a further developed embodiment, the step of modifying the log-likelihood ratio value corresponding to said symbol comprises multiplying both of the likelihoods being ratioed in the log-likelihood ratio with at least one factor representing the at least one probability.

In an embodiment, the step of determining, for each symbol of the plurality of following symbols, at least one probability of at least one error state occurring for said symbol, is based on a value and an estimated error state of the received symbol immediately preceding said symbol.

In a second aspect of the present disclosure, there is provided a processing module for a receiver. The processing module is suitable for reducing decision-feedback equalizer, DFE,-induced error propagation impact on soft-input decoding. The processing module is configured to:

- obtain a sequence of DFE-equalized symbols, the sequence comprising a first symbol and a plurality of following symbols; - for each symbol of the plurality of following symbols, determine at least one probability of at least one error state occurring for said symbol, based on an output of the DFE; and - demap the sequence of DFE-equalized symbols, taking into account the determined at least one probability for each symbol of the plurality of following symbols.

The skilled person will appreciate that analogous considerations and advantages may apply to embodiments of the processing module as for the above-described method embodiments.

In an embodiment, the processing module is integrated with the receiver's DFE.

In an embodiment, the processing module is further configured to perform the steps of any one of the above-described method embodiments.

This may mean that the processing module comprises at least one processor and at least one memory containing instructions corresponding with the various steps of those method embodiments, to ensure that the processing module can perform those steps.

In practical implementations, these instructions may e.g. be loaded on the processing module as firmware, or the processing module may be adapted to use a dedicated hardware solution to execute the instructions, or the processing module may comprise a general-purpose processor (e.g. as part of a general-purpose computer) arranged to retrieve the instructions from a memory (e.g. a long-term storage memory such as a hard drive or a short-term storage memory such as RAM). Although using a general- purpose computer for the processing module may be considered over-dimensioned, this is especially advantageous in simulations.

In a third aspect of the present disclosure, there is provided a receiver comprising a processing module according to any one of the above-described processing module embodiments. 5 In a fourth aspect of the present disclosure, there is provided a computer program comprising instructions adapted for, when executed by at least one processor of a processing module according to any one of the above-described processing module embodiments, causing the processing module to perform the steps of any one of the above-described method embodiments.

The skilled person will appreciate that analogous considerations and advantages may apply to embodiments of the receiver and the computer program as for the above- described method embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

The above-described embodiments will be more fully understood with the help of the following detailed description, which is not intended to limit the present disclosure but is intended to illustrate some of the principles of the above-described embodiments, and with the help of the appended drawings, in which:

Figure 1 schematically illustrates a signal processing diagram using an embodiment of the method according to the present disclosure;

Figure 2 schematically illustrates another signal processing diagram using an embodiment of the method according to the present disclosure;

Figure 3 schematically illustrates a finite state machine, FSM, representing three error states (c, I, and r) as nodes and various conditional probabilities representing state transitions or edges between the nodes; and

Figures 4, 5 and 6 schematically illustrate three plots of performance of various embodiments according to the present disclosure.

DETAILED DESCRIPTION

In a first aspect of the present disclosure, the method comprises several steps, in order to demap DFE-equalized symbols ensuring that the impact on soft-input decoding is reduced. To this end, the method begins with obtaining a sequence of DFE-equalized symbols. This sequence comprises a first symbol and a plurality of following symbols, which means that the following symbols follow the first symbol in the order of the sequence. This distinction is made because the DFE usually does not make a decision for the first symbol of the sequence, as that first symbol lacks a predecessor and may therefore either be accepted as-is, or may follow a convention.

Next, the method of a first aspect of the present disclosure involves a step of determining at least one probability of at least one error state occurring for each symbol of the plurality of following symbols, based on an output of the DFE. In other words, based on what the DFE outputs for the previous symbol or the previous symbols preceding the symbol at hand, the method estimates a number of probabilities of one or more error states occurring for that symbol. This may preferably be done in a recursive manner, which means that the current error state probabilities are determined based on the previous error state probabilities, and the state transition probabilities are computed based on the current received DFE-equalized symbol.

Next, the method of a first aspect of the present disclosure involves a step of demapping the sequence of DFE-equalized symbols, taking into account the determined at least one probability for each symbol of the plurality of following symbols. In other words, the estimated possible error states probabilities are then used to demodulate the equalized symbol. Different error states may be taken into account, and thus the LLR better reflects the error propagation effect on the equalized symbols.

The more accurate LLR in turn benefits the subsequent soft-input FEC decoding, which increases system performance.

In an embodiment, the at least one error state comprises three error states. This has the advantage that, if the SNR is high (because the noise level is low), confusion of symbols would occur mainly between neighbouring symbols, so symbols separated by

0, +d, -d, so it is sufficient to use only three error states. Of course, if SNR would be lower and thus confusion of symbols could occur between symbols farther away from each other, it would be advantageous to use more than three error states, e.g. five or seven error states, or even more error states. In that case, the number of error states would be bounded depending on the chosen modulation (e.g. with 4PAM, there could be up to seven error states).

Figure 1 schematically illustrates a signal processing diagram 100 using an embodiment of the method according to the present disclosure. The data centre interconnect link can be modelled as a partial response (PR) channel 105 with two-tap impulse response [1, a], as shown in Fig. 1. At time instant {, the received symbol is given by yi =x; +ax;-1 +n where n; stands for the AWGN with noise variance §2, and x; belongs to 4PAM symbol set y. The minimum euclidean distance of the 4PAM symbol set is d = 2. Of course, if a different modulation system would be chosen, the value of d would be different.

DFE 103 cancels the ISI in x; by exploiting the previous hard decision (HD) %;_4, and can produce error propagation, which is undesirable. The error produced by DFE is ee; = x; —X;_4, where ¢; € {0, +d, +2d, £3d} (in the case of 4PAM modulation). After the

DFE feedback 101A, 101B, e; can lead to different biased states for y;, which gives yVi=x; +n; + ae.

For high signal-to-noise ratios (SNRs), the majority of errors occur between neighbouring symbols. Hence, the reduced set e; € {0,+d} may preferably be considered to reduce complexity, as it may suffice to consider only three error states.

Of course, if SNR would be lower and thus confusion of symbols could occur between symbols farther away from each other, it would be advantageous to use more than three error states, e.g. five or seven error states, or even more error states. In that case, the number of error states would be bounded depending on the chosen modulation (e.g. with 4PAM, there could be up to seven error states).

The resultant state may therefore be represented as s; € {{,c,r}, which stand for left- biased, centred, and right-biased states, respectively.

The shown method first performs state tracking 102, 106 on the DFE error states.

Compared to standard DFE 101A, 101B, state tracking only requires a recursive operation, as will become more apparent from Fig. 2. The error state probabilities conditioned on the previous equalized symbol are initialized, which may be defined by a vector P; as

P; = [P(silyi-1, Vi-2 si = Ler.

The summation of P; elements is 7 as they represent probabilities of various error states occurring. Usually, the first transmitted symbol x, does not experience ISI and it may therefore be initialized as P, = [0,1,0].

The method may preferably use a finite-state machine to track the evolution of the state probabilities. Figure 3 schematically illustrates such a finite state machine, FSM, representing three error states s; €{l,c,r} as nodes and various conditional probabilities representing state transitions or edges between the nodes. In other words, the nodes and edges indicate the error states and their transitions, respectively.

Two major loops in Fig. 3 characterize the DFE behaviour. The first loop 301 indicates an error-free output, wherein the error state stays at c. The error propagation is shown by the second loop 302A, 302B between [ and r. The state transition probability is defined as Pgs = [P(¥;-1,s:ls;-1)], which depends on the observation of y,_; and §;_;.

To do the recursive inference, one may compute 4;_,, which is a matrix of Pgs. The computation starts with an intermediate matrix B; , By defining an offset ¢, a

Gaussian distribution y,_,~N(£;_; + 9,6%) is assumed, and its probability density function (PDF) is denoted as ¢(¢). When X;,_; = +1, B;_; is given by the matrix " +ad) glad) g(-d+ A

Bi;=| od) p(0) p(=d) p(d— ad) ¢(-ad) p(-d- ad) when £;_1 = —3 or 3, the left or right column of B;_; is set to a zero column vector.

Finally, A; is obtained by doing a row normalization on B;_,. Based on the state transition model, P; then can be inferred recursively, i.e.,

P,=P,_,A._,.

After the state tracking, the method may implement state demapping. The different state probabilities inferred by the state tracking may be used to compute the LLR, such that the effect of error propagation on the past equalized symbols is taken into account.

At time i, the LLR may be computed as — Tex Lsies [rx Oils SJP Gil Va, mea) ’ dze Zsies [rx Oil, s)P(sily1 F2, Fen) where k = 1,2, and y2 c y are 4-PAM symbols labelled by a bit b € {0,1} at position k. frix(¥|x, s) is given by Gaussian distribution y;-N(x; + %,6%), where ¢ = —ad, 0, ad for states [,c, and r, respectively. In other words, the numerator and the denominator of the ratio respectively indicate the probability of transmitting bit k of the j-th symbol as eithera 1 or a 0.

Figure 2 schematically illustrates another signal processing diagram 200 using an embodiment of the method according to the present disclosure. The diagram 200 shows a part of the diagram 100 of Figure 1, using different but equivalent representations. In particular, the figure shows how a DFE-equalized symbol y; is obtained and is on the one hand provided to a demapper 204 directly via path 201, but is on the other hand also used to track error state probabilities in a state tracking DFE 203. To this end, the symbol is delayed y;_, and a state transition matrix A; is generated. Based on the state transition matrix 4;_, and on a delayed iteration of the state probability vector P,_,, the state probability vector P; may be determined 206 and may be provided to the demapper 204, which thus functions as a state demapper, in order to calculate LLRs for decoding.

Figure 2 shows more clearly than Figure 1 how the present disclosure adds a recursive operation in signal processing terms to the operation of a convention DFE, and how the present disclosure enriches the demapper to take into account the error state probabilities.

Figures 4, 5 and 6 schematically illustrate three plots of performance of various embodiments according to the present disclosure. The performance will be numerically evaluated in three aspects: i) equalization; ii) improved demapping; iii) combined equalization, demapping, and decoding performance. The system under consideration is the one depicted in Fig. 1, where a = 0.6. Other schemes are also shown for comparison, including DFE, DFE with bit-interleaving (random interleaving across 4 codewords), and DFE with precoding. In addition, performance in the AWGN channel (ISl-free) is shown as a reference. The disclosed method may be referred as STD for simplicity. The IEEE 802.3ca standard LDPC code is used with blocklength of 17664 bits and code rate 0.83. The decoder receives LLRs and performs belief propagation (BP) with 6 iterations. For precoding scheme, the demapper transforms each HD into a fixed LLR.

In Fig. 4, the pre-FEC BER vs. SNR is plotted. At a BER of 0.02, the disclosed method gains 0.17 dB for DFE due to the improved LLR accuracy. Curve A shows the AWGN, curve B shows a conventional DFE, curve C shows a DFE with interleaving, curve D shows a DFE with precoding, and curve E shows the performance of an embodiment according to the present invention.

Because the performance of conventional DFE (curve B) and DFE with interleaving (curve C) is so close in the illustrated domain and range, curves B and C overlap, and curve C is only barely visible in select areas of the plot. The difference in performance between conventional DFE and DFE with interleaving will be more apparent from Fig. 5 below, where there is more space between them.

Fig. 5 shows post-FEC BER vs. pre-FEC BER. For soft-input FEC, the decoding ability largely depends on the LLR accuracy. Compared using interleaving, the disclosed method can decrease the post-FEC BER by more than three orders of magnitude (3.4 x 1073), performing closer to the AWGN scenario x 16 lower BER).

Post-FEC BER vs. SNR is shown in Fig. 6. The disclosed method may outperform interleaving and precoding schemes. Compared to interleaving, STD gives an extra gain of 0.76 dB for DFE at a BER of 107°. Although DFE with precoding reduces pre-

FEC BER, its post-FEC performance is the worst due to the LLR quantization. Finally, a gap of 1.57 dB between the DFE with STD scheme and the AWGN performance can be observed.

The complexity of the proposed LLR computation may be decreased even further with the adoption of a PDF lookup table for the state tracking (to speed up determining the

PDFs), and/or ii) replacing the log-sum-exp computation of the LLRs with the max-log approximation (to speed up calculation).

Claims (12)

CONCLUSIONS 1. Method for reducing decision feedback equalizer, DFE,-induced error propagation impact on soft-input decoding; which method comprises: - obtaining a sequence of DFE-equalized symbols, which sequence comprises a first symbol and several subsequent symbols; - for each symbol of the plurality of subsequent symbols, determining at least one probability of at least one error condition occurring for said symbol, based on an output from the DFE; and - demapping the sequence of DFE-equalized symbols, taking into account the determined at least one probability for each symbol of the plurality of subsequent symbols. Method according to claim 1, wherein the at least one error condition comprises three error conditions. The method of claim 2, wherein the three error states include: left-facing, centered, and right-facing. Method according to any preceding claim, wherein the at least one probability comprises multiple conditional probabilities corresponding to state transitions between the at least one error state. A method according to any preceding claim, wherein the step of taking into account the determined at least one probability for each symbol of the plurality of subsequent symbols includes modifying a log-likelihood quotient value corresponding to said symbol. Method according to claim 5, wherein the step of changing the log-likelihood quotient value corresponding to said symbol comprises multiplying both likelihood functions quotiented in the log-likelihood quotient by at least one factor representing the at least one likelihood . A method according to any preceding claim, wherein the step of determining, for each symbol of the plurality of subsequent symbols, at least one probability of at least one error condition occurring for said symbol is based on a value and an estimated error condition of the received symbol immediately preceding the said symbol. 8. Receiver processing module for reducing decision-feedback equalizer, DFE,-induced error propagation impact on soft-input decoding; which processing module is designed for: - obtaining a sequence of DFE-equalized symbols, which sequence comprises a first symbol and several subsequent symbols; - for each symbol of the plurality of subsequent symbols, determining at least one probability of at least one error condition occurring for said symbol, based on an output from the DFE; and - demapping the sequence of DFE-equalized symbols, taking into account the determined at least one probability for each symbol of the plurality of subsequent symbols. 9. Processing module according to claim 8, wherein the processing module is integrated with the DFE of the receiver. 10. Processing module according to claim 8 or 9, wherein the processing module is further designed to perform the steps according to any of the claims 2-7. 11. Receiver comprising a processing module according to any one of claims 8-10. 12. Computer program comprising instructions adapted to, when executed by at least one processor of a processing module according to any one of claims 8-10, cause the processing module to perform the steps of any of the methods of claims 1-7.