NL2031859B1

NL2031859B1 - Polyphase converter with high-frequency isolation

Info

Publication number: NL2031859B1
Application number: NL2031859A
Authority: NL
Inventors: Huber Jonas; Menzi David; Walter Kolar Johann; Everts Jordi
Original assignee: Eth Zuerich; Prodrive Tech Innovation Services B V
Priority date: 2022-05-13
Filing date: 2022-05-13
Publication date: 2023-11-20
Also published as: WO2023218059A1

Abstract

Polyphase converter with high-frequency isolation Electrical converter comprising a first converter stage connected to a plurality of first converter terminals. The first converter stage comprises, for each of the plurality of first converter terminals a switching cell and a second capacitor. The switching cell comprises a first capacitor, having a first capacitor terminal connected to the corresponding first converter terminal and a second capacitor terminal connected to a star-point common to the first capacitors, an upper node connected to the first capacitor terminal, a lower node connected to the star-point and an intermediate node switchably connected to the upper node and the lower node. The second capacitor has a first capacitor terminal connected to the intermediate node and a second capacitor terminal forming an interface node of the first converter stage, wherein the electrical converter comprises a control unit to operate the switching cells so as to convert between a polyphase AC voltage signal at the plurality of first converter terminals having a first frequency and a polyphase amplitude-modulated voltage signal at the interface nodes having a carrier frequency substantially higher than the first frequency, and such that a differential mode of each phase of the polyphase amplitude-modulated voltage signal is modulated based on an amplitude of a corresponding phase of the polyphase AC voltage signal.

Description

Polyphase converter with high-frequency isolation

Technical field

[0001] The present invention is related to polyphase AC-DC and AC-AC converters with an integrated high-frequency isolation.

Background art

[0002] It is known from US 8446743, 21 May 2013 to provide a power electronic transformer having a high-frequency link. A transformer having a primary winding and a secondary winding is configured to receive a primary power signal having a first frequency. A primary converter is configured to selectively oscillate polarity of the primary windings with respect to the secondary windings at a second frequency, the second frequency substantially higher than the first frequency. A secondary converter is coupled to the secondary winding and is configured to provide a load power signal by converting the high frequency power signal generated using the secondary winding. The secondary converter can be configured to reduce current flow in the primary winding when the polarity of the primary winding is switched, the reduced current flow is configured to reduce disturbances resulting from leakage inductance of the transformer.

One disadvantage of the above solution however is that the use of center-tapped transformer primary windings implies a bad utilization of the transformer. Furthermore, the switching elements of the primary converter are such that high conduction losses occur and additional snubber elements are needed to prevent overvoltages across these switching elements.

[0003] US 2021/01881086, 24 June 2021 discloses AC to AC and AC to DC converter systems for wireless power transfer via air-coupled inductive coils. At the transmitter side, a grid-voltage signal is received that is single-phase or three-phase, and a modulated high-frequency voltage signal is produced that includes a high-frequency carrier signal having an envelope with grid-voltage fundamental frequency. The modulated high-frequency voltage signal is wirelessly transmitted to a receiver. In the specific case of a three-phase AC to AC or AC to DC converter, the switching circuitry of the power supply of the transmitter is driven with 50% duty cycle and 120° phase shifted pulse-width modulation (PWM) carriers, resulting in opposite gate signals during positive and negative cycles of the grid for upper and lower switching legs. More specifically, looking at Figs. 42 and 54 of US 2021/0188106, the PWM signals for each phase leg show a discontinuous portion in which the gate signals of the upper and lower switches are clamped in complimentary ON and OFF states respectively. The discontinuous portion of the PWM signals is applied when the corresponding phase of the grid is in the negative half-cycle and hence the PWM signals are phase shifted over 120° between the three phase legs. The grid-side fundamental frequency and a high frequency switching signal are superimposed through a resonant compensation network and coupling coils, such that the fundamental frequency is transferred to the AC load. While

US 2021/0188106 describes that the modulated high-frequency voltage signal produced at the resonant tank terminals of the transmitter includes a high-frequency carrier signal having an envelope with grid-voltage signal, from the simulations it can be derived that the envelope is not symmetrical with respect to the 0 V axis.

[0004] Furthermore, the above converter system requires a compensation network connected to the terminals of the inductive coils at the primary and secondary side that ensures resonant tuning. This compensation network comprises inductors and capacitors in series or in parallel in which the capacitor values are tuned to compensate, e.g., a downstream transformer’s stray inductance for resonant operation. Specifically, an LCC compensation network is described. One drawback of such a compensation network is that the power flow cannot be regulated.

Summary

[0005] It is an aim of the present disclosure to provide a polyphase AC to

AC or AC to DC converter which overcomes the above drawbacks. Specifically, it is an aim to provide such a converter which provides high frequency and possibly galvanic isolation in an easy and compact manner, with reduced hardware count, easier control and/or reduced switching losses.

[0006] According to a first aspect of the disclosure, there is therefore provided an electrical converter as set out in the appended claims. An electrical converter according to the present disclosure comprises a plurality of first converter terminals and a first converter stage connected to the plurality of first converter terminals. The first converter stage comprises, for each of the plurality of first converter terminals, a switching cell and a second capacitor. The switching cell comprises a first capacitor, having a first capacitor terminal connected to the corresponding first converter terminal and a second capacitor terminal connected to a star-point common to the first capacitors, an upper node connected to the first capacitor terminal, a lower node connected to the star-point and an intermediate or switch node switchably connected to the upper node and to the lower node. The second capacitor comprises a first capacitor terminal connected to the intermediate node and a second capacitor terminal forming an interface node of the first converter stage. Each switching cell can comprise an upper controllable switch device connecting the upper node to the intermediate node and a lower controllable switch device connecting the lower nade to the intermediate node.

[0007] The electrical converter can further comprise a plurality of second converter terminals and possibly a second converter stage connected to the plurality of second converter terminals. The second converter stage comprises a plurality of interface nodes coupled to the interface nodes of the first converter stage. The electrical converter can be configured to convert between a polyphase AC voltage signal at the plurality of first converter terminals and a second signal at the plurality of second converter terminals, which can be a polyphase AC signal, preferably of equal number of phases as the polyphase AC voltage signal at the first converter terminals, one or a plurality of single-phase AS signals or one or a plurality of DC signals.

[0008] The electrical converter further comprises a control unit configured to operate the switching cells so as to convert between the polyphase AC voltage signal at the plurality of first converter terminals having a first frequency and a polyphase amplitude-modulated voltage signal at the interface nodes of the first converter stage having a carrier frequency substantially higher than the first frequency. The control unit is advantageously configured to operate the switching cells such that a differential mode of each phase of the polyphase amplitude-modulated voltage signal is modulated based on an amplitude of a corresponding phase of the polyphase AC voltage signal. The differential mode signal of each phase of the polyphase amplitude-modulated voltage signal has thus an envelope which is advantageously defined by, and in phase with the corresponding phase of the polyphase AC voltage signal at the first converter terminals.

[0009] To obtain the polyphase amplitude-modulated voltage signal at the interface nodes of the first converter stage, the control unit is advantageously configured to operate the switching cells of the first converter stage synchronously, particularly with opposite switching signals for upper and lower controllable switches. Advantageously, the control unit is configured to superimpose on the synchronous switching signal, an individual compensation signal for each switching cell individually, wherein the compensation signal is based on an error signal between a measured common-mode offset voltage and a reference common-mode offset voltage.

[0010] Alternatively, the control unit is configured to operate the switching cell respective of a phase of the polyphase AC voltage signal having a lowest instantaneous voltage value in a clamping mode. The clamping mode is defined by a transitioning of both upper and lower controllable switches of the switching cell to an ON state. Hence, the intermediate node is continuously connected to both the first capacitor terminal of the first capacitor and to the common star-point. Advantageously, the remaining switching cells are operated synchronously.

[0011] The interface nodes of the first converter stage can be directly connected to the interface nodes of the second converter stage, particularly without any energy storage elements between them. Alternatively a magnetic transformer comprises primary windings with terminals connected to the interface nodes of the first converter stage and secondary windings with terminals advantageously connected to the interface nodes of the second converter stage. The first converter stage is advantageously operated with a switching (carrier) frequency that is outside a resonant operating range defined by the second capacitor and the primary winding connected to the corresponding interface node. Such a resonant operating range can be defined by the resonant frequency of the LC system defined by the second capacitor and the corresponding primary winding of the transformer. The resonant operating range advantageously is between 75% and 125% of the resonant frequency. The switching (carrier) frequency hence is advantageously 75% of the resonant frequency or less, or 125% of the resonant frequency or less, and can be 25% of the resonant frequency or less, or 400% of the resonant frequency or less. Alternatively, the first converter stage is operated with a switching frequency within resonant operating range.

[0012] Advantageously, the second converter stage is configured to operate such that currents at the interface nodes of the second converter stage have local average values proportional to local average values of corresponding voltages of the polyphase amplitude-modulated voltage signal appearing at corresponding interface nodes of the first converter stage. A local average value can refer to a value that is averaged over half a switching period.

[0013] Electrical converters according to the present disclosure allow obtaining galvanic separation in a compact way by providing a converter stage with switching cells allowing to chop each phase of an applied polyphase AC voltage signal separately and connecting the output terminals (switch nodes) of the switching cells to series capacitors without requiring magnetic components. The converter stage allows converting between the polyphase AC voltage signal and a polyphase amplitude- modulated voltage signal at the output terminals of the series capacitors in which a differential mode of each phase of the polyphase amplitude-modulated voltage signal is modulated based on an amplitude of a corresponding phase of the polyphase AC voltage signal. At each of the output terminals of the converter stage hence an amplitude- modulated differential mode signal is obtained that is advantageously modulated by the corresponding phase input voltage signal only. This allows easy processing of the amplitude-modulated polyphase voltage signal at subsequent converter stages to reconstruct each phase of the polyphase AC voltage input signal.

[0014] Furthermore, electrical converters according to aspects of the present disclosure employ simple pulse-width modulation schemes allowing to reduce 5 switching losses and/or control common-mode voltage offset drifts.

[0015] Advantageously, electrical converters of the present disclosure do not need to be operated in a resonant mode, and the capacitor values of the series capacitors do not need to be tuned to any downstream inductance, allowing to optimize component selection.

[0016] Key features of the electrical converters of the present disclosure are one or more of: - galvanic separation between input and output; - ohmic grid behavior (cos @ = +1); - compact realization / single-stage power conversion; - controllable output voltage (DC or AC); - controllable (bidirectional) power flow.

[0017] According to a second aspect of the disclosure, there is provided a power supply as set out in the appended claims.

[0018] According to a third aspect of the present disclosure, there are provided methods of operating an electrical converter as set out in the appended claims and as described herein. A method of operating the electrical converter of the first aspect comprises generating a switching signal for operating the switching cells of the first converter stage. The switching signal comprises opposite switching signals for the upper and lower controllable switches of preferably all the switching cells of the first converter stage.

[0019] The switching signal can be a synchronous switching signal for all the switching cells. Alternatively, a voltage signal indicative of a voltage of each phase of the polyphase AC signal is detected. A phase of the polyphase AC signal having a lowest instantaneous voltage value is determined. While the phase has the lowest instantaneous voltage value, the corresponding switching cell is clamped such that the intermediate node is continuously connected to both the first capacitor terminal of the first capacitor and the star-point. Advantageously, the one or more switching cells in respect of all other phases of the polyphase AC signal, each having a voltage value higher than the lowest voltage value, are operated synchronously.

[0020] An error signal between a measured common-mode offset voltage and a reference common-mode offset voltage is determined. The common-mode offset voltage can be determined from voltages of the first capacitors of the switching cells. A compensation signal is determined for each switching cell individually based on the error signal. The compensation signal is superimposed on the synchronous switching signal thereby controlling the common-mode offset voltage.

Brief description of the figures

[0021] Aspects of the invention will now be described in more detail with reference to the appended drawings, wherein same reference numerals illustrate same features and wherein:

[0022] Figure 1a represents a diagram of a three-phase AC to DC converter according to the present disclosure; Figure 1b represents a diagram of a three- phase AC to three-phase AC converter according to the present disclosure;

[0023] Figure 2a represents key waveforms of a continuous pulse width modulation scheme utilizing the 000 and 111 states (synchronous switching) according to an aspect of the present disclosure; Figure 2b represents key waveforms of a discontinuous pulse width modulation (DPWM) scheme according to aspects of the present disclosure;

[0024] Figure 3 represents a diagram of a clamping logic for the DPWM scheme of Fig. 2b;

[0025] Figure 4a represents an equivalent circuit diagram of a three-phase

AC to DC converter structure according to aspects of the present disclosure; Figure 4b represents an equivalent circuit diagram of a three-phase AC to three-phase AC converter structure according to aspects of the present disclosure;

[0026] Figure 5 represents a diagram of a boost-type second converter stage with DC output and bidirectional power flow according to aspects of the present disclosure;

[0027] Figure Ba represents a diagram of a boost-type second converter stage with DC output and unidirectional power flow according to aspects of the present disclosure; Figure 8b represents an alternative diagram of a boost-type second converter stage with DC output and unidirectional power flow according to aspects of the present disclosure; Figure 6c represents exemplary waveforms of the operation of the converters of Fig. 6a and 6b;

[0028] Figure 7 represents a diagram of a buck-type second converter stage with DC output and impressed DC-link current and a DC-side inductance according to aspects of the present disclosure;

[0029] Figure 8a represents a diagram of a magnetic transformer achieving non-unity voltage scaling between the first and the second converter stage; Figure 8b represents a diagram for the transformer of Fig. 8a in which the primary and the secondary windings are connected in star configuration;

[0030] Figure 9a represents a diagram of a magnetic transformer achieving non-unity voltage scaling between the first and the second converter stage in which the windings of the secondary side are realized independent of one another; Figure 9b represents a diagram for the transformer of Fig. 9a in which the primary windings are connected in star configuration;

[0031] Figure 10 represents a diagram of a phase-modular embodiment of the second converter stage according to aspects of the present disclosure;

[0032] Figure 11 represents an alternative diagram of a phase-modular embodiment of the second converter stage according to aspects of the present disclosure;

[0033] Figure 12 represents a diagram of the second converter stage for the converter of Fig. 1b, wherein the second converter stage has identical topology as the first converter stage of Fig. 1b.

Detailed Description

[0034] Referring to Fig. 1a, an electrical converter according to aspects of the present disclosure comprises a first converter stage 1, a second converter stage 2, a first plurality of (input) terminals a, b, c for connection to a polyphase AC voltage supply, e.g. athree-phase grid, and a second plurality of (output) terminals for connection to a load which can be DC or AC, e.g. output terminals P, N. The first converter stage 1 comprises a number of interface or connection nodes a’, b’, ¢’ which are equal in number to the number of input terminals a, b, c. Fig. 1a shows an embodiment of an electrical converter with three input terminals of the first converter stage (nodes a, b, ¢), which is therefore suitable for interfacing a three-phase AC mains ua, us, Ue, and correspondingly with three interface or output connection nodes a’, b’, ¢’ of the first converter stage 1.

[0035] It will be appreciated that an input filter (not shown) can be connected between the polyphase AC mains us, up, Uc and the input terminals a, b, c of the first converter stage. Such an input filter may be present to ensure electromagnetic compatibility (EMC) but does not impact the operating principle of the electrical converter of the present disclosure.

[0036] The electrical converter of Fig. 1a furthermore comprises a second converter stage 2, which features again an equal number of input terminals or nodes A’,

B’, C’ and connects to the second plurality of (output) terminals (e.g., two nodes P and

Nin case of a DC output Uac, or as shown in Fig. 1b, three second (output) terminals A,

B, C in case of a three-phase AC output. An output filter (not shown) can be connected between the second (output) terminals of the electrical converter (e.g., P and N, or A, B,

C) and the load. Such an output filter may be present to ensure electromagnetic compatibility (EMC) but does not impact the operating principle of the electrical converter of the present disclosure.

[0037] In some examples, the interface nodes a’, bb’, c’ of the first converter stage 1 are directly connected to the interface nodes A’, B’, C’ of the second converter stage 2. Alternatively, a transformer is connected between the interface nodes a’, b’, c' of the first converter stage and the interface nodes A’, B’, C’ of the second converter stage. Similarly, a common-mode inductor (not shown) can be connected between the interface nodes a’, b’, c’ of the first converter stage 1 and the interface nodes A’, B’, C’ of the second converter stage 2.

[0038] The inner structures and the operating principles of the first and the second converter stages as well as their interconnection will be disclosed in the following.

[0039] A control and modulation unit 3 can process, for example, measurements of the first (input) and second (output) terminals, measurements of internal quantities of the two converter stages, and external reference values such as the output DC or AC voltage, the power flow, etc. Ultimately, the control unit 3 generates switching commands for the switching elements of the first converter stage 1 and possibly of the second converter stage 2.

Structure of the First Converter Stage

[0040] In the first converter stage 1, the plurality of first (input) terminals a, b, c are each connected to a corresponding switching cell 11. Fig. 1a shows an exemplary embodiment with three input terminals a, b, c and three switching cells 11, which is therefore suitable for connecting to a three-phase mains us, Us, Ue.

[0041] Each switching cell 11 comprises a first capacitor Ca which carries strictly positive voltage uan, at least two series connected controllable switching elements

Sa and Sa’ (e.g. arranged in a half-bridge leg) which are connected across (parallel to) the first capacitor Ca, an input node connecting the positive capacitor terminal to the corresponding first terminal (e.g., terminal a), and an output node & being the switching node between the switching elements Sa and Sa’. The output node a is an intermediate node of the first converter stage.

[0042] The switching elements Ss and Ss’, Sp and Sp’, S and Se’ of the various switching cells 11 of the first converter stage 1 advantageously need to have only unipolar voltage blocking capability since a strictly positive voltage across the first capacitor Ca is imposed. Advantageously, the maximum blocking voltage of the switching elements is defined by the switching cell's capacitor voltage. The switching elements Sa,

Sv, Sc connected between the positive capacitor terminal (first terminal a, b, c respectively) and the output node a, b,c respectively are referred to as high-side switching elements and the switching elements Ss’, Sp’, Sc’ connected between the output node a, b,¢ and the star-point n are referred to as low-side switching elements.

Furthermore, a switching cell 11 can be compactly realized such that the commutation inductance is minimal, which enables fast switching, low switching losses and limited overvoltages during switching transients.

[0043] The switching cells 11 can be realized as multilevel bridge-legs (e.g., neutral-point clamped, flying-capacitor) or even as modular-multilevel converter (MMC) structures with full-bridge or half-bridge cells.

[0044] The negative capacitor terminals of the first capacitors of all switching cells 11 are connected to a common star-point node n.

[0045] The common-mode (CM) voltage (e.g., ugn) is defined as the voltage between the AC mains star point g and the switching cells’ common star-point node n.

This CM voltage is controlled such that the voltages across the switching cells’ capacitors are strictly positive, even though the mains voltages (ua, U, Uc) are AC voltages with respect to the mains star-point g.

[0046] The output nodes 2, b, ¢ of the switching cells 11 are each connected to a first terminal of a series capacitor Csa, Cs, Cs respectively. The series capacitors’ main purpose is to provide galvanic separation in a compact way and advantageously without the need for magnetic components. This implies that the power transfer between the first and the second converter stages must occur at high frequencies (i.e. substantially higher than the mains frequency) where the capacitor’s impedance is low, i.e., a high switching frequency must be selected. It will be convenient to note that the series capacitors can have arbitrary values, i.e, it is not necessary to tune the capacitor values to achieve some sort of compensation, e.g., of a downstream inductance.

[0047] The series capacitors’ second terminals form the interface nodes a’, b’, ¢’ of the first converter stage 1. The number of interface nodes equals the number of first (input) terminals a, b, ¢ and the number of switching cells 11. The interface nodes a’, b’, ¢ of the first converter stage are connected or at least coupled to the interface nodes A’, B’, C’ of the second converter stage 2.

Mode of Operation of the First Converter Stage

[0048] The purpose of the first converter stage 1 is to generate an amplitude-modulated high-frequency polyphase voltage system at its interface nodes a’,

Db’ ¢. In the advantageous case that the switching cells 11 employ switches with only unipolar blocking voltage capability, the first capacitor voltages (e.g., Lan) must be strictly positive. Therefore, these first capacitor voltages must contain a common-mode (CM) offset voltage with respect to the common star-point node n. For example, a DC CM offset voltage that equals the amplitude of the input AC voltage (e.g., at the first terminals a, b, c) ensures strictly positive voltages across the first capacitors Ca.

[0049] In general, the (potentially time-varying) CM offset voltage determines the voltage system that the switching cells 11 can generate at their output nodes a, b, ¢. Considering a three-phase system, this means that the orientations and the lengths of the available space vectors depend on the CM offset voltage, except for those corresponding to the switching states [111] (i.e., all high-side switches such as S, are turned ON, connecting each switching cells output node & to the corresponding first terminal a, while the low-side switches are turned OFF) and [000] (i.e., all low-side switches such as S.'’ are turned ON, connecting all switching cells’ output nodes to the common star-point node n, while the high-side switches are turned OFF). It is therefore beneficial to apply a modulation scheme for the first converter stage that employs only these two switching states, i.e., which switches all switching cells synchronously and with opposite switching signals for the high-side and low-side switches. Note that this consideration can be generalized to polyphase systems with a different number of input phases and switching cells. Advantageously, only two control signals (one for all high- side switches and one for all low-side switches) are needed regardless of the number of switching cells.

[0050] Advantageously, equal durations (i.e., a duty cycle of D= 0.5) of the two switching states [111] and [000] are selected (exemplarily considering the embodiment with three phases and three switching cells) within a pulse period Ts = 1/f;, whereby fs denotes a switching frequency that is typically significantly higher than the mains frequency fac of e.g. 50 Hz or 60 Hz, e.g. at least 10 times, advantageously at least 100 times the mains frequency fa, and possibly in the range of several tens of kilohertz, the voltage at the interface nodes of the first converter stage is a high-frequency (HF) voltage that is amplitude-modulated with carrier frequency f. The amplitude is determined by, and in phase with, the respective switching cell’s input voltage, i.e., the corresponding mains phase voltage us, U, Ue. The envelope of the differential mode (DM) high-frequency (HF) voltage signal ua,pm thus obtained at the interface node a’ can be written as:

Ugipy = Td Ug SIN(27 fat) (Eq. 1), wherein the + and — levels toggle with carrier frequency fs and wherein d is a factor dependent on the duty cycle D of the switching cells, e.g., d = 0.5 for duty cycle D = 0.5 due to the voltage across the series capacitor Csa. The DM HF voltage signals at the other interface nodes b’ and ¢’ have equal magnitude but are 120° phase shifted (in the case of a three-phase mains).

[0051] Fig. 2a shows exemplary waveforms for the embodiment of Fig. 1a with three switching cells connected to a three-phase mains. It is important to highlight that the Fig. 2a shows the focal average value of the HF current waveforms; the effective current shape differs for the various realization options and operating modes of the second converter stage, which are discussed below.

[0052] The modulation scheme of the first converter stage described above is just one advantageous example, however. Other switching patterns that employ also other switching states (e.g., [110], [910], etc.) may be used.

[0053] Nonidealities (e.g., interlock delay times required when changing between the switching states to prevent short-circuiting the first capacitors) can lead to a undesired shift of the CM offset. Even though this does not affect the HF voltage system at the first converter stages’ interface nodes, it can lead to increased voltage stress of the switching elements, i.e., to higher switching losses and potentially destructive overvoltages. It is hence advantageous to define the CM offset by suitable control and modulation.

[0054] One option is to employ a closed-loop control of the CM voltage.

The CM voltage is calculated from measurements of the switching cells’ input voltages (the first capacitor voltages such as Ue), and the control unit 3 {e.g., implementing a PI controller) is configured to calculate a compensation signal that modifies the duty cycle

D for each switching cell 11 individually as needed for the CM voltage to track a desired reference value.

[0055] In an alternative advantageous embodiment, discontinuous pulse- width modulation (DPWM) is employed. At any given time, the switching cell, whose input voltage (e.g., van) is the lowest of all input voltages, is clamped such that both its switching elements (i.e., the low-side switch and the high-side switch) are transitioned to the ON or conduction state regardless of the modulation signal. A possible clamping logic is shown in Fig. 3. Turning on both switches ensures clamping regardless of the power flow direction. The corresponding first capacitor voltage is zero during the clamping time interval whereas the HF voltage system generated at the first converter sages’ interface nodes is not affected. As a result, the common star-point node n is tied to the converter's first (input) terminal with the lowest instantaneous voltage, which ensures that the CM offset voltage remains strictly defined and limited. Advantageously, this DPWM method reduces the switching losses, as at any given time one switching cell is clamped and hence does not generate switching losses, and because the resulting CM offset voltage is such that the maximum blocking voltage stress of the switching elements is minimized.

The other switching cells, i.e. whose input voltage is not lowest, can be operated synchronously with opposite gate signals between high-side and low-side switches, i.e. according to the [111] and [000] states for all but the switching cell having lowest input voltage.

[0056] Fig. 2b shows exemplary waveforms for the embodiment of Fig. 1a with three switching cells connected to a three-phase mains. One can discern from

Fig. 2b that the HF differential mode (DM) voltage signals obtained at the first converter stage’s interface nodes a’, Db’, c’ are identical to the ones obtained with the synchronous

PWM according to Fig. 2a, i.e. they can be defined by the formula of Eq. 1. Particularly, for each phase, the envelope of the DM voltage signal has mirror symmetry with respect to the 0 V axis.

Second Converter Stage: Mode of Operation

[0057] The second converter stage 2 is advantageously operated such that at each of its interface nodes A’, B’, C’ a current appears, whose local average value is proportional to the local average value of the corresponding HF voltage appearing at the corresponding interface nodes a’, b’, ¢’ of the first converter stage. This ensures ohmic behavior at the first converter stage’s first (input) terminals a, b, c, i.e., cosy = +1, so that the first converter stage does not need to contain any significant energy storage elements.

[0058] Fig. 4a shows an equivalent representation of a second converter stage 2 that can impress such currents at its interface terminals A’, B’, C’ and transfer power to a DC voltage output (terminals P and N), i.e., the overall converter realizes AC-

DC conversion. The first converter stage 1 is represented by three HF voltages that appear at its interface nodes a’, b', ¢'.

[0059] Fig. 4b similarly shows an equivalent representation for a second converter stage that transfers power to a three-phase AC output (terminals A, B, C), i.e, the overall converter realizes AC-AC conversion.

[0060] In the following, illustrative embodiments of the second converter stage are discussed. In principle, any converter that can achieve the behavior described above at its interface node A’, B’, C’ can be employed as second converter stage of electrical converters of the present disclosure.

Second Converter Stage: Implementation Variants for AC-DC Operation

[0061] In the following, the explanations consider power flow from the AC to the DC side, i.e, rectifier operation, for the sake of clarity. Most embodiments,

however, also allow a power flow in the other direction, such that the converter operates as an inverter.

[0062] Fig. 5 shows a first implementation of the second converter stage that consists of a boost-type three-phase rectifier. Being a boost-type rectifier, the DC output voltage is higher than the peak phase-to-phase voltage appearing at the interface nodes A’, B’, C'. It is therefore in principle possible to shape the currents in the input inductors Lsa, Lsg, Lsc such that the desired proportionality of their local average values to the local average values of the respective voltages at the interface nodes of the first converter stage can be achieved (for example, space vector modulation (SVM) can be employed for operating the second converter stage). An operating principle similar to that of (polyphase) dual active bridge (DAB) converters can be utilized.

[0063] Hence, the electrical converter achieves overall AC-DC conversion with unity power factor and sinusoidal currents at the input terminals a, b, c and a regulated DC output voltage. It will be convenient to note that fully bidirectional power flow is possible, i.e., the converter can also operate as a DC-AC inverter. It will also be convenient to note that systems with more than three phases are possible.

[0064] Fig. 6a and fig. 8b show two implementation variants of a boost-type second converter stage that show reduced complexity (fewer controlled switching elements), and can achieve only unidirectional power flow (i.e., operation as AC-DC rectifier) as compared to the second converter topology of Fig. 5.

[0065] The second converter stages as shown in Figs. 5 and 6a-6b can be operated as follows. In a first interval of the switching period, all controlled switching elements are turned ON, effectively connecting all switch nodes 4, B, € together. During this first interval, in each input inductor Ls, Le, Lsc a current that is proportional to the respective input voltage at the interface nodes A’, B’, C’ builds up. In a second interval of the switching period, all controlled switching elements are turned OFF. Consequently, the input inductors demagnetize via the diode rectifier (corresponding diodes of Sa, Sg,

Sc in Fig. 5, diodes Da in Fig. 6a and diodes Da and Da in Fig. 6b) into the output capacitor (Ca, Cs, Cc in Figs. 5, 6a and Cas in Fig. 8b). Finally, only the two input phases with the highest and the lowest instantaneous voltage remain connected to the positive and the negative output terminals P and N, respectively, via the corresponding diodes, whereas no current flow is possible in the third phase. Fig. 6¢ shows exemplary waveforms for this mode of operation during one HF switching period for the converters of Figs. 6a-6b. The price of the lower complexity is a deviation from the second converter stage’s desired behavior and ultimately low-frequency distortions in the converter’s input currents at the first terminals a, b, c, which, however, are still in phase with the input voltages at those terminals. In the lower graph of Fig. 6c, <isa>, <ise™> and =<isc> in dashed lines indicate the local average values of the inductor currents, i.e., averaged over one half of the switching period Ts.

[0066] The above modulation scheme, however, is just the most straightforward one, which achieves only approximate proportionality of the local average values of the input inductor currents and the local average value of the corresponding HF output voltage of the first converter stage appearing at the corresponding interface nodes a’, b’, ¢’. There are other modulation methods possible, which are more complicated yet can achieve the desired exact proportionality.

[0067] Fig. 7 finally shows an implementation of the second converter stage as a buck-type rectifier with an impressed DC-link current and a DC-side inductance Las. Therefore, in contrast to the boost-type rectifiers discussed above, it does not require input inductances connected at its interface nodes A’, B’, C'. Instead, commutation capacitors Ca, Ce, Cc are required, e.g. star-point connected, which, however, can be small enough to not impact the mode of operation described here.

[0068] The switching elements Sa, SA must provide bipolar voltage blocking capability and allow controlled current conduction in both directions. This can be achieved, for example, by an anti-series connection of two MOSFETs as shown in

Fig. 7. Alternatively, monalithic bidirectional GaN transistors can be employed.

[0069] The buck-type rectifier can directly impress a desired current at its interface nodes A’, B’, C' and hence again the overall converter achieves unity power factor and sinusoidal currents at its input terminals a, b, c. To maintain controllability of the DC link current, the output voltage must be strictly smaller than 3/2 times the peak phase-to-phase voltage appearing at the interface nodes A’, B’, C' — and, if no transformer is used (see below), therefore also smaller than V3/2 times the peak phase- to-phase voltage at the converters input terminals a, b, c.

[0070] The buck-type converter of Fig. 7 allows fully bidirectional power flow, i.e., the converter could also operate as a PV DC-AC inverter. Note that systems with more than three phases are possible.

Transformer

[0071] The series capacitors (Csa, Cs, Csc) of the first converter stage 1 provide galvanic separation between the converter’s input and output in a very compact way. However, for example to achieve a non-unity voltage scaling, a magnetic transformer 4a can be connected between the interface nodes of the first converter stage a,b,c and the second converter stages’ interface nodes A’, B’, C’ as shown in Fig. 8a.

[0072] Advantageously, the transformer experiences only a HF magnetization (with switching frequency fs), which facilitates compact realizations.

[0073] The stray inductance present in real transformers can be utilized to partly or entirely replace the inductive component at the input of those embodiments of the second converter stage that require such input inductors Lsa, Lsg, Lsc.

[0074] The transformer 4a can have various configurations, and is advantageously a core transformer. For example, the primary and the secondary windings can both be in star configuration as shown in Fig. 8b. Alternatively, one of the two or both can be in delta configuration.

[0075] Figs. 9a-9b show a transformer 4b having secondary-side windings that are realized independent of each other, and each of these windings can have both their terminals Ay, AZ, Bi, By, C+, C: accessible. This facilitates phase-modular embodiments of the second converter stage.

[0076] Similarly, a Scott transformer configuration with three primary windings but only two independent secondary windings can be employed. The Scott transformer configuration converts a three-phase voltage system (with 120° phase displacement between the phases) into a two-phase voltage system with 90° phase displacement between the two phases. Advantageously, this facilitates a modular realization of the second converter stage with only two instead of three modules.

Phase-Modular Embodiments of the Second Converter Stage

[0077] Fig. 10 shows a first phase-modular embodiment of the second converter stage. The interface nodes of such a phase-modular second converter stage can be connected to the secondary side of the transformer 4b. Similar to the integrated version shown above in Fig. 5, each phase module can shape the current in its input inductor (like a DAB) such that the desired proportionality of local average values of voltage and current at the second stages’ interface nodes A’, B’, C’ and hence unity power factor and sinusoidal currents at the converters input terminals a, b, ¢ are achieved. Advantageously, the phase-modular realization would enable a plurality of independent DC outputs, e.g., considering Fig. 10, instead of connecting the three DC outputs of the three-phase modules in parallel, each of the three-phase module’s DC outputs could be used as independent external ports.

[0078] Fig. 11 shows a further embodiment of a phase-modular second converter stage. Each phase module features a full-bridge diode rectifier and a non- isolated boost converter. The diode rectifier acts as a folder stage and thus restores the (low-frequency) envelope of the HF voltage appearing at its input terminals.

Advantageously, the boost converter can be controlled such that the current in the inductor La is proportional to the output voltage of the diode rectifier, e.g., as known from single-phase PFC rectifiers. The diode rectifier can ensure that the HF current in the corresponding transformer winding is again proportional to the corresponding voltage, as needed for unity power factor and sinusoidal currents at the converter input terminals abc

[0079] It may be necessary to provide a small commutation capacitor Cpa at the output of the diode rectifier.

[0080] Bidirectional power flow can be achieved by replacing the diode rectifier with transistors that are controlled to implement active synchronous rectification and allow bidirectional current flow.

[0081] If the duty cycle D of the first converter stage is reduced or increased (ie. not selected as D= 0.5), the (local average over one switching period) of the rectified diode bridge voltage Ups reduces with approximately (D-D?), enabling single- stage buck-boost capability.

[0082] Alternatively, by selecting the values of the first converter stage’s series capacitors (Csa, Csb, Csc) such that they compensate the impedance of the transformer’s stray inductance (and any other inductance between the two stages) at or close to the switching frequency, resonant operation with sinusoidal current pulses and advantageously very low switched currents (in the first converter stage) and hence low switching losses can be achieved (see, e.g., J. E. Huber, D. Rothmund, and J. W. Kolar, “Comparative evaluation of isolated front end and isolated back end multi-cell SSTs,” in

Proc. 8th Int. Power Electron. and Motion Contr. Conf. (IPEMC/ECCE Asia), Hefei,

China, May 2016, pp. 3536-3545 doi: 10.1109/IPEMC.2016.7512863 for details on this mode of operation). Note that in this case, however, the first converter stage must operate with D = 0.5 and the buck-boost capability is lost.

[0083] As mentioned above, a modular realization with only two modules can be achieved if the transformer is realized as a Scott transformer.

Second Converter Stage: Implementation Variants for AC-AC Operation

[0084] As indicated in Fig. 4b, the second converter stage 2 can also be realized with an AC output (terminals A, B, C) instead of a DC output. For example, the second converter stage may be realized as a direct matrix converter or as an indirect matrix converter.

[0085] Fig. 12 shows an alternative, advantageous embodiment where the second converter stage is implemented in the same way as the first converter stage. The operating principle of the second converter stage is identical to that of the first converter stage (synchronous switching of all phases, duty cycle D = 0.5, closed-loop control of the CM offset or, preferably, DPWM).

[0086] In a first operating mode, the switching signals of the second converter stage are phase-shifted with respect to the switching signals of the first converter stage. As in a DAB converter, the power flow in a series inductance between the two converter stages can be controlled via this phase shift.

[0087] In a second operating mode, the series capacitors (Csa, Cen, Csc, Csa,

Css, Csc) are selected such that they compensate the respective series inductances at the (or close to) the switching frequency, i.e., resonant operation is achieved. The second converter stage can then be realized with diodes instead of with active switches, or, in case active switched are used, the phase shift between the switching signals of the first and of the second converter stage is zero. Advantageously, the HF currents flowing in the series inductances between the two converter stages are sinusoidal pulses, and hence only low currents must be switched. Furthermore, the power flow adjusts automatically to the load, i.e., the AC voltages at the converter's output terminals A, B,

C are ideally (not considering conversion losses, and assuming no transformer or a transformer with unity turns ratio) equal to the AC input voltages at the converter’s input terminals a, b, ¢, and (almost) load-independent, without the need for closed-loop control.

This operating mode is known from DC-DC converters as “DCX”, see, e.g., J. E. Huber,

J. Miniböck, and J. W. Kolar, “Generic derivation of dynamic model for half-cycle DCM series resonant converters,” IEEE Trans. Power Electron., vol. 33, no. 1, pp. 4-7, Jan. 2018, doi: 10.1109/TPEL.2017.2703300 for details).

[0088] Electrical converters of the present disclosure can be utilized as or integrated in power supplies. Possible applications are Electric Vehicle chargers,

Photovoltaic (PV) inverters, telecommunications and data center power supplies, drives, etc.

Claims

CONCLUSIONS

1. Electrical inverter comprising: a plurality of first inverter terminals (a, b, c) and a plurality of second inverter terminals (P, N and/or A, B, C), the electrical inverter configured to transmit between a multi-phase alternating current signal at the plurality of first converter terminals and a second signal at the plurality of second converter terminals, a first converter stage (1) connected to the plurality of first converter terminals {a, b, Cc), where the first converter stage for each of the plurality at first inverter terminals comprises: a switching cell (11) comprising a first capacitor (Ca), which has a first capacitor terminal connected to the corresponding first inverter terminal (a, b, c) and a second capacitor terminal connected to a star point common to the first capacitors ( n) has, an upper node connected to the first capacitor terminal, a lower node connected to the star point (n) and an intermediate node (a) switchably connected to the upper node and to the lower node, a second capacitor (Ca), which a first capacitor terminal connected to the intermediate node (&) and a second capacitor terminal constituting a terminal node (a') of the first inverter stage, the electrical inverter comprising a control unit (3) configured to control the switching cells (11) to be operated to convert between the multi-phase alternating voltage signal at the plurality of first inverter connections (a, b, c) with a first frequency, and a multi-phase, amplitude modulated voltage signal at the connection nodes (a', b', ¢') with a carrier frequency substantially higher than the first frequency, and such that a differential mode of each phase of the multiphase amplitude modulated voltage signal is modulated based on an amplitude of a corresponding phase of the multiphase ac voltage signal.

An electrical converter according to claim 1, wherein the differential mode of each phase of the multi-phase amplitude modulated voltage signal is in phase with the corresponding phase of the multi-phase AC voltage signal.

Electrical inverter according to claim 1 or 2, wherein the control unit (3) is configured to operate the switching cells (11) synchronously.

An electrical inverter according to claim 1 or 2, wherein the control unit (3) is configured to operate the switching cell (11) corresponding to a phase of the multi-phase AC signal having a lowest instantaneous voltage value of the multi-phase AC signal, in a clamp-in mode where the intermediate node (ä) is continuously connected to both the first capacitor terminal of the first capacitor (Ca) and to the star point (n).

An electrical inverter according to claim 4, wherein the control unit (3) is configured to operate the remaining switching cells synchronously.

Electrical inverter according to any of the preceding claims, wherein the carrier frequency is at least 10 times higher than the first frequency, preferably the first frequency is 100 Hz or lower and the carrier frequency is 1 kHz or higher.

An electrical inverter according to any one of the preceding claims, wherein the switching cell (11) has an upper controllable switching device (Ss), which connects the upper node to the intermediate node (&), and a lower controllable switching device (Sa), which the bottom node connects to the intermediate node, comprises.

An electrical converter according to claim 7, wherein one or both of the upper controllable switching device and the lower controllable switching device are unipolar voltage blocking, switching devices.

An electrical inverter according to any one of the preceding claims, further comprising a second inverter stage (2) connected to the plurality of second inverter terminals, the second inverter stage comprising a plurality of terminal nodes (A', B', C') coupled to the terminal nodes (a, b', ¢) of the first inverter stage (1), wherein the second inverter stage (2) is configured to transmit a signal at the terminal nodes of the second inverter stage into the second signal at the plurality of second inverter terminals (P, N, A, B, C) to shape.

Electrical inverter according to claim 9, further comprising a magnetic transformer (4a, 4b) comprising a primary side with primary side connections connected to the connection nodes (a', b', c') of the first inverter stage (1) and a secondary side with secondary side connections connected to the connection nodes (A', B', C') of the second inverter stage (2).

An electrical converter according to claim 10, wherein the control unit (3) is configured to operate the switching cells (11) such that the carrier frequency is outside a resonant operating range defined by the second capacitors and windings of a primary side of the magnetic transformer , preferably the carrier frequency is equal to or below % of a resonant frequency, defined by the second capacitors and windings of a primary side of the magnetic transformer, and/or the carrier frequency is equal to or higher than 4 times the resonant frequency.

An electrical converter according to claim 10, wherein the control unit (3) is configured to operate the switching cells (11) such that a ratio of the carrier frequency and a resonant frequency defined by the second capacitors and windings of a primary side of the magnetic transformer, is between 0.75 and 1.25.

Electrical inverter according to any one of claims 9 to 12, wherein the connection nodes (a', b', ¢') of the first inverter stage and of the second inverter stage (A', B', C') are equal in number .

An electrical inverter according to any one of claims 9 to 13, wherein the second inverter stage (2) is configured to operate such that currents at the connection nodes (A', B', C') of the second inverter stage have local average values proportional to local average values of corresponding voltages of the multi-phase, amplitude modulated voltage signal occurring at corresponding connection nodes (a', b', c') of the first inverter stage (1).

An electrical inverter according to any one of claims 9 to 14, wherein the second inverter stage (2) comprises an up-switching type circuit, a down-switching type circuit or a combination of an up-switching and a down-switching circuit.

An electrical converter according to claim 15, wherein the second converter stage includes a corresponding input inductor (Ls, Lse, Lsc) connected to each of the terminal nodes of the second converter stage.

The electrical inverter of claim 18, wherein the second inverter stage includes a corresponding switching cell connected to each of the input inductors, the switching cell configured to switch a current from the corresponding input inductor.

An electrical converter according to any one of claims 9 to 17, wherein the second signal is a direct current signal or a three-phase alternating current signal.

An electrical inverter according to any one of the preceding claims, configured to convert power bidirectionally between the plurality of first inverter terminals (a, b, c) and the plurality of second inverter terminals {P, N, A, B, C).

20. Power supply, comprising the electrical converter according to any of the preceding claims.

A method of operating an electrical inverter according to any one of claims 1, 2 and 4 to 19, comprising: detecting a voltage indicative of each phase of the multi-phase alternating current signal (Us, Uan), determining a phase of the multi-phase AC signal which has a lowest instantaneous voltage value, while the phase has the lowest instantaneous voltage value, clamping the corresponding switching cell, such that the intermediate node (3) is continuously connected to both the first capacitor terminal of the first capacitor (Ca ) as with the star point (n).

A method according to claim 21, comprising operating the one or more switching cells synchronously with respect to all other phases of the multi-phase alternating current signal, each of which has a voltage value higher than the lowest voltage value.