NL2026064A - Multiple LDPC Decoding Method and Device Based on Code Element Reliability Dominance Nodes Subset Partition Criterion - Google Patents
Multiple LDPC Decoding Method and Device Based on Code Element Reliability Dominance Nodes Subset Partition Criterion Download PDFInfo
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- H03M13/112—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the min-sum rule with correction functions for the min-sum rule, e.g. using an offset or a scaling factor
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Abstract
A multiple LDPC decoding method based on the code element reliability dominance node subset partition criterion, includes: Sl: computing and truncation initialization information; S2: judging 5 current and maximum number of iterations, if the current number equals the maximum number, exiting the iterative decoding, otherwise entering step S3: updating the information of the check nodes in processing subset M…, computing the external information and truncating the information, S4: replacing the external information of the check nodes, S5: computing the posterior probability . . L S . . Laß—“LI!” S . Lag—”LIN S . information ”( ) and information vector “‘" ( ), and replacmg “‘" ( ); S6: conduct1ng fi] = arg max{LV (s)} 10 decision decoding on each variable node according to SEE] ' ; S7: checking result of . . . . AT _ . . . . . . . . the dec1s1on decod1ng, 1f HV _ 0, decod1ng 1s fin1shed, otherw1se, enter1ng step S8: part1tlon1ng the check nodes, of which the information needs to be updated in next iteration, into the subset M(1), simultaneously, making the number of iterations iter ziler +1, and jumping to S2 for the next iterative decoding. 28
Description
Multiple LDPC Decoding Method and Device Based on Code Element Reliability Dominance Nodes Subset Partition Criterion Technical Field The invention belongs to the field of channel coding, and in particular relates to a multiple LDPC decoding method based on the code element reliability dominance node subset partition criterion.
Background Techniques Because of its better decoding performance than binary LDPC codes and its inherent advantages in high-order modulation channels, multiple LDPC codes have attracted much attention from researchers in the field of channel coding.
The multiple LDPC codes were originally proposed by Davey and MacKay.
They proposed a kind of LDPC codes defined on a finite domain GF (q), and a decoding method accordingly applicable to this kind of multiple LDPC codes, commonly known as Q-ary sum-product algorithm (QSPA). Multiple LDPC codes have better performance in the field of medium and short code length because they can avoid error layering, but the direct computation of QSPA algorithm is very complicated, which makes it difficult for LDPC codes to be applied in practice.
In order to reduce the computational complexity of multiple LDPC codes, Declercq et al. proposed an extended min-sum (EMS) algorithm in 2007, which reduces the computation of check nodes by truncating the information vectors from the input to the check nodes.
In 2012, Ma et al. redescribed the EMS algorithm (called M-EMS algorithm) with the help of Trellis graph, and proposed two improved algorithms of M-EMS algorithm, known as T-EMS algorithm and D-EMS algorithm.
In 2013, Zhao et al. proposed a uEMS algorithm.
These algorithms reduce the computational complexity all by using truncation criteria to reduce the length of the vectors involved in check nodes updating calculations.
In addition, partitioning non-processing subsets of nodes is also an effective way to reduce the computational complexity of the algorithm, the works related including an improved information transfer decoding algorithm proposed by Han et al. in 2013 and a reliability iterative proportional logic decoding algorithm based on adaptive decision mechanism proposed by Sun et al. in 2015. In 2017, Sun Youming et al. proposed a multiple LDPC algorithm 1 which combined the two truncation mechanisms of nodes subset and k-order information truncation. The algorithm proposed a new node subset partition criterion, which uses the reliability of the decision symbols of the variable nodes adjacent to the check nodes to partition the check nodes subsets. It remains to be studied how to define the subset threshold and how to partition the subsets.
Contents of Invention In view of the disadvantages of the existing techniques mentioned above, the present invention aims to provide a multiple LDPC decoding method and a device thereof based on the code element reliability dominance node subset partition criterion.
In order to achieve the above purposes and other related purposes, the present invention provides a multiple LDPC decoding method based on the code element reliability dominance node subset partition criterion, which is used for channel coding, including: S1: Computing initialization information IDs) according to the channel received value y; and the given scale factor &, quantized bit number ?, and quantized interval A, and using the information truncation criterion to truncate the initialization information L770 (s) setting the current number of the iteration iter = 0; when conducting the first iterative decoding, making all the check nodes being in the check nodes processing subset A; S2: Judging the current number of the iteration iter and the maximum number of iterations ifer, if the current number of the iteration iter is equal to the maximum number of iterations iter then exiting the iterative decoding and outputting decoding results, if the current number of the iteration ifer is less than the maximum number of iterations fer then entering step S3, S3: Updating the check nodes in the processing subset of the check nodes A7 according to the result of the check nodes partition, computing the external information Ly" (a) and truncating the information; S4: Replacing the external information Li" (a) of the check nodes according to the replacement rule of the intermediate nodes to obtain the information transmitted by the intermediate nodes to the neighboring variable nodes Ly" MOF S5: Computing respectively the posterior probability information of the variable node L. (s) and the information vector Ly > (sy transmitted by the variable nodes 1° to the 2 intermediate nodes #7, according to the updating rule of the variable nodes, and replacing the information Ly EOF $6: Conducting the decision decoding on each variable node according to 5, =arg maik (s)} for0< j<n-l; S7: Checking the result of the decision decoding, if #9” =0, then the decoding is finished, outputting the result of the decoding, otherwise entering step S8; S8: Partitioning the check nodes, of which the information needs to be updated in the next iteration, into the subset AY” according to the criterion of check nodes subset partition, at the same time, setting the number of iterations iter =iter +1, and jumping to step S2 for the next iterative decoding.
Optionally, for a given channel received value >, the value of the initialization information is computed in the following manner; First computing the likelihood information RK. (s) in the logarithmic domain: 1S 7) (i) R,(©)=23 3 1-25") 5c F, ° £ i=0 In the formula, s'’ refers to the No./ bit of the vector representation of this finite field symbol, F‚ represents the finite field of q order. The likelihood information of the logarithmic domain is quantified into integer information according to the quantized interval A > 0, the quantized bit number 5>1 and the following rules; i 2" -D,R, /A<—(2"-1) Ly (s)=1[R; (s)/ Al, IR (5)/A <2 1 le -D,R(s)/A22’-1 In the formula, [x] stands for a rounding operation, representing the integer nearest tox is obtained.
Optionally, the updating rule for the variable nodes is: The variable nodes J’, receive information Ly from the connected intermediate nodes H, and update the information according to the following rule: (SF) (HU, >Fj) Ly. (s)= Ly. Ts) + DL Ts), s € Fr, ied ; 3
The external information Ly 27 (sy that the variable nodes V, pass to the intermediate nodes H,, is computed in the following way: EH) u CH, =) on Ly (8)=1 (s) Lg sel.
Optionally, the information truncation criteria are: |) Lb, seF,, Fo) [© et EF, —o, otherwise L,.(s) represents the logarithmic domain information vector,. F = Ig = F | Laisvizoneofihe MN 3 A Ess 3 4 . 4 A x g | Lyv{syisomeofthe Mmaxvaluess £ L, _ min L, (5). Optionally, updating the check nodes, including: Two vectors a, =(a,(0),o,(1),....,a,(g—1)) and B, =(L.(0),L5,(1,..,0(g—1)) are defined as the forward iteration vector and the backward iteration vector, respectively.
The computational process is as follows: Forward Iterative Process: Givena, =(0,—,...,—0), d_ indicating the degree of the No.i check node, for 0<r<d —1 and Vs e (GF (q), making the iterative computation: - u ( THC) a (s) =max{c, (s—z)+ Ly (2)},s€ kl, Backward Iterative Process: Given B, =(0,—x,...,—%) d_ indicating the degree of the No.; check node, for d 2t>1 and Vs € GF (gq). making the iterative computation: u) — § 0 = TOE) en nl Pis) = maxi f(s —z)+ Ly (2)}.8€F, zef, i External Information Extraction: For 0<t<d —1 and VseGl(g), using the following formula to compute the external information transmitted by the check nodes to the intermediate nodes: C,H) La) = max{a, (9) + fu (s+ al} SF, Information Post-processing: For0 <: <d. —1, computing: 4
Ee de La) = ’ di . (CoH) ming £4}. Other In the formula, & is a scale factor.
Optionally, the replacement rules for the intermediate nodes are: The information of the variable nodes 1° transmitted to the check nodes C‚ through the intermediate nodes H, is replaced according to the following formula: (FH; -C) FH) | Ls, | (s) = Ly (4, s), SE F, The information that is transmitted to the variable nodes 17, through the intermediate nodes H, from the check nodes C; is replaced according to the following formula: (HV) CH) A | Ls, | (s) T Ly (h, 5), SE F, ° Optionally, the check nodes are partitioned according to the criterion of the subset partition of check nodes based on reliability dominance.
Optionally, for a variable node, reliability dominance adv, means the degree of dominance in possibility of the code element symbol with the highest reliability degree compared to the code element symbol with the second highest reliability degree.
adv, = max{ Ly. ($)}—max"{ IL, (9), sel, In the formula, max’ represents the submaximum in vector Z,. (s).
Optionally, the check nodes of the checksum ¢, =) 4 -%"=0 are partitioned according to the jel, criterion of subset partition of the check nodes based on reliability dominance. The criterion of subset partition 1s as follows: MO -{c en ule [zw > 2" of The check nodes are partitioned into the processing nodes subset and non-processing nodes subset. The check nodes in the processing nodes subset is characterized in that its checksum is not zero, or its checksum is zero, but the code element reliability dominance of two or more variable nodes in the adjacent is less than the threshold value 7.
In order to achieve the above purposes and other related purposes, the present invention provides a multiple LDPC decoding device based on the code element reliability dominance node subset partition criterion used for channel coding, which consists of: 5
An initialization module, which is used to calculate the initialization information Ls) according to the channel received value y and the given scale factor’ | quantized bit number? | and quantized interval A, and by the information truncation criterion to truncate the initialization information Lo (s); setting the current number of the iteration iter = 0; when conducting the first iterative decoding, all the check nodes are in the check nodes processing subset Af;
A judgment module, which is used to judge the current number of the iteration iter and the maximum number of iterations ifer, if the current number of the iteration iter is equal to the maximum number of iterations iter exiting the iterative decoding and outputting the decoding result, and if the current number of the iteration iter is less than the maximum number of iterationiter, _, entering the iterative decoding process;
A check nodes update module, which is used to update the check nodes in the processing subset of the check nodes M) according to the result of partition of the check nodes, to calculate the external information Ly >) (a) and to truncate the information;
An intermediate nodes replacement module, which is used to replace the external information
I; (a) of the check nodes according to the replacement rule of the intermediate nodes to get the information Ly ”)(s) transmitted by the intermediate nodes to the adjacent variable nodes, and to replace LY Hy) (5) according to the replacement rule to get the information KO) transmitted by the intermediate nodes #7, to the adjacent check nodes;
A variable nodes update module, which is used to calculate separately the posterior probability information of the variable nodes Ly. (s) and the external information Ly ’(s) that transmitted by the variable nodes I’, to the intermediate nodes 77, according to the updating rule of the variable nodes;
A decoding decision module, which is used for decision decoding of each variable node according to Vv, =arg max IA (s)} for0< j <m—l, and at the same time, for checking the result of the decision decoding, if HV = 0 the decoding is finished, and the decoding result is outputted;
A check nodes partition module, which is used to partition the check nodes, of which the information needs to be updated in the next iteration, into the subset M according to the criterion of the check nodes subset partition, and at the same time, to set the number of iterations as
6 iter = iter +1 to proceed to the next iterative decoding.
As mentioned above, the multiple LDPC decoding method based on the code element reliability dominance node subset partition criterion provided in the present invention has the following beneficial effects: The multiple LDPC decoding method based on the code element reliability dominance node subset partition criterion provided in the present invention proposes a novel node subset partition criterion, which uses the code element reliability dominance degree to judge the reliability of the decision symbols of the variable nodes when partitioning processing/non-processing subsets of the check nodes, of which the checksum is not zero. The decoding symbol is considered to be reliable only when the reliability of the symbol is greater than that of other symbols by a threshold value 7, and then is partitioned into processing or non-processing subsets according to the number of the reliable variable nodes in the check nodes. Furthermore, a calculation method for determining the threshold value is also given in the present invention. Compared with the EMS algorithm based on other subset partitioning criteria, this method can achieve better error correction performance with lower computational complexity.
Instruction with Figures In order to further elaborate the contents described in the present invention, the specific embodiment of the present invention is further illustrated in detail with the figures. It should be understood that these figures serve only as typical examples and should not be regarded as limiting the scope of the invention.
Figure 1 is a flow chart of the multiple LDPC decoding method based on the code element reliability dominance node subset partition criterion provided in the present invention; Figure 2 is a Normal diagram of a multiple LDPC code; Figure 3 shows the BER data of each algorithm in Experiment 1.
Figure 4 shows the complexity ratio of each algorithm in Experiment 1.
Specific Embodiment The following specific examples are used to illustrate the embodiment of the present invention.
The technical personnel in this field can easily understand the other advantages and effects of the present invention by the contents disclosed in this Specification. The invention can also be implemented or applied in other different specific embodiments, and the details in this Specification can be modified or changed without deviating from the spirit of the invention based on different 7 viewpoints and applications. It is important to note that, without conflicts, the following embodiments and the characteristics of the embodiments can be combined with each other.
It is important to note that the diagrams provided in the following embodiments only describe the basic concept of the present invention by indication, and that the diagrams show only the components connected with the present invention, rather than being drawn with the number, shape and size of the components at the time of actual embodiment, and that the types, quantities and proportions of the components at the time of actual embodiment may be changed at will, and its component layout may be more complex.
For a clearer description of the technical scheme, the specific embodiment of the present invention is as follows: Supposing F, represents q order (¢=2") finite field, a multiple LDPC code J =[n.k] based on the finite field # can be defined as the zero space of its sparse check matrix #=[4, | therein her . A codeword is a valid codeword for this LDPC code only if the message vector vel vv ) satisfies Hv’ =0.
First, defining two indexing sets: N, = {J 0<j<n-Lh # 0} The element represents the ordinal number of the column in which the non-zero element is located in the No.; line of the check matrix # ; M,={i:0<i<m-Lh_ = 0} The element represents the ordinal number of the row in which the non-zero element is located in the No.j column of the check matrix A.
As for a given check matrix H, the Normal diagram as shown in Figure 2 may be used to describe the decoding procedure of LDPC codes. In the Normal diagram, the edge represents a variable value and the vertex represents a kind of constraint condition. There are totally three nodes in the Normal diagram of the multiple LDPC codes, including a variable node (node V) representing each column of the check matrix, a check node (node C) representing each raw of the check matrix, and a intermediate node used to express the non-zero element in the check matrix, i.e. /, #0. In the Normal diagram, all the edges adjacent to the No j variable node must be the same variable value and the checksum represented by all the edges adjacent to the No. check node must be zero.
As shown in Figure 1, the present invention provides a multiple LDPC decoding method based on the code element reliability dominance node subset partition criterion, which includes: S1: Computing initialization information L779) according to the channel received value y; 8 and the given scale factor £, quantized bit number b and quantized interval A, and using the information truncation criterion to truncate the initialization information Ds); setting the current number of the iteration iter = 0; when conducting the first iterative decoding, making all the check nodes being in the check nodes processing subset A; S2: Judging the current number of the iteration ifer and the maximum number of iterations iter, , if the current number of the iteration iter is equal to the maximum number of iterations iter, then exiting the iterative decoding and outputting decoding results, if the current number of the iteration iter is less than the maximum number of iterations izer, then entering step S3; S3: Updating the check nodes in the processing subset of the check nodes M? according to the result of the check nodes partition, computing the external information Ly > (a) and truncating the information; S4: Replacing the external information Ly (a) of the check nodes according to the replacement rule of the intermediate nodes to obtain the information transmitted by the intermediate nodes to the neighboring variable nodes Ly (Gs); S5: Computing respectively the posterior probability information of the variable node Ly, (s) and the information vector Ly 2H (5) transmitted by the variable nodes 1; to the intermediate nodes +7, according to the updating rule of the variable nodes, and replacing the information Ly NOR S6: Conducting the decision decoding on each variable node according to v, =arg max, (s)} for0sjx<n-l; S7: Checking the result of the decision decoding, if #9” =0, then the decoding is finished, outputting the result of the decoding, otherwise entering step S8; S8: Partitioning the check nodes, of which the information needs to be updated in the next iteration, into the subset A4‘? according to the criterion of check nodes subset partition, at the same time, setting the number of iterations iter =iter +1, and jumping to step S2 for the next iterative decoding.
Now we will describe the specific steps of EMS algorithm based on the Normal diagram, mainly including information initialization, information truncation criterion, variable nodes, information transfer and processing between check nodes and intermediate nodes.
9
Considering a multiple LDPC code ¢ =[nk] in a fimte field F, ( g=2"), set v=(v, 1 v, Je Fas a codeword in which any code symbol can be represented by a binary vector v=(v vv of one bit, so for BPSK modulation, the codeword v can be mapped to a bipolar sequence: va aa) (1) When Osis<n-L0s<js<{-1, the relationship between the sequence and the codeword isx? =1-2v\" Then, the channel received value sequence of the bipolar sequence interfered by noise through the channel transfer is as follows: vs ee] (2) For a given channel received value y in step S1, the value of the initialization information can be computed in the following manner: First computing the likelihood information R,. (s) in the logarithmic domain: R. (s)= 53 y (1-257 ).se F, (3) Arey In the formula, s“’ refers to the No.i bit of the vector representation of this finite field symbol. Setting quantized interval A >0 and quantized bit number 5>1 as two parameters that need to be designed, the likelihood information of the logarithmic domain can be quantified into integer information according to the following rules with these two parameters. It 1s important to note that during the quantization process, 2°A should be large enough to ensure that the channel received values can be included more: 2" -D.R. /A<2"-]) LE (5) =1[R; (s)/AL|R,. (5)/A <2 1 (4) Q°-D,R‚(s)/Az2°-1 In the formula, [x] stands for a rounding operation, representing the integer nearest tox is obtained.
In step S3, updating the check nodes in the processing subset of the check nodes A according to the result of the check nodes partition, computing the external information Ly (a) and truncating the information; In this embodiment, the check nodes are partitioned based on the criterion of subset partition of check nodes based on reliability dominance. 10
For check node C;, the constraint condition that it represents is that the sum of all the variables represented by the edges adjacent to the No.7 check node must be zero. Set fy [i el je N} as the decision code element sets of the variable nodes connected with the check nodes C, when the No./ iteration is updated, and these code element sets participate in the checksum calculation of the Noi check equation: c= > h, 90 (5) Je In one iteration, the checksum exists in two cases: 1) The checksum does not satisfy the constraint condition of the check nodes, that is to sayc,= » h 0" =0, it means there is an error code element in the decision code set which jel; participates in the checksum calculation, so in the next iterative update, information update is needed for the check nodes.
2) When the checksum occurs c‚= > 4, -¥!"=0, there are also two kinds of cases existed in the JEN, decision code element set: (a) all the decision code element symbols in fy [i el je N} are correct symbols; (b) there are two or more error symbols in the decision code element symbol set, which can also make the checksum being zero. In the case of (a), since all the decision code elements are correct code symbols, the check nodes may not need to update the information when the next iteration is updated; in the case of (b), because of an error exists in the decision symbols, it is necessary to update the information of the check nodes at the next iteration.
In order to distinguish which case occurs when the checksum occurs c‚= > 4, =, this paper proposes a novel criterion for the subset partition of check nodes based on the code element reliability dominance to partition the check nodes that satisfy the checksum.
Firstly, the definition of reliability dominance of variable node decision code elements is given: ad, =max{Z, (9)} max” {r, ( s)} sek (6) In the formula, max’ represents the submaximum in vector ZL, (s).
For a variable node, the reliability dominance of code elements means the degree of dominance in possibility of the code element symbol with the highest reliability degree compared to the code element symbol with the second highest reliability degree.
Based on the check node subset partition criterion proposed by the invention, the check nodes of the checksum ¢ => 4, 9-0 is partitioned into processing/non-processing nodes, in which a jeN,
I common feature of the non-processing nodes is that: the reliability dominance of the decision code elements of the variable nodes adjacent to the check nodes is large enough, that is, compared with other symbols, this finite field symbol is more likely to be used as the correct decision decoding result.
Supposing mi’ represents the tag of the No; variable node in the No./ iterative decoding, if the code element reliability dominance of the variable node exceeds a threshold value 7, then the variable node is considered to be reliable enough, and is tagged as 0; otherwise, the variable nodes is tagged as 1, that is: 0 fo. ad, 2, | VL ad, <T, (7) therein 0x j<n-1, the threshold value I is determined by the following formula: T= san | (8) ni In the formula, & 1s a correction factor, which is determined by simulation. Assume that A" is a set of all check nodes, MY cM! is a set of check nodes of which the information needs to be updated in the No./ iteration, and that the check nodes that are partitioned tothe set M are determined by the following formula: Ta M! ={e J ule |Z 22e of (9) AEN, therein, 0<i<m-1. At this point, all the check nodes are partitioned into two subsets, in which the node subset that does not need to be updated in the No./ iterative decoding is MM) M©. Information Truncation of External Information: For a given logarithmic domain information vector L.(s).seF,, its finite field is partitioned into two parts according to some criterion. For M-EMS algorithm, the basis of partition is as follows: Fe = SF, Luis oneoftheMmasvaluss § (10) According to subset 7, , the information truncation criterion for vector I, (s).seF, can be defined as follows: - L.(s}—-L,.if seF, b +) - i! on : ( 1) therein, I, = min /,. (5). In step S4, the replacement rules for intermediate nodes are: 12
The information of the variable nodes 7° transmitted to the check nodes C, through the intermediate nodes #, is replaced as the following formula: ho “(y= is W(hs).seF, (12) The information that is transmitted to the variable nodes 1, through the intermediate nodes H, from the check nodes C, is replaced according to the following formula: ij 577) (s)= hi PMs), € FE (13) In step S35, the update rule for the variable nodes is: During iterative decoding, the variable nodes +, receive the information Ls) transmitted by the connected intermediate nodes #, and update it according to the following rule: (i=) {17,17} L (sy=L""(s)+ >. Ly (8).5eF, (14) ’ ! ied, ’ The external information 1 (s) that the variable nodes 1 transmit to the intermediate nodes #, is computed in the following way: BM (5) = (sE (5) se F, (15) The update of the multiple LDPC code check nodes is computed by using the forward-backward iterative process on the Trellis diagram.
First, we define the following two vectors, = (eo, (0).a, (1)..« (g-1)) and g =(4(0), 5 (1). 8 (¢-1)) as the forward iteration vector and the backward iteration vector, respectively.
The computational process is as follows: Forward Iterative Process Giveng, =(0.-0%. 0), d, indicating the degree of the No.; check node, for 0<7<d —1 and Vs € GF (gq), making the iterative computation: o,., (5) = max fa, (s—z) +A" ~} 8) SEF, (16) Backward Iterative Process Given pg, =(9,-x,… 0), d, indicating the degree of the No.i check node, for d, >7/>1 and VseGF(q), making the tierative computation B{s)= max] (s=z)+ 4) (=) seF, (17) External Information Extraction For 0<t<d 1 and VseGH(g), using the following formula to compute the external 13 information transmitted by the check nodes to the intermediate nodes: I of) (a) =max{%4 (s)+B(s+a)}, seF, (18) Information Post-processing For O<t<d, -t, computing: ia i Eil, omer es, (19) In the formula, & is a scale factor.
In this paper, we consider using a regular check matrix H, based on a finite field © with its parameters "=%n =88 19 condor an experiment. The row weight and column weight of this matrix are respectively + = +d =2 The decoding performance of the algorithm is measured by bit error rate (BER), and in order to compare the computational complexity of each decoding algorithm crosswise, it is measured by using the ratio of the total number of check nodes (complexity ratio) of information update in different algorithms compared with the M-EMS algorithm without partition of subsets: pe (20) Experiment 1: The regular multiple LDPC codes defined in finite field F,, with the parameters of the check matrix m=44,n=88 In the present invention, we consider comparing the performance and computational complexity of M-EMS algorithm without using node subset partition criteria, M-EMS algorithm adopting existing subset partition criteria (abbreviated as kM-EMS), and M-EMS algorithm adopting the node partition criterion based on code element reliability dominance provided in this paper (abbreviated as advM-EMS) under different SNR. For the M-EMS algorithm, set its parameter as 4/=32; for the kM-EMS algorithm, the parameters are given as 4/=32 and 7,=150; and for the advM-EMS algorithm, the correction factor is 3=0.9. For all decoding algorithms, the relevant parameters are set as £=09.b=8A=1/64.
Figure 3 shows the bit error rate (BER) of various algorithms in different channel SNR environments. As we can see from the figure, the advM-EMS algorithm adopting the node partition criterion provided in the present invention is of better error correction performance than the check node subset partition criterion proposed by the kM-EMS algorithm under all SNR conditions, at the 14 same time, comparing with the M-EMS algorithm without using node subset partition criteria, its performance lost about 0.4dB.
According to the complexity ratio of various algorithms shown in Figure 4, compared with M-EMS algorithm, the complexity ratio of advM-EMS algorithm is only about 0.7 when the SNR is E/N,=1/22/2.6/3.0(dB). In the meanwhile, in all SNR conditions, compared with M-EMS algorithm, the advM-EMS algorithm can get stronger error correction performance with lower complexity ratio.
A multiple LDPC decoding device based on the code element reliability dominance node subset partition criterion used for channel coding, which includes: An initialization module, which is used to calculate the initialization information L770 (s) according to the channel received value y and the given scale factor? , quantized bit number? | and quantized interval A, and by the information truncation criterion to truncate the initialization information Lo (s); setting the current number of the iteration iter = 0; when conducting the first iterative decoding, all the check nodes are in the check nodes processing subset A4“; A judgment module, which is used to judge the current number of the iteration iter and the maximum number of iterations ifer, if the current number of the iteration iter is equal to the maximum number of iterations iter exiting the iterative decoding and outputting the decoding result, and if the current number of the iteration ifer is less than the maximum number of iterationiter, entering the iterative decoding process, A check nodes update module, which is used to update the check nodes in the processing subset of the check nodes M) according to the result of partition of the check nodes, to calculate the external information I; a (a) and to truncate the information; An intermediate nodes replacement module, which is used to replace the external information Ly 2 (a) of the check nodes according to the replacement rule of the intermediate nodes to get the information Ly ”(s) transmitted by the intermediate nodes to the adjacent variable nodes, and to replace Le” (s) according to the replacement rule to get the information EG) transmitted by the intermediate nodes #7, to the adjacent check nodes; A variable nodes update module, which is used to calculate separately the posterior probability information of the variable nodes Ly (s) and the external information L575) that transmitted by 15 the variable nodes 1 to the intermediate nodes #, according to the updating rule of the variable nodes; A decoding decision module, which is used for decision decoding of each variable node according to $, =arg max {L. (s)} for0 < j<n-1, and at the same time, for checking the result of seh, í the decision decoding, if HV’ = 0 the decoding is finished, and the decoding result is outputted, A check nodes partition module, which is used to partition the check nodes, of which the information needs to be updated in the next iteration, into the subset M ’according to the criterion of the check nodes subset partition, and at the same time, to set the number of iterations as iter =iter +1 to proceed to the next iterative decoding.
In one embodiment, for a given channel received value y, the value of the initialization information is computed in the following way; First computing the likelihood information R,. (s) in the logarithmic domain: Io © Re (s) = yl > Yi (1 == 2s ). se Fk, ’ ist In the formula, s‘? refers to the No.i bit of the vector representation of this finite field symbol, F‚ represents the finite field of ¢ order. The likelihood information of the logarithmic domain is quantified into integer information according to the quantized interval A > 0, the quantized bit number »>1 and the following rules; CC D,R IA<—(2" 1) LPs) =[R,, (5)/ AL|R- (5)/ A <2" 1 2" -D.R.,(s)/A=2"-1 In the formula, [x] stands for a rounding operation, representing the integer nearest tox is obtained.
In one embodiment, the update rule for the variable nodes is: The variable nodes J, receive information Ly “2 from the connected intermediate nodes H, and update the information according to the following rule: L. (8) = Ly” fl (5) + >, Ls =) (s), sE F, ) ieM, The external information LD (s) that the variable nodes J, transmit to the intermediate 16 nodes H, is computed in the following way: FH) (Hy, = ee LYS) = (s)- Ly, 7 seF In one embodiment, the information truncation criteria are: |L) Li s€F, L, (s) _ f O3 A — 0, otherwise L,.(s) represents the logarithmic domain information vector,. Fy = is = F, Lefshis one ofthe dM max values } L, — min L. (s). Sef, In one embodiment, the check nodes are updated, including: Two vectors «, =(2,(0), 0,0), a, (g-D) and f, =(8(0), 8,01), .B,(q 1) are defined as the forward iteration vector and the backward iteration vector, respectively.
The computational process is as follows: Forward Iterative Process: Givena, =(0,—,...,—c), d indicating the degree of the No.i check node, for 0 <t <d, -1 and Vs e GF (q), making the erative computation: ) = maxta (5-2) + se OE = max{q;(s —z) +L (2)},s el, Backward Iterative Process: Given B, =(0,—»,..,—»), d. indicating the degree of the No.; check node, for d >1>1 and Vs e GF (q), raking the erative computation: CN FH GY, . Bs)=max{f(s—z) +L," "(2)}, sel sel, J External Information Extraction: For Ostsd, —1 and YseGFH(g), using the following formula to compute the external information transmitted by the check nodes to the intermediate nodes: OR a ì LE" (a) = max {a (5) + B, (s+) s < F, Information Post-processing: For 0<¢<d, —1, computing: LT ay = Ca a ; s > jmin{ LT}, Other: L : In the formula, ¢ is a scale factor. 17
In one embodiment, the replacement rules of the intermediate nodes are: The information of the variable nodes !, transmitted to the check nodes C, through the intermediate nodes #, is replaced according to the following formula: (H,->C) HH ,) L770 (s)y= Ly 7 (bys), s € F, The information that is transmitted to the variable nodes 1 through the intermediate nodes H, from the check nodes C, is replaced according to the following formula: LE) = (hs, s € Fo In one embodiment, the check nodes are partitioned according to the criterion of subset partition of check nodes based on reliability dominance.
In one embodiment, for a variable node, reliability dominance adv, means the degree of dominance in possibility of the code element symbol with the highest reliability degree compared to the code element symbol with the second highest reliability degree.
adv, =max{L, (s)}-max"{L, (s)},s€F, In the formula, max’ represents the submaximum in vector Z;- (S).
Optionally, the multiple LDPC decoding method based on the code element reliability dominance node subset partition criterion is characterized in that the check nodes of the checksum ¢, => h,-#"=0 are partitioned according to the criterion of subset partition of the check nodes based JEN, on reliability dominance, and the subset partition criterion is as follows: Mó{ce ule [zw 2, of
AVE The check nodes are partitioned into the processing nodes subset and non-processing nodes subset. The check nodes in the processing nodes subset is characterized in that its checksum is not zero, or its checksum is zero, but the code element reliability dominance of two or more variable nodes in the adjacent is less than the threshold value 7, .
It is important to note that since the embodiment of the part of the device corresponds to the embodiment of the part of the method, the contents of the embodiment of the part of the device please refer to the description in the embodiment of the part of the method, and no unnecessary details are given here.
The invention also provides a storage medium used for storing computer programs. The computer programs are executed by the method described above when it is running by a processor. 18
The invention also provides an electronic terminal comprising: A memory used to store computer programs; A processor used to execute the computer programs stored by the memory, so that the device can execute the aforementioned method.
The computer programs comprise computer program codes, which may be in the form of source codes, object codes, executable files, or some intermediate forms, etc. The computer readable medium may include: any entity or device capable of carrying the computer program codes, a recording medium, a U-disk, a mobile hard disk, a disk, a optical disk, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal and a software distribution medium, etc.
The processor may be a central processing unit (CPU) or other general purpose processors, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, a discrete gate or a transistor logic device, a discrete hardware component, etc. The general-purpose processors can be a microprocessor, or it can be any conventional processor, etc.
The memory may be an internal storage unit or an external storage device, such as a plug-in hard disk, a smart media card (SMC), a secure digital card (SD), a flash memory card (Flash Card), etc. Further, the memory may include both an internal storage unit and an external storage device. The memory is used to store the computer programs and other programs and data. The storage can also be used to temporarily store data that has been or 1s to be outputted.
Technicians in the field can clearly understand that, in order to describe conveniently and simply, we only take the divisions of the above-mentioned functional units and modules as examples, in practical applications, the above functions can be allocated to different functional units and modules to be completed according to the needs, that is, the internal structure of the device will be divided into different functional units or modules to complete all or part of the functions described above. In the embodiment, each functional unit and module can be integrated in one processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The integrated unit can be realized either in the form of hardware or in the form of software functional unit. In addition, the specific names of each functional unit and module are only for the convenience of distinction, and are not used to limit the scope of protection of this application. The specific working process of the unit and module in the above-mentioned system can be referred to the corresponding process in the embodiment of the aforementioned method, and no unnecessary details are given here.
In the above-mentioned embodiments, the descriptions of each embodiment have their own 19 emphasis, and the parts of one embodiment that are not specified or documented can be seen in the relevant descriptions of other embodiments. The common technicians in this field can realize that the units and algorithm steps of each example described in the embodiment disclosed in this paper can be realized by electronic hardware or the combination of computer software and electronic hardware. Whether these functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods for each particular application to realize the functions described, but such a realization should not be considered beyond the scope of the invention.
In the embodiments provided by the invention, it should be understood that the device/terminal device and method disclosed can be executed in other ways. For example, the device/terminal device embodiments described above are only demonstrative; for example, the division of the modules or units 1s simply a logical functional division, and there can be additional dividing ways when actualization, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. On the other hand, the reciprocal coupling or direct coupling or communication connection that is shown or discussed may be an indirect coupling or communication connection through some interfaces, devices or units, and may be electrical, mechanical or otherwise.
The above embodiments only illustrate the principle and effect of the invention, and is not used to limit the invention. Any person familiar with the technique may modify or alter the above embodiments without contravening the spirit and scope of the invention. Therefore, all equivalent modifications or alterations performed by persons with general knowledge in the technical field which are not separated from the spirit and technical ideas disclosed in the present invention shall be covered by the Claims of the present invention.
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---|
GUOJUN HAN ET AL: "Check Node Reliability-Based Scheduling for BP Decoding of Non-Binary LDPC Codes", IEEE TRANSACTIONS ON COMMUNICATIONS, IEEE SERVICE CENTER, PISCATAWAY, NJ. USA, vol. 61, no. 3, 1 March 2013 (2013-03-01), pages 877 - 885, XP011504976, ISSN: 0090-6778, DOI: 10.1109/TCOMM.2013.011613.120249 * |
VOICILA A ET AL: "Low-Complexity, Low-Memory EMS Algorithm for Non-Binary LDPC Codes", PROCEEDINGS OF THE 2007 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS (ICC 2007), 24-28 JUNE 2007, GLASGOW, UK, IEEE, PISCATAWAY, NJ, USA, 1 June 2007 (2007-06-01), pages 671 - 676, XP031125748, ISBN: 978-1-4244-0353-0 * |
XIAO MA ET AL: "Low Complexity X-EMS Algorithms for Nonbinary LDPC Codes", IEEE TRANSACTIONS ON COMMUNICATIONS, IEEE SERVICE CENTER, PISCATAWAY, NJ. USA, vol. 60, no. 1, 1 January 2012 (2012-01-01), pages 9 - 13, XP011413196, ISSN: 0090-6778, DOI: 10.1109/TCOMM.2011.092011.110082 * |
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