NL2003510C2 - Photovoltaic cell and method for fabricating a photovoltaic cell. - Google Patents
Photovoltaic cell and method for fabricating a photovoltaic cell. Download PDFInfo
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- NL2003510C2 NL2003510C2 NL2003510A NL2003510A NL2003510C2 NL 2003510 C2 NL2003510 C2 NL 2003510C2 NL 2003510 A NL2003510 A NL 2003510A NL 2003510 A NL2003510 A NL 2003510A NL 2003510 C2 NL2003510 C2 NL 2003510C2
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- photovoltaic element
- based substrate
- monocrystalline silicon
- semiconductor substrate
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- 238000000034 method Methods 0.000 title claims description 65
- 239000000758 substrate Substances 0.000 claims description 148
- 239000004065 semiconductor Substances 0.000 claims description 75
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 41
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 23
- 229910052710 silicon Inorganic materials 0.000 claims description 23
- 239000010703 silicon Substances 0.000 claims description 23
- 239000004020 conductor Substances 0.000 claims description 18
- 230000005855 radiation Effects 0.000 claims description 18
- 239000013078 crystal Substances 0.000 claims description 12
- 230000003287 optical effect Effects 0.000 claims description 10
- 238000003486 chemical etching Methods 0.000 claims description 7
- 239000002019 doping agent Substances 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 229910004205 SiNX Inorganic materials 0.000 claims description 5
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims description 5
- 238000000608 laser ablation Methods 0.000 claims description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 239000002210 silicon-based material Substances 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 238000003631 wet chemical etching Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 description 15
- 239000002800 charge carrier Substances 0.000 description 8
- 238000002955 isolation Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 239000000969 carrier Substances 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 238000005215 recombination Methods 0.000 description 4
- 230000006798 recombination Effects 0.000 description 4
- 238000002161 passivation Methods 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000002679 ablation Methods 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000005381 potential energy Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Life Sciences & Earth Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Sustainable Development (AREA)
- Photovoltaic Devices (AREA)
Description
Photovoltaic cell and method for fabricating a photovoltaic cell
The present invention relates to a photovoltaic cell, for example a solar cell, comprising a semiconductor substrate having a front side and a back side, wherein at 5 least one layer of electrically conductive material is present at the front side and back side of the semiconductor substrate. The present invention further relates to a method for fabricating such a photovoltaic cell.
Photovoltaic cells may have a semiconductor substrate comprising silicon-based material. The silicon-based substrate has a front side and a back side. At the front side 10 radiation, for example sunlight, may be received. Depending on the design of the photovoltaic cell, non-rectifying electrical contacts that may connect the photovoltaic cell to an external electrical load may be applied at both the front side and back side or only at the back side of the substrate. Photovoltaic cells with electrical contacts that are arranged both on the front side and back side are commonly known as front contact 15 cells. Photovoltaic cells with electrical contacts at the back side of the semiconductor substrate are commonly indicated as back contact cells. In the case of a front contact cell the electrical contacts at the front side of the substrate are patterned such that blocking of the incident radiation is substantially minimized.
Due to the relatively large difference between the refractive indices of silicon-20 based material and air a significant amount of incident radiation may be reflected at the interface between the air and the front side of the silicon-based substrate. To improve the coupling of the incident radiation to the silicon-based substrate and consequently to increase the generation of a photocurrent that can be extracted from the photovoltaic cell an anti reflection coating (ARC) may be applied at the front side of the silicon-25 based substrate.
The silicon-based substrate may be provided with dopant atoms to substantially achieve an n-type or p-type doping. A photocurrent that is extracted from the photovoltaic cell comprises charge carriers generated by incident photons substantially in a depletion region of a p-n junction in the silicon-based substrate. In the case of a p-30 type doped monocrystalline silicon-based substrate an n-type doped emitter is applied to form the p-n junction. In the case of an n-type doped mono crystalline silicon-based substrate the emitter is p-type doped. Depending on the design of the photovoltaic cell, 2 the emitter can be fabricated at the front side or at the back side of the semiconductor substrate.
The life time of generated excess minority carriers, i.e. holes in the case of an n-type doped silicon-based substrate and electrons in the case of a p-type doped silicon-5 based substrate, is substantially increased by a surface field portion. Depending on the design of the photovoltaic cell the surface field portion is provided by significantly increasing the doping level of the silicon-based substrate at its front side or at its back side. The surface field portion substantially increases the probability that the generated excess minority carriers reach the electrical contacts before recombining with excess 10 majority carriers. As a result, the photocurrent that can be extracted from the photovoltaic cell is substantially being improved.
In the case of a photovoltaic cell having for example an n-type doped monocrystalline silicon-based substrate, wherein the p-type doped emitter is fabricated at the front side and the electrical contacts are arranged at both the front side and the 15 back side of the silicon-based substrate, a so-called back surface field portion is provided by significantly increasing the doping level of the n-type doped silicon-based substrate at the surface of the back side adjacent to the electrical contacts. A resulting n+-doping level of the back surface field portion provides a potential energy barrier for the generated excess minority carriers, i.e. holes. This potential barrier substantially 20 confines the generated excess minority carriers to the n-type doped silicon-based substrate and drives them towards the electrical contacts at the front side of the silicon-based substrate.
As a result of the fabrication of the abovementioned photovoltaic cell at least one layer of electrically conductive material may be present on the semiconductor substrate 25 in such a way that it substantially provides an undesired electrical connection between the front side and back side of the substrate.
It is known that in photovoltaic cells the undesired electrically conductive connection, which comprises at least one layer of electrically conductive material and is located substantially between the front side and the back side of the semiconductor 30 substrate, is disrupted at the front side of the semiconductor substrate.
A drawback of this approach may be that parts of the front side, for example the outer perimeter, no longer contribute to the electrical power performance of the photovoltaic cell. Other drawbacks may be that valuable material of the front side of 3 the photovoltaic cell is wasted and the electrical power performance of the photovoltaic cell is reduced.
It is an object of the present invention to provide a photovoltaic cell wherein at least one of the abovementioned drawbacks is obviated or at least reduced. It is a 5 further object of the present invention to provide a photovoltaic cell wherein the entire front side of the semiconductor substrate contributes to the electrical power performance of the photovoltaic cell. An even further object of the present invention is to provide a photovoltaic cell wherein substantially no valuable material of the front side is wasted and the electrical power performance is increased. It is another object of 10 the present invention to provide a method for fabricating a photovoltaic cell according to the present invention.
At least one of the objects may be achieved by a photovoltaic cell according to the present invention wherein at least one groove has been applied at the back side of the semiconductor substrate to electrically isolate the front side and back side. By applying 15 at least one groove at the back side of the semiconductor substrate no material at the front side is removed and the entire front side of the substrate can contribute to the electrical power performance of the photovoltaic cell. Although the electrically conductive material may be removed from the side surfaces of the semiconductor substrate this still may lead to wasting valuable material of the substrate of the 20 photovoltaic cell. In addition, process complexity may be increased due to additional process steps that may have to be introduced.
In a preferred embodiment of the present invention, the at least one groove at the back side of the semiconductor substrate is applied to at least part of the at least one layer of electrically conductive material. This may increase the shunt resistance 25 between the front side and back side of the semiconductor substrate that is formed by the at least one layer of electrically conductive material. To substantially maximize the electrical isolation of the front side and the back side of the semiconductor substrate the at least one groove preferably completely disrupts the at least one layer of electrically conductive material at the back side of the semiconductor substrate.
30 In another embodiment of the present invention, the at least one groove at the back side of the semiconductor substrate is a closed loop structure. The at least one groove could also be applied as a line or an arrangement of lines or any other non-closed structure. However, application of the at least one groove at the back side as a closed 4 loop structure, such as a square or a circle or any other arbitrary closed loop shape, may provide a better electrical isolation of the front side and back side of the semiconductor substrate. An arbitrary closed loop shape can be formed using a vision system that scans the outer perimeter of the semiconductor substrate to determine the shape of its 5 edges and to detect irregularities, for example chipping effects, in them. The vision system then determines the exact shape of the closed loop structure and the distance at which it may be applied with respect to the outer perimeter of the semiconductor substrate.
In an embodiment of the present invention, the semiconductor substrate is a silicon-10 based substrate. Although the electrical isolation of the front side and back side of the semiconductor substrate does not depend on the kind of semiconductor substrate material, silicon-based substrates may preferably be used mainly because of cost considerations.
In a further embodiment of the present invention, the silicon-based substrate has a 15 monocrystalline crystal structure. A monocrystalline silicon-based substrate may preferably be used because of the generally superior material properties compared to those of polycrystalline or amorphous silicon-based substrates that may positively affect the electrical power performance of the photovoltaic cell. However, for the isolation of the front side and the back side by the application of the at least one groove 20 at the back side of the semiconductor substrate, the crystal structure may be of little relevance.
In yet a further embodiment of the present invention, the monocrystalline silicon-based substrate comprises dopant atoms of a type that substantially dope at least part of the monocrystalline silicon-based substrate n-type or p-type.
25 In an embodiment of the present invention, the at least one groove at the back side of the mono crystalline silicon-based substrate is applied using a chemical etching process or a mechanical device or an optical device.
In another embodiment of the present invention, the mechanical device comprises a sawing blade to apply the at least one groove at the back side of the monocrystalline 30 silicon-based substrate.
In yet another embodiment of the present invention, the optical device comprises a laser diode to apply the at least one groove at the back side of the monocrystalline silicon-based substrate.
5
In an embodiment of the present invention, the laser diode emits radiation at a wavelength in a range of approximately 780 nm to 1150 nm, in particular in the range of approximately 1040 nm to 1080 nm, for instance approximately 1064 nm.
In a further embodiment of the present invention, the at least one groove at the back 5 side of the monocrystalline silicon-based substrate is applied using a laser ablation process. Although continuous wave laser diodes can be used for the ablation process, pulsed laser diodes generally are preferred as the heat generation in the semiconductor substrate as a result of the laser ablation process may better be controlled.
In an embodiment of the present invention, an anti reflection coating (ARC) is 10 provided at least at the back side of the monocrystalline silicon-based substrate. An ARC may be provided at the front side of the semiconductor substrate to increase the coupling of the incident radiation to the semiconductor substrate and to provide good surface passivation which leads to reduced surface recombination and consequently increased electrical power performance of the photovoltaic cell. By applying the ARC 15 layer at the back side of the substrate good surface passivation and improved coupling of radiation to the back side of the substrate may be provided.
In another embodiment of the present invention, the ARC comprises at least a silicon nitride (SiNx) layer. However, the ARC can comprise any suitable material that reduces the reflection of radiation incident at the air-semiconductor interface, for 20 example silicon oxide (SiOx).
In a further embodiment of the present invention, the ARC is applied using an atmospheric or low pressure chemical vapor deposition process at an ambient temperature in the range of approximately 350°C to 500°C, in particular in the range of approximately 380°C to 425°C, for instance approximately 400°C. The ARC can be 25 applied using any suitable process such as electron cyclotron resonance (ECR) deposition or plasma enhanced chemical vapor deposition (PECVD).
In an embodiment of the present invention, electrical contacts are arranged at the front side and back side of the monocrystalline silicon-based substrate. Photovoltaic cells with electrical contacts that may supply the photocurrent to an external electrical 30 load that are arranged both on the front side and back side of the semiconductor substrate are generally known as front contact cells. Photovoltaic cells with electrical contacts substantially at the back side of the semiconductor substrate are generally 6 indicated as back contact cells. The isolation of the front side and back side of the semiconductor substrate may be most advantageous for front contact cells.
In another embodiment of the present invention, the electrical contacts at the front side of the monocrystalline silicon-based substrate have an H-pattem. The H-5 pattern generally comprises two bus bars that interconnect the individual electrical contacts which are arranged in a direction substantially perpendicular to the bus bars.
In a further embodiment of the present invention, the photovoltaic cell has a semi square or substantially square shape.
According to another aspect of the present invention a method for fabricating a 10 photovoltaic cell, for example a solar cell, is provided. The photovoltaic cell comprises a semiconductor substrate having a front side and a back side, wherein at least one layer of electrically conductive material is present at the front side and back side of the semiconductor substrate, the method comprising of the application of at least one groove to the backside of the semiconductor substrate to electrically isolate the front 15 side and the back side.
In an embodiment of the present invention, the method comprises that the at least one groove at the back side of the semiconductor substrate is applied to at least part of the at least one layer of electrically conductive material.
In another embodiment of the present invention, the method comprises that the at 20 least one groove at the back side of the semiconductor substrate is applied to form a closed loop structure.
In an embodiment of the present invention, the method comprises that a semiconductor substrate is applied comprising silicon-based material.
In another embodiment of the present invention, the method comprises that the 25 silicon-based substrate has a monocrystalline crystal structure.
In a further embodiment of the present invention, the method comprises that the monocrystalline silicon-based substrate is n-type or p-type doped.
In an embodiment of the present invention, the method comprises that the at least one groove at the back side of the monocrystalline silicon-based substrate is applied 30 using a chemical etching process or a mechanical device or an optical device.
In another embodiment of the present invention, the method comprises that the chemical etching process to apply the at least one groove at the back side of the 7 monocrystalline silicon-based substrate comprises wet chemical etching or plasma-assisted etching.
In an embodiment of the present invention, the method comprises that the mechanical device that is used for the application of the at least one groove at the back 5 side of the monocrystalline silicon-based substrate comprises a sawing blade.
In a further embodiment of the present invention, the method comprises that the optical device that is used for the application of the at least one groove at the back side of the monocrystalline silicon-based substrate comprises a laser diode.
In an embodiment of the present invention, the method comprises that the laser 10 diode emits radiation at a wavelength in a range of approximately 780 nm to 1150 nm, in particular in the range of approximately 1040 nm to 1080 nm, for instance approximately 1064 nm.
In another embodiment of the present invention, the method comprises that the at least one groove at the back side of the monocrystalline silicon-based substrate is 15 applied using a laser ablation or cutting process.
In an embodiment of the present invention, the method comprises that an anti reflection coating (ARC) is applied at least at the back side of the monocrystalline silicon-based substrate.
In a further embodiment of the present invention, the method comprises that the 20 ARC that is applied at least at the back side of the monocrystalline silicon-based substrate comprises at least a silicon nitride (SiNx) layer. However, the ARC can comprise any suitable material that reduces the reflection of radiation incident at the air-semiconductor interface, for example silicon oxide (SiOx).
In another embodiment of the present invention, the method comprises that the 25 ARC is applied using an atmospheric or low pressure chemical vapor deposition process at an ambient temperature in the range of approximately 350°C to 500°C, in particular in the range of approximately 380°C to 425°C, for instance approximately 400°C. The ARC can be applied using any suitable process, for example plasma enhanced chemical vapor deposition (PECVD).
30 In an embodiment of the present invention, the method comprises that electrical contacts are arranged at the front side and back side of the monocrystalline silicon-based substrate.
8
In another embodiment of the present invention, the method comprises that the electrical contacts at the front side are arranged in an H-pattem.
In a final embodiment of the present invention, the method comprises that the photovoltaic cell has a semi square or substantially square shape.
5 The invention will be explained in more detail below with reference to a few drawings in which illustrative embodiments of the invention are shown. The person skilled in the art will realize that other alternatives and equivalent embodiments of the invention can be conceived and reduced to practice without departing from the scope of the present invention.
10 Figure 1 shows a perspective view of a front contact photovoltaic cell according to an embodiment of the present invention.
Figure 2 schematically shows a cross sectional view of a semiconductor substrate of a photovoltaic cell.
Figure 3 schematically shows the undesired electrically conductive connection 15 between the front side and back side of the semiconductor substrate.
Figure 4 schematically shows the disruption of the at least one layer of electrically conductive material by the at least one groove at the back side of the semiconductor substrate.
Figure 5 schematically shows the at least one groove that is applied as a closed 20 loop structure at the back side of the semiconductor substrate.
The figures are not necessarily drawn to scale. In the figures identical components are denoted by the same reference numerals.
Figure 1 shows a perspective view of a front contact photovoltaic cell 1 according to an embodiment of the present invention. The photovoltaic cell 1 comprises a 25 semiconductor substrate 2 having a front side 3 and a back side. In the context of the present invention the back side comprises both the lying surface 4 and the side surfaces 20, 30.
The semiconductor substrate 2 may comprise silicon-based material, such as silicon (Si), silicon germanium (SiGe) or any other semiconductor material that is 30 suitable for fabricating photovoltaic cells, such as solar cells, for example gallium arsenide (GaAs) or germanium (Ge).
For relatively low-cost high-performance photovoltaic cells silicon-based monocrystalline substrates 2 are preferably used due to their generally superior material 9 properties compared to silicon-based substrates having polycrystalline or amorphous crystal structures. The material properties of monocrystalline silicon-based substrates generally are superior to those having a polycrystalline or amorphous crystal structure as the latter two types of crystal structures comprise a high density of grain boundaries 5 and other crystal imperfections, such as dislocations, defects or undesired impurities.
The life time of charge carriers in the bulk of the semiconductor substrate 2 is a very important parameter for the photocurrent and consequently the electrical power performance of the photovoltaic cell 1. The life time of charge carriers in the bulk of the semiconductor substrate 2 is longer in the case of a monocrystalline crystal 10 structure than in the case of a polycrystalline or amorphous crystal structure because a monocrystalline semiconductor substrate 2 comprises substantially no grain boundaries and has substantially fewer other crystal imperfections, such as dislocations, defects or undesired impurities that give rise to a high recombination rate of for example photogenerated charge carriers. As a result of the longer charge carrier life time in 15 monocrystalline semiconductor substrates 2 the photocurrent and electrical power that can be extracted from a photovoltaic cell 1 having such a semiconductor substrate have higher values.
A long charge carrier life time is preferred as the probability increases that charge carriers, which are generated by photons of radiation incident on the front side 3 of the 20 semiconductor substrate 2, can reach the electrical contacts 40 that are arranged either at both the front side 3 and lying surface 4 of the back side or only at lying surface 4. Photovoltaic cells with electrical contacts 40 that may supply the photocurrent to an external electrical load that are arranged both on the front side 3 and the lying surface 4 of the back side are commonly known as front contact cells, an example of which is 25 shown in Figure 1. Photovoltaic cells with electrical contacts substantially at the lying surface 4 of the back side of the semiconductor substrate 2 are commonly indicated as back contact cells.
The electrical contacts 40 on the front side 3 of front contact cells may have an H-pattem. The H-pattem generally comprises two bus bars 50 that interconnect the 30 individual electrical contacts 40 which are arranged in a direction substantially perpendicular to the bus bars 50 as is shown in Figure 1. Also in the case that three bus bars 50 are used to interconnect the electrical contacts 40, the designation H-pattem is used.
10
Referring to Figure 2, a semiconductor substrate 2 is schematically shown having a front side 3 and a back side 4, 20, 30. At the front side 3 an emitter 5 is provided by doping the substrate material. The dopant atoms may end up not only at the front side 3 of the substrate 2 but also at the side surfaces 20, 30. Similarly, a back surface field 5 portion 6 is provided at the lying surface 4. Also in this case, the dopant atoms may end up at the side surfaces 20, 30. This is schematically shown by the portions 7.
As a result of the abovementioned doping processes wherein an emitter 5 and back surface field portion 6 are formed at the front side 3 and at the lying surface 4 of the back side of the semiconductor substrate 2 respectively, one or more electrically 10 conductive layers are present at the front side 3 and back side 4, 20, 30. This causes the front side 3 and lying surface 4 to be electrically connected by portions 7 as is schematically shown in Figure 3. The at least one layer of electrically conductive material may comprise dopant atoms that are used to dope the emitter 5 n-type or p-type and dopant atoms that are used to dope the back surface field portion 6 n-type or 15 p-type depending on the type of doping present in the semiconductor substrate 2.
Due to the relatively large difference between the refractive indices of silicon-based material and air a significant amount of incident radiation may be reflected at the interface between the air and the front side of the silicon-based substrate 2. Optionally, to improve the coupling of the incident radiation to the silicon-based substrate 2 and 20 consequently to increase the generation of a photocurrent that can be extracted from the photovoltaic cell 1 an anti reflection coating (ARC) 10 may be applied.
The ARC layer 10 may comprise any suitable material that reduces the reflection of radiation incident at the air-semiconductor interface, for example silicon oxide (SiOx). However, in a preferred embodiment of the present invention the ARC layer 10 25 that is applied at least at the lying surface 4 of the monocrystalline silicon-based substrate 2 comprises at least a silicon nitride (SiNx) layer.
The ARC layer 10 according to a preferred embodiment of the present invention is applied using an atmospheric or low pressure chemical vapor deposition process at an ambient temperature that typically lies in the range of approximately 350°C to 500°C, 30 in particular in the range of approximately 380°C to 425°C, for instance approximately 400°C. However, the ARC layer 10 can be applied using any suitable process such as plasma enhanced chemical vapor deposition (PECYD).
11
The life time of generated charge carriers may further be improved by also reducing recombination at the front side 3, the lying surface 4 and the side surfaces 20, 30 of the semiconductor substrate. A reduced surface recombination may be achieved by an ARC layer 10 that has been optimized to achieve a good surface passivation. For 5 that reason it may be beneficial to apply an ARC layer portion 10’ to the front side 3, an ARC layer portion 10” at the lying surface 4, and/or an ARC layer portion 10’” at the side surfaces 20, 30 of the semiconductor substrate 2 as is also schematically shown in Figure 3.
To increase the electrical isolation between the front side 3 and the back side, 10 which in the context of the present invention comprises both the lying surface 4 and the side surfaces 20, 30, at least one groove or channel or any similar disruptive structure 8 is applied to physically separate the front side and back side. In an embodiment of the present invention the at least one groove 8 is applied at the lying surface 4. In this case there is no reason to remove any material at the front side 3 of the semiconductor 15 substrate 2 to isolate the front side 3 and back side. This implies that the entire front side 3 of the substrate 2 can contribute to the electrical power performance of the photovoltaic cell 1. This is schematically shown in Figure 4.
By applying the at least one groove 8 the shunt resistance that is formed by the at least one layer of electrically conductive material may be increased. By choosing a 20 suitable depth of the groove 8 the value of the shunt resistance may be tuned.
The groove 8 may be applied to the ARC layer portion 10” and at least to part of the at least one layer of electrically conductive material at the lying surface 4 of the semiconductor substrate 2 using a chemical etching process or a mechanical device or an optical device.
25 In a preferred embodiment of the present invention the at least one groove 8 is applied by an optical device comprising for example a laser diode that emits radiation at a wavelength that typically lies in the range of approximately 780 nm to 1150 nm, in particular in the range of approximately 1040 nm to 1080 nm, for instance approximately 1064 nm. As the ARC layer 10 is present at the lying surface 4 it may be 30 used to couple radiation of the laser diode to the back side of the semiconductor substrate 2 to remove at least part of the at least one layer of electrically conductive material for the formation of the at least one groove 8.
12
Figure 5 schematically shows that the at least one groove 8 that is applied at the lying surface 4 of the semiconductor substrate 2 is a closed loop structure. The at least one groove could also be applied as a line or an arrangement of lines or any other non-closed structure. However, in a preferred embodiment of the present invention the at 5 least one groove 8 is a closed loop structure, such as a rectangle or a square or a circle or any other arbitrary closed loop shape, as it may provide a better electrical isolation of the front side 3 and back side of the semiconductor substrate 2.
Claims (35)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| NL2003510A NL2003510C2 (en) | 2009-09-18 | 2009-09-18 | Photovoltaic cell and method for fabricating a photovoltaic cell. |
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| Application Number | Priority Date | Filing Date | Title |
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| NL2003510 | 2009-09-18 | ||
| NL2003510A NL2003510C2 (en) | 2009-09-18 | 2009-09-18 | Photovoltaic cell and method for fabricating a photovoltaic cell. |
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| NL2003510A NL2003510C2 (en) | 2009-09-18 | 2009-09-18 | Photovoltaic cell and method for fabricating a photovoltaic cell. |
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Citations (6)
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|---|---|---|---|---|
| DE3316417A1 (en) * | 1983-05-05 | 1984-11-08 | Telefunken electronic GmbH, 7100 Heilbronn | SOLAR CELL |
| US4989059A (en) * | 1988-05-13 | 1991-01-29 | Mobil Solar Energy Corporation | Solar cell with trench through pn junction |
| US5665175A (en) * | 1990-05-30 | 1997-09-09 | Safir; Yakov | Bifacial solar cell |
| US5935344A (en) * | 1995-10-26 | 1999-08-10 | Sanyo Electric Co., Ltd. | Photovoltaic element and manufacturing method thereof |
| EP1378947A1 (en) * | 2002-07-01 | 2004-01-07 | Interuniversitair Microelektronica Centrum Vzw | Semiconductor etching paste and the use thereof for localised etching of semiconductor substrates |
| WO2009107955A2 (en) * | 2008-02-25 | 2009-09-03 | Lg Electronics Inc. | Solar cell and method for manufacturing the same |
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2009
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|---|---|---|---|---|
| DE3316417A1 (en) * | 1983-05-05 | 1984-11-08 | Telefunken electronic GmbH, 7100 Heilbronn | SOLAR CELL |
| US4989059A (en) * | 1988-05-13 | 1991-01-29 | Mobil Solar Energy Corporation | Solar cell with trench through pn junction |
| US5665175A (en) * | 1990-05-30 | 1997-09-09 | Safir; Yakov | Bifacial solar cell |
| US5935344A (en) * | 1995-10-26 | 1999-08-10 | Sanyo Electric Co., Ltd. | Photovoltaic element and manufacturing method thereof |
| EP1378947A1 (en) * | 2002-07-01 | 2004-01-07 | Interuniversitair Microelektronica Centrum Vzw | Semiconductor etching paste and the use thereof for localised etching of semiconductor substrates |
| WO2009107955A2 (en) * | 2008-02-25 | 2009-09-03 | Lg Electronics Inc. | Solar cell and method for manufacturing the same |
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| Title |
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| EMANUEL G ET AL: "HIGH THROUGHPUT LASER ISOLATION OF CRYSTALLINE SILICON SOLAR CELLS", 17TH. E.C. PHOTOVOLTAIC SOLAR ENERGY CONFERENCE. MUNICH, GERMANY, OCT. 22 - 26, 2001; [PROCEEDINGS OF THE INTERNATIONAL PHOTOVOLTAIC SOLAR ENERGY CONFERENCE], MUNICH : WIP-RENEWABLE ENERGIES, DE, vol. CONF. 17, 22 October 2001 (2001-10-22), pages 1578 - 1581, XP001139751, ISBN: 978-3-936338-08-9 * |
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