MY192587A - Binary weighted capacitor array with split capacitor layout - Google Patents
Binary weighted capacitor array with split capacitor layoutInfo
- Publication number
- MY192587A MY192587A MYPI2018001448A MYPI2018001448A MY192587A MY 192587 A MY192587 A MY 192587A MY PI2018001448 A MYPI2018001448 A MY PI2018001448A MY PI2018001448 A MYPI2018001448 A MY PI2018001448A MY 192587 A MY192587 A MY 192587A
- Authority
- MY
- Malaysia
- Prior art keywords
- binary weighted
- capacitor array
- top plate
- capacitor
- split capacitor
- Prior art date
Links
- 239000003990 capacitor Substances 0.000 title abstract 5
- 230000003071 parasitic effect Effects 0.000 abstract 3
- 239000000758 substrate Substances 0.000 abstract 2
- 239000002184 metal Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention discloses a method of building a binary weighted split capacitor array (1) for minimizing routing induced parasitic mismatch. Specifically, the binary weighted split capacitor array is built with a plurality of unit capacitors with three- dimensional structures having a top plate comprising a plurality of stacked metal plates (M2, M3, M4, M5) and a bottom plate enclosing the top plate with side walls, a floor layer and a ceiling layer to minimize top plate parasitic capacitance to the substrate, and to achieve overall equal parasitic capacitance to the substrate. (Figure 15)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
MYPI2018001448A MY192587A (en) | 2018-08-15 | 2018-08-15 | Binary weighted capacitor array with split capacitor layout |
PCT/MY2019/000031 WO2020036479A1 (en) | 2018-08-15 | 2019-07-26 | Binary weighted capacitor array with split capacitor layout |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
MYPI2018001448A MY192587A (en) | 2018-08-15 | 2018-08-15 | Binary weighted capacitor array with split capacitor layout |
Publications (1)
Publication Number | Publication Date |
---|---|
MY192587A true MY192587A (en) | 2022-08-29 |
Family
ID=69525735
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
MYPI2018001448A MY192587A (en) | 2018-08-15 | 2018-08-15 | Binary weighted capacitor array with split capacitor layout |
Country Status (2)
Country | Link |
---|---|
MY (1) | MY192587A (en) |
WO (1) | WO2020036479A1 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114726374B (en) * | 2022-04-22 | 2024-04-30 | 深圳市灵明光子科技有限公司 | Capacitor array structure |
CN114844503B (en) * | 2022-05-11 | 2024-05-14 | 上海交通大学 | Low-power-consumption successive approximation type analog-to-digital converter based on Split capacitor DAC |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7456462B1 (en) * | 2006-03-07 | 2008-11-25 | Alvand Technologies, Inc. | Fabricated U-shaped capacitor for a digital-to-analog converter |
US7473955B1 (en) * | 2006-03-07 | 2009-01-06 | Alvand Technologies, Inc. | Fabricated cylinder capacitor for a digital-to-analog converter |
US20140049872A1 (en) * | 2012-08-16 | 2014-02-20 | Himax Technologies Limited | Metal-oxide-metal capacitor able to reduce area of capacitor arrays |
CN104143982B (en) * | 2014-04-02 | 2017-11-10 | 上海菱沃铂智能技术有限公司 | A kind of small area DAC capacitor arrays for SAR types ADC |
WO2017168521A1 (en) * | 2016-03-28 | 2017-10-05 | オリンパス株式会社 | A/d converter and a/d conversion apparatus |
-
2018
- 2018-08-15 MY MYPI2018001448A patent/MY192587A/en unknown
-
2019
- 2019-07-26 WO PCT/MY2019/000031 patent/WO2020036479A1/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO2020036479A1 (en) | 2020-02-20 |
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