MY174802A - Apparatus and method of performing bit separation - Google Patents

Apparatus and method of performing bit separation

Info

Publication number
MY174802A
MY174802A MYPI2011700109A MYPI2011700109A MY174802A MY 174802 A MY174802 A MY 174802A MY PI2011700109 A MYPI2011700109 A MY PI2011700109A MY PI2011700109 A MYPI2011700109 A MY PI2011700109A MY 174802 A MY174802 A MY 174802A
Authority
MY
Malaysia
Prior art keywords
bit
marked
parity
register
switches
Prior art date
Application number
MYPI2011700109A
Inventor
Yusri Mohamad Yusof Mohamad
Prasad Devi
Santosh Palai Smruti
Original Assignee
Mimos Berhad
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mimos Berhad filed Critical Mimos Berhad
Priority to MYPI2011700109A priority Critical patent/MY174802A/en
Priority to PCT/MY2012/000136 priority patent/WO2013009162A1/en
Publication of MY174802A publication Critical patent/MY174802A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/766—Generation of all possible permutations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2757—Interleaver with an interleaving rule not provided for in the subgroups H03M13/2703 - H03M13/2753
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/276—Interleaving address generation
    • H03M13/2764—Circuits therefore
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6561—Parallelized implementations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H04L1/0043—Realisations of complexity reduction techniques, e.g. use of look-up tables
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Mathematical Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

A method of performing bit permutation by separating marked 1-bit and marked 0-bit is disclosed. The sequence of order of 1-bit marked bits position in a lower part of register is preserved while the sequence of order of 0-bit marked bits position in an upper part of register is reversed. The bit permutation is performed by providing a delta network (801, 803) of 2x2 switches (201 or 202), preferably flip network of 2x2 switches. The delta network is performed by a parity prefix generation circuit (600). The parity prefix generation circuit is performed by a plurality of XOR operators (601, 602, 603) to generate control signals.
MYPI2011700109A 2011-07-12 2011-07-12 Apparatus and method of performing bit separation MY174802A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
MYPI2011700109A MY174802A (en) 2011-07-12 2011-07-12 Apparatus and method of performing bit separation
PCT/MY2012/000136 WO2013009162A1 (en) 2011-07-12 2012-06-22 Method of providing signals to perform bit permutation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
MYPI2011700109A MY174802A (en) 2011-07-12 2011-07-12 Apparatus and method of performing bit separation

Publications (1)

Publication Number Publication Date
MY174802A true MY174802A (en) 2020-05-15

Family

ID=46800328

Family Applications (1)

Application Number Title Priority Date Filing Date
MYPI2011700109A MY174802A (en) 2011-07-12 2011-07-12 Apparatus and method of performing bit separation

Country Status (2)

Country Link
MY (1) MY174802A (en)
WO (1) WO2013009162A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
MY172620A (en) * 2014-01-22 2019-12-06 Mimos Berhad System and method for arbitrary bit pemutation using bit-separation and bit-distribution instructions

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4752777A (en) * 1985-03-18 1988-06-21 International Business Machines Corporation Delta network of a cross-point switch
AU2001288209A1 (en) * 2000-05-05 2001-11-26 Ruby B. Lee A method and system for performing permutations using permutation instructions based on modified omega and flip stages
US8285766B2 (en) * 2007-05-23 2012-10-09 The Trustees Of Princeton University Microprocessor shifter circuits utilizing butterfly and inverse butterfly routing circuits, and control circuits therefor
GB2456775B (en) * 2008-01-22 2012-10-31 Advanced Risc Mach Ltd Apparatus and method for performing permutation operations on data

Also Published As

Publication number Publication date
WO2013009162A1 (en) 2013-01-17

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