MY133444A - Motion compensated digital video decoding with buffered picture storage memory map - Google Patents

Motion compensated digital video decoding with buffered picture storage memory map

Info

Publication number
MY133444A
MY133444A MYPI9804250A MY133444A MY 133444 A MY133444 A MY 133444A MY PI9804250 A MYPI9804250 A MY PI9804250A MY 133444 A MY133444 A MY 133444A
Authority
MY
Malaysia
Prior art keywords
picture
memory
stored
pixel
data
Prior art date
Application number
Inventor
Shirish C Gadre
Edward J Paluch
Taner Ozcelik
Subroto Bose
Syed Reza
Original Assignee
Sony Electronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/001,129 external-priority patent/US6088047A/en
Priority claimed from US09/001,122 external-priority patent/US6215822B1/en
Application filed by Sony Electronics Inc filed Critical Sony Electronics Inc
Publication of MY133444A publication Critical patent/MY133444A/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/43—Hardware specially adapted for motion estimation or compensation
    • H04N19/433—Hardware specially adapted for motion estimation or compensation characterised by techniques for memory access
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
    • H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
    • H04N19/174—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a slice, e.g. a line of blocks or a group of blocks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
    • H04N19/187—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a scalable video layer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
    • H04N19/51—Motion estimation or motion compensation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding

Abstract

A DIGITAL VIDEO PRESENTATION SYSTEM (30) IS PROVIDED WITH HARDWARE AND SOFTWARE LOGIC FOR MAPPING THE PICTURE DATA INTO BUFFER MEMORY (48) IN A WAY THAT PERMITS BOTH THE READING OF MOTION VECTOR COMPENSATED MACROBLOCKS (S) OF DATA AND THE READING OF HORIZONTAL PICTURE WIDE SCAN LINES WITH A LOW NUMBER OF MEMORY PAGE CROSSINGS. PREFERABLY, THE MEMORY (48) IS A PLURALITY OF ROWS (74), FOR EXAMPLE 16 ROWS, WIDE. PREFERABLY, 16 LINES OF 8-PIXEL (TWO 32 PIXEL WIDE COLUMN) LINE SEGMENTS OF 8x8 PIXEL BLOCKS (A-P) ARE STORED IN CONSECUTIVE STORAGE LOCATIONS (76) FOLLOWED BY THE CONSECUTIVE STORAGE VERTICALLY ADJACENT LINE SEGMENTS UNTIL ONE LINE SEGMENT IS STORED IN EACH LOGICAL ROW (74) OF THE MEMORY (48). THEN THE NEXT HORIZONTALLY ADJACENT SET OF LINE SEGMENTS OF SIMILARLY STORED UNTIL THE RIGHT BOUNDARY OF THE PICTURE IS REACHED, THEN THE EACH ADDITIONAL ROW OF 16 LINES OF THE PICTURE SIMILARLY ARE STORED UNTIL THE BOTTOM OF THE PICTURE IS REACHED. EACH 16x16 PIXEL MACROBLOCK (S) OF DATA IS STORED ON A SINGLE PAGE (75); PREFERABLY, TWO HORIZONTALLY ADJACENT MACROBLOCKS (S) ARE STORED ON ONE PAGE OF MEMORY (48). EACH LINE OF THE PICTURE IS STORED IN CONTIGUOUS LOCATIONS ON THE SAME ROW OF THE MEMORY. THE MOTION COMPENSATION LOGIC (77) INTERPRETS MOTION VECTORS FROM THE INCOMING DATA (32) AND CALCULATES ADDRESSES FOR A MACROBLOCK (S) OF PICTURE DATA BY SEPARATING READ COMMANDS INTO SEPARATE COMMANDS WHERE A PAGE BOUNDARY DIVIDES THE MACROBLOCK INTO VERTICALLY ADJACENT RECTANGLES. MEMORY CONTROLLER LOGIC (50) FURTHER DIVIDES SUCH RECTANGLES WHERE THEY CROSS BOUNDARIES BETWEEN HORIZONTALLY ADJACENT PAGES OF THE MEMORY. ONE FIXED ADDRESS 8-HEX INCREMENT STEPS FROM LINE SEGMENT TO VERTICALLY ADJACENT LINE SEGMENT WHILE ANOTHER FIXED ADDRESS 80-HEX INCREMENT STEPS HORIZONTALLY FROM ONE 8-PIXEL LINE SEGMENT TO THE NEXT, SUCH AS ACROSS A SCAN LINE OF THE PICTURE.(FIG 8)
MYPI9804250 1997-09-19 1998-09-17 Motion compensated digital video decoding with buffered picture storage memory map MY133444A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US5967897P 1997-09-19 1997-09-19
US09/001,129 US6088047A (en) 1997-12-30 1997-12-30 Motion compensated digital video decoding with buffered picture storage memory map
US09/001,122 US6215822B1 (en) 1997-12-30 1997-12-30 Motion compensated digital video decoding and buffer memory addressing therefor

Publications (1)

Publication Number Publication Date
MY133444A true MY133444A (en) 2007-11-30

Family

ID=27356829

Family Applications (1)

Application Number Title Priority Date Filing Date
MYPI9804250 MY133444A (en) 1997-09-19 1998-09-17 Motion compensated digital video decoding with buffered picture storage memory map

Country Status (4)

Country Link
AU (1) AU9388298A (en)
MY (1) MY133444A (en)
TW (1) TW398153B (en)
WO (1) WO1999016252A1 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1051854A1 (en) * 1998-01-27 2000-11-15 Siemens Aktiengesellschaft Method and device for converting image data blocks into image lines
JPH11285004A (en) * 1998-03-31 1999-10-15 Nec Corp Moving image expander and its method
CN1309257C (en) * 2001-12-13 2007-04-04 联发科技股份有限公司 Video decoded memory accessing method
EP1331604A1 (en) * 2002-01-22 2003-07-30 Deutsche Thomson-Brandt Gmbh Method and device for memory access of block encoders/decoders
MY134659A (en) 2002-11-06 2007-12-31 Nokia Corp Picture buffering for prediction references and display
GB0323284D0 (en) 2003-10-04 2003-11-05 Koninkl Philips Electronics Nv Method and apparatus for processing image data
EP2104356A1 (en) * 2008-03-18 2009-09-23 Deutsche Thomson OHG Method and device for generating an image data stream, method and device for reconstructing a current image from an image data stream, image data stream and storage medium carrying an image data stream
WO2010014696A1 (en) * 2008-07-29 2010-02-04 Marvell World Trade, Ltd. Processing rasterized data
GB2501535A (en) 2012-04-26 2013-10-30 Sony Corp Chrominance Processing in High Efficiency Video Codecs

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2062200A1 (en) * 1991-03-15 1992-09-16 Stephen C. Purcell Decompression processor for video applications
TW245871B (en) * 1994-08-15 1995-04-21 Gen Instrument Corp Method and apparatus for efficient addressing of dram in a video decompression processor
DE4441295A1 (en) * 1994-11-21 1996-05-23 Sican Gmbh Method and circuit arrangement for addressing components of digital image data organized in blocks in a memory with page addressing
US6005624A (en) * 1996-12-20 1999-12-21 Lsi Logic Corporation System and method for performing motion compensation using a skewed tile storage format for improved efficiency

Also Published As

Publication number Publication date
TW398153B (en) 2000-07-11
WO1999016252A1 (en) 1999-04-01
AU9388298A (en) 1999-04-12

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