CONTROL CONNECTION FOR NON VOLATILE SEMICONDUCTOR MEMORY SETTING Field of the Invention The present invention relates to a control connection for a non-volatile semiconductor memory array, with a level transformer connection having an output value and a output value complementary to that output value in a bit path and / or a speech path of the accumulator array and with a closing connection, which intermediately stores the data to be stored in the semiconductor memory array. BACKGROUND OF THE INVENTION Such a control connection is known from EP 0 154 379 A2. SUMMARY OF THE INVENTION Non-volatile semiconductor memory arrays, such as flash memory or flash and electrically erasable programmable fixed value memory (EEPROM) need to attract or remove loads and with this data from individual memory cells typical voltages of 15V. These voltages, which essentially exceed the normal supply voltages VDD, which remain in the degree of magnitude of 5V, are referred to below as "high voltages". Depending on the type of operation, the high voltages are applied as words or bit conduction or also in word passages and bit conduits to the semiconductor memory array. Figure 2 schematically illustrates the structure of a so-called accumulation gate cell. This accumulation cell has a source zone and a drainage zone 2 in a semiconductor substrate 3. the source zone 1 and the drainage zone 2 are both doped type n + while the semiconductor substrate 3 has a doped type p. The source zone 1 and the drainage zone 2 as well as the channel region of the semiconductor substrate 3 between the source zone 1 and the drainage zone 2 are provided with a tunnel oxide layer 4 of for example silicon dioxide. In the tunnel oxide layer 4, in the region between the drainage zone 2 and the source zone 1, a floating gate 5 made of, for example, polycrystalline silicon. In this floating gate 5, an intermediate poly-drilling 6 and a control gate 7 are also arranged. For the erasure and programming of data, the so-called "Nordheim Fowler Tunnel" can be used in a gate cell (FN tunnels). ). In an erasing process, for example, OV is applied in drainage area 2 and +15 V in control gate 7. Then the electrons flow through the tunnels from the channel region through the tunnel oxide layer 4 to the floating gate 5. In programming, for example, there are OV in the control gate and + 15V in the drain zone 2, which causes the electrons to pass from the float gate 5 through the tunnel oxide layer 4. to the drainage area 2. But it is also possible, for example, to apply - 11 V in the control gate 7 and + 4 V in the drainage area 2. This also causes the electrons to pass from the float gate 5 to the drainage area through the tunnel. When programming with excited electrons (hot-e programming) they are applied in the control gate 7 for example = 15V, in the drainage area 2 + 5V and in the source zone 10 V. In this way they move electrons penetrate from the drain zone 2 to source zone 1 and simultaneously through the tunnel of tunnel oxide layer 4 to floating gate 5. An EEPROM is known to be programmed per byte and is erasable, while a flash memory is programmable by hot electrons or in the form of byte of tunnels FN and is erasable in block form by tunnels FN. Figure 4 shows as another type of memory cell, a so-called divided gate gate (Split-Gate), with a semiconductor substrate 3, a doped source zone 1 n2, a doped n 2 + drainage area, a layer of tunnel oxide 4, a floating gate 5, an intermediate polydielectric 6 and a control gate 7. The "recessed" part of the control gate 7 is also designated as a series gate 8, since the elevated control gate 7 and the series gate 8 can be considered as interconnected gates of two NMOS series connected transistors. The accumulation cell shown in Figure 3 is repeated by a symbol placed to the right of the Figure, where "CG" means the control gate 7, "D" the connection of the drain zone 2 and s "the connection of the source area 1. Memory cells of the type shown in Figure 3 can form a semiconductor memory with bit conduits BLO, BLI, BL2, BL3 and word passages LO, WL1, L2 and L3 as outlined schematically in the Figure 5. In a semiconductor memory array, selectively elevated voltages must be applied to selected word or bit conduits, to erase individual memory cells or to program, semiconductor memory arrays must also be switched to regulated voltages. especially with a high constancy as the supply voltage for high voltages of for example 15 V. An important application case is for example the control of bit channels in memories snapshots with negative programming voltage (compare here for example R. Heinrich, W. Heinrigs, G. Tempel, J. Winnerl, T. Zettler in Proc. of the International Electron Device Meeting (IEDM) 1993, pages 445 to 448). In order to achieve constant programming conditions, for example, the voltage of the bit channel at 5V is regulated, while the word pipes are set to -12V. Also such regulated voltages of for example 5V, which are below the supply voltage of 5.5 V, are then understood as "high voltages". For the generation of such control voltages, a connection or control connection is needed, which must provide the desired voltages with high constancy and low area requirement. In particular, a control connection "with a voltage distribution connection for the separate supply of the memory and memory field for redundancy positions with high voltages is described in US-A-5,293,561. This known control connection has especially a level transformer connection, which allows to establish an output value and an output value complementary to the previous one in a semiconductor memory array, but it has been presented, that the known connections of control of agreement with US-A- -5, 293, 561 are not well suited for bit-channel control, since they do not allow any intermediate storage of data.In addition, the known control connection contains NMOS transistors of the reducing type, which as parts Additional constructions require a considerable technological cost The connection according to EP 0 154 379 A2 contains, on the contrary, a large number of PMOS transistors, which require a relatively large area and low current productivity. SUMMARY OF THE INVENTION It is therefore the task of the present invention to create a control switching for a non-volatile semiconductor memory array, which is feasible with few constructive parts in a small area, so that it can be built over the space narrower in the socket or sear of the memory matrix of the semiconductor memory array, and the control voltages can be provided with high constancy also in the range of high voltages. To solve this task, a control connection of the aforementioned type is constructed in accordance with the characteristic features of claim 1. The input connection according to the invention consists of a source-drain section between the data input and a first transistor NMOS that is in a first data output and a serial connection of two second and third NMOS transistors that lie between masses and a second data output, where the gates of the second NMOS transistor are connected with the gates of the first NMOS transistor and the gates of the third NMOS transistor are connected to the source or drain of the first NMOS transistor. It should be expressly noted that such an input connection can also be established separately from the control connection, if with simple means a signal and an inverted signal have to be generated. The connection according to the invention can be realized with few constructive elements on a small surface, so that it can be placed in the narrowest space on the screen of the memory array of the semiconductor memory array. The input connection is built only of three NMOS transistors, so that it can be realized in a simple and favorably flat way, which for semiconductor memory arrays or their screens is of great importance. Since no PMOS transistor is used here, the input connection can be placed in a common housing, which means an additional advantage of surface gain. Due to the high current productivity of the NMOS transistors compared to the PMOS transistors, the particularly small connection can also be prepared. The block connection can advantageously consist of two inverters connected antiparallel. BRIEF DESCRIPTION OF THE DRAWINGS: The invention will be described in more detail below with reference to the drawings. Sample: Figure 1 a connection diagram of the control connection according to the invention; Figure 2 a CMOS transfer gate; Figure 3 a drawing of a cell - accumulation door; Fig. 4 a sectional drawing of a gate-divided cell; and Figure 5 a memory cell array with word pipes and bit conduits. DETAILED DESCRIPTION OF THE INVENTION Figure 1 shows the connection structure of a control connection according to the invention. This connection connection consists of a level 10 transformer connection, a latch switch 11 and an input connection 12. The level 10 transformer connection consists of PMOS transistors Pl, P2 and NMOS transistors N4, N5 and it has output connections D or DN, which are connected to the bit conduits or word pipes of a semiconductor memory array. The output conduits D or DN have an arrangement according to a sendo input value of "l" or "0", which remains in an input DATA, a voltage VPROG or 0 V. This is the complementary DN output connection to the output connection D and provides 0 V or a voltage VPROG, if in the output connection D there is a voltage V of VPROG or 0 V. In the source or drain of the PMOS Pl or P2 transistors there remains a voltage VPROG supplied from the outside of for example 15V. By means of the transistors N4, N5, pl and p2 the supply of this voltage VPROG is controlled for the connection of output D or DN where the output DN is complementary to output D, as has already been explained. A level transformer connection, which is similar to the level 10 transformer connection, is in itself known from the aforementioned US Pat. No. 5,293, 561. The transformer connection 10 is pre-connected to the connection. blocking 11, consisting of two inverters remaining between them anti-parallel II and 12. Before that blocking connection 11 there is an input connection 12 made of three NMOS transistors NI up to N3. The data to be stored, for example 5V for a data value "1", is routed through a DATA input of the input connection. Here is this source or drain of the transistor NI connected to the DATA input, which also applies to the gate of the transistor N3, which is connected to the transistor N2 in series. The gates of the transistors NI and N2 are joined together and connected to a LOAD connection. They remain in the LOAD connection for example 5V, then the transistors NI and N2 lead, so that OV remains in figure 1 at the left input of the blocking connection 11, while for example a data signal "1" of 5 V is conducted over the transistor NI to the right input of Figure 1 of the blocking connection 11 (decreased for the application voltage of the transistor NI). The control connection according to the invention is perfectly suitable for data, which must be programmed in a non-volatile semiconductor memory array. This data is stored intermediately in the blocking connection 11, and a regulated voltage VPROG is available for each bit channel. The control connection is provided in this separate application for each bit conduit or word conduit. The data to be programmed is put into the DATA input conduit. By means of a positive pulse in the LOAD connection the data is then transferred to the blocking position of the level transformation connection
then, depending on the input value "1" or "0" on the DATA input connection, the voltage VPROG or 0 V is available. The signal at the output connection D is here complementary to the signal at the output connection D and provides 0 V or a voltage VPROG, if the voltage at the output connection D has the value VPROG or OV. VPROG O 0. It is understood that the control connection according to the invention of a bit and / or word conduit can be applied for the general distribution of high voltages. The input connection 12 is structured only by three NMOS transistors NI, N2, and N3. It is with this easy to perform and with a thickness of favorable surface, which has a high significance for the switch of memory lock. Since there are no PMOS transistors this connection part can be generated in a common tank, which means a remarkable area advantage. The input connection 12 sets according to the input data of the blocking connection in the right node, according to FIG. 1 by means of the transistor N (in the input connection DATA there is "0") to 0 V or the left node by transistors N2 and N3 at 0 V. By means of the current production capacity of the NMOS transistors compared to the PMOS transistors the input connection 12 can be made especially small. In particular, the sum of the width of the transistors N2 and n3 must have a maximum width of a PMOS transistor with a CMOS transfer gate (compare Fig. 2) for the control of the input connection 12 only a LOAD signal will be needed . An additional inverted signal, as is necessary in a CMOS transfer gate, does not need to be used. The control connection according to the invention does not need any additional input inverter for the control of the transistors N4 and N5, but here for the function of the inverter II and 12 the blocking connection is used. The advantageous combination of the blocking connection 11 with the level 10 transformer connection thereby saves constructive elements and is therefore particularly suitable for application in memory screen switches where the surface is critical.