MXPA99010288A - Deviation scheme to minimize the output variation in phase comparing circuits and erro correction - Google Patents

Abstract

A phase comparison and error correction circuit, which uses one of a plurality of outputs from its phase detector as a deviation voltage for its error correction circuit

Description

DEVIATION SCHEME TO REDUCE THE VARIATION OF DEPARTURE AT THE MINIMUM IN THE CIRCUITS OF COMPARISON OF PHASE AND ERROR CORRECTION BACKGROUND OF THE INVENTION This invention relates to a phase comparison and error correction circuit, and more particularly, to a correction circuit which uses a deviation scheme to minimize the leakage current of the diode, and therefore the variation of the output control voltage. Referring to Figure 1, there is shown a phase comparison and error correction circuit 10 of the prior art. The circuit 10 comprises a logic phase detector coupled to an emitter (ECL) 12 and a correction circuit 14. The phase detector ECL 12, which is diverted between the connection to ground and -5.2 volts, receives two P i signals Ph2. Typically, the purpose of circuit 10 is to maintain alignment (synchronization) between P i and Ph2. However, depending on the different applications, such as frequency modulation, Phi and Ph2 may lose their synchronization. The ECL 12 phase detector is responsible for detecting whether Phi and Ph2 are out of phase, and if so which REF .: 31338 is at the head of the other. If Phi is at the head of Ph2, the phase detector ECL 12 sends a pulse on its error output 16 and if Ph2 is at the head of Phi, the phase detector ECL 12 sends a pulse on its error output 18. Finally, if the two signals Phi and Ph2 are synchronized with each other, the phase detector ECL 12 sends substantially equal pulses over the outputs 16 and 18. As shown in the output 16, the pulse sent by the phase detector ECL 12 is a negative pulse which has a transition of approximately -0.9 volts to approximately -1.7 volts and again -0.9 volts. The width of the error pulse depends on how far the Phi and Ph phases are from each other. Typically, the width of the error pulse is in the range of nanoseconds or picoseconds. The error pulse on the output 18 has the same characteristic voltage as the error pulse of the output 16, except that it is generated only when Ph2 is at the head of Phi- The correction circuit 14, which receives a pulse of error either from the output 16 or the output 18, generates a corresponding correction signal at the output node 20 to be used to align the signals Phi and Ph2. The outputs 16 and 18 are connected to the nodes 22 and 24 of the correction circuit 14 respectively. The nodes 22 and 24 are connected to -5.2 volts through the resistors Rn and R? 2 respectively. The output of Op-amp 26, the correction signal, is connected to the output node 20. The inverted (-) input of Op-amp 26 is connected to the anode of a diode Dn and the cathode of diode Du is connected to the node 22 through resistance R13. The non-inverted (+) input of the Op-amp 26 is connected to the anode of a diode D12 and the cathode of the diode D ?2 is connected to the node 24 through the resistor R14. The inverted input of Op-amp 26 is also connected to anode 20 through a capacitor Cu and the non-inverted input of Op-amp 26 is connected to ground through capacitor Ci2. In operation, nodes 22 and 24 are maintained near -0.9 volts through outputs 16 and 18, respectively, unless they receive an error pulse. In the absence of an error pulse, the inverted and non-inverted inputs of Op-amp 26 are substantially at the same voltage. An error pulse on the output 16 causes the voltage of the node 22 to drop to approximately -1.7 volts. The voltage of node 22 falls and produces a forward deflection through Dn. This pulls the capacitor Cu current through resistors R13 and Ru, which causes the Cu capacitor to discharge. When capacitor Cu starts to discharge, the inverted input voltage of Op-amp 26 drops. However, the non-inverted input voltage of Op-amp 26 remains constant. The lowest voltage over the inverted input compared to the non-inverted input voltage of the Op-amp 26, causes the output voltage of Op-amp 26 to increase. Therefore, when Phi is at the head of Ph2, the voltage of the correction signal increases. Once the error impulse ends, the voltage of node 22 returns to approximately -0.9 volts and Cu will stop being discharged. This causes the value of the correction signal to remain at its new level. Typically, if correction is not required, the normal level of the correction signal depends on the system in which the correction circuit is used. A similar phenomenon is expected when the output 18 sends an error pulse to the correction circuit 14. This will produce a forward deflection through the diode Di2 and pull current through R? 4 and R12, which results in the discharge of capacitor C12. Once the capacitor C? 2 begins to discharge, the voltage of the non-inverted input of the Op-amp drops while the non-inverted voltage remains constant. This produces a voltage difference between the two inputs of the Op-amp 26, which results in a decrease in the correction signal. Therefore, if Ph2 is at the head of Phi, the voltage of the correction signal will decrease. The amount by which the voltage of the correction signal decreases depends on the width of the error pulse. When the error pulse ends, the voltage of the node 24 returns to approximately -0.9 volts and the diode D12 returns to an absence of deviation, which stops the discharge of the capacitor Ci2. As a result, the voltage of the correction signal remains at its new level. In the absence of an error pulse, if the diodes Du and D12 have any leakage current, they will cause the capacitors Cu and C? 2 to discharge slightly or discharge respectively. Such a leakage current will cause the voltage at the inputs of Op-amp 26 to change and therefore change the output voltage (correction signal). This is an undesirable effect which can cause an undesirable change of phase between P i and Ph2. It should be noted that the leakage current is usually not sufficient to change the voltages at nodes 22 and 24. However, the load / discharge of either the capacitor Cu or the capacitor Ci2 is sufficient to create a voltage difference at the inputs of the Op-amp 26 and the change of the correction signal. This phenomenon is magnified as temperature increases since the leakage current of the diodes increases exponentially as the temperature rises. In Figure 1, the reference voltage VREF (deviation voltage) is connected to the inverted and non-inverted inputs of the Op-amp 26 through the resistors R14 and R15, respectively. The VREF is a regulated, temperature-stable voltage of -0.9 volts, which was selected to match the voltages of outputs 16 and 18. The purpose of using a VREF offset voltage is to keep the input voltage inverted and not inverted from Op-amp 26 to a level that minimizes the leakage current of diodes Dn and D? 2. This in turn causes the output voltage of Op-amp 26 to remain at a fixed level regardless of the leakage current unless an error pulse is generated. This type of deviation is not effective. The problem arises due to the different tolerance ranges of the different outputs of the ECL phase detector 26. Each output of the ECL phase detector 26 has a different tolerance range and each tolerance range changes as the temperature changes. Typically, a VREF offset voltage is selected that must be half the tolerance intervals to equal the voltages at outputs 16 and 18. However, when the temperature changes, the tolerance intervals change, but the offset voltage It is insensitive to the temperature remains constant. Therefore, when the temperature changes, the deflection voltage VREF tries to be equal to the voltages in the ECL outputs 16 and 18. A voltage difference between the deflection voltage VREF and the outputs of the ECL 16 and 18 causes the leakage currents to change the input voltages of the Op-amp 26. An object of this invention is to provide a deflection scheme to minimize the undesirable effects of the leakage current of the diode on a phase comparison and error correction circuit and to provide a substantially fixed correction signal in the absence of an error pulse.

BRIEF DESCRIPTION OF THE INVENTION According to the present invention, there is described a phase comparison and error correction circuit, comprising phase detection means and a correction circuit. The phase detection means have a plurality of outputs. One of the plurality of outputs of the phase detector is used as a deviation output and is connected to the correction circuit to provide deviation to the correction circuit.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a conventional phase comparison and error correction circuit; and Figure 2 shows a phase comparison and error correction circuit of this invention.

DESCRIPTION OF THE PREFERRED MODALITY Referring to Figure 2, there is shown a phase comparison and error correction circuit 30 of this invention. The circuit 30 comprises a well-known ECL phase detector 32 and a correction circuit 34. The phase detector ECL 32, which is diverted between the ground connection and -5.2 volts, receives two signals Pi and P2. The phase detector ECL 32 is responsible for detecting whether Pi and P2 are out of phase, and if so, which is at the head of the other. If Pi is at the head of P2, the phase detector ECL 32 sends a pulse on its error output 36 and if P2 is at the head of Pl the phase detector ECL 32 sends a pulse on its error output 38. Finally, if the two signals Pi and P2 are synchronized with each other, the phase detector ECL 32 sends substantially equal pulses over the outputs 36 and 38. The correction circuit 34, which receives an error pulse either on the output of error 36 or the error output 38 of the phase detector 32, is responsible for generating a correction signal at the output node 40 to be used to align the signals Pi and P2. The outputs 36 and 38 are connected to the nodes 42 and 44 of the correction circuit 34, respectively. The nodes 42 and 44 are connected to -5.2 volts through the resistors Ri and R2, respectively. The output of the Op-amp 46, which generates the correction signal, is connected to the output node 40. The inverted (-) input of the Op-amp 46 is connected to the anode of a diode Di and the cathode of the diode Di is connected to node 42 through resistor R3. The non-inverted (+) input of Op-amp 46 is connected to the node of a diode D2 and the cathode of diode D2 is connected to node 44 via resistor R4. The inverted input of Op-amp 46 is also connected to node 40 through a capacitor Ci and the non-inverted input of Op-amp 46 is connected to ground through capacitor C2. Typically, an ECL phase detector has multiple outputs and they usually have the same characteristics and follow the general changes within the ECL circuit. For example, if the temperature rises, the voltages of all the outputs change in the same degree. Therefore, if extra ECL outputs are used as a deviation output, then the deviation voltage will follow the voltage changes of the outputs that generate the error pulses. In the described embodiment of this invention, the output 48 of the ECL phase detector 32 is dedicated to be a bypass output. Within the ECL 32 phase detector, output 48 is a constant high ECL (HI) output. Externally, the output 48 is connected to the node 50 of the correction circuit 34 through the resistor R5. Output 48 is also connected to -5.2 volts through resistor R6. The node 50 is connected to ground through the capacitor C3. The inverted input of Op-amp 46 is connected to node 50 through resistor R7 and the non-inverted input of Op-amp 46 is connected to node 50 via resistor R8. Resistors R7 and Rs have the same size. The resistor Re is identical to the resistors Ri and R2 to create the same load and characteristics on the output 48 as those of the outputs 36 and 38. R5 and C3 also create an RC circuit to filter out any noise that may possibly be coupled to the output 48. In operation, in the absence of an error pulse, when the temperature changes, the deviation voltage at output 48 substantially follows and equals the voltage changes of outputs 16 and 18. This keeps the two inputs of Op-amp 46 at a voltage which avoids the leakage current in diodes Di and D2. Therefore, the two outputs of Op-amp 46 remain constant and substantially minimize the undesirable variation of the correction signal due to diode leakage currents. It should also be noted that numerous changes can be made in the details of construction and the combination and arrangement of the elements without departing from the true spirit and scope of the invention claimed hereinbefore.

It is noted that in relation to this date, the best method known by the applicant to carry out the aforementioned invention, is the conventional one for the manufacture of the objects to which it relates.

Claims (2)

CLAIMS Having described the invention as above, the content of the following claims is claimed as property:

1. A phase comparison and error correction circuit, characterized in that it comprises: phase detection means for receiving a first signal with a first phase and a second signal with a second phase; the phase detection means have a plurality of outputs of which at least two are error outputs; phase detection means comparing the first phase and the second phase and generating a first error in one of at least two error outputs if the first phase is at the head of the second phase or generates a second error on the other of the two error outputs if the second phase is at the head of the first phase; correction means that are electrically connected to at least two error outputs of the detection means for receiving the first error or the second error and generating a correction signal; one of the plurality of outputs of the phase detecting means is a bypass output; and the bypass output is electrically connected to the comparison means to provide a bypass voltage.

2. The phase comparison and error correction circuit according to claim 1, characterized in that the phase detection means is an ECL device.