MXPA99010210A - Architecture of electric arc detection based on correlation for circu circuit breakers - Google Patents

Abstract

A specific integrated circuit of mixed digital analog signal (ASIC) application includes a central processing unit (CPU) programmed to execute a correlation function for electric arc detection. The use of a standard central processing unit is possible because the need for digital fourier analysis is eliminated by the structure of the mixed signal application-specific integrated circuit. The specific integrated circuit of mixed signal application includes a power supply configured to be coupled to a power line to supply power to the components of the specific integrated circuit of mixed signal application and additionally includes a current detector coupled to a conductor of current to generate a signal representative of current in the conductor. A first analog-to-digital converter (ADC) coupled to the current detector, has its output coupled to a central processing unit (CPU). The central processing unit provides a digital-to-analog converter (DAC) with a digital signal representative of a portion of the detected current. The digital-to-analog converter provides this signal, in analog form, to an adder, which also receives an output signal from the current detector. The summed analog output signal of the adder is converted to digital form by a second analog-to-digital converter and is provided to the central processing unit. The output of the central processing unit is coupled to a trigger, fe, a trigger of a circuit breaker

Description

ELECTRIC ARC DETECTION ARCHITECTURE BASED ON CORRELATION FOR CIRCUIT CIRCUIT BREAKERS FIELD OF THE INVENTION This invention relates generally to circuit breakers and, more particularly, to detection in residential type circuit breakers. BACKGROUND OF THE INVENTION Although electric arc detection is desirable to reduce the possibility of a fire that is initiated by an electric arc and to protect building wiring and consumer wiring, such as extension cords and cables of electronic devices , as well as the electronic devices themselves, the commonly known residential-type circuit breakers do not include an electric arc detection unit. Electrical arcs can generally be identified by the high frequency content of current in a branch circuit. The high frequency current, that is, the current having a frequency that exceeds the range of 1 KHz to 10 MHz, can be introduced into the branch circuit through a benign apparatus such as universal motors in hair dryers, drills and vacuum cleaners Said motors can produce significant high frequency due to the production of the electric arc of the brush motor commutation. Silicon controlled rectifier lamp controllers and advanced electronic devices can also generate high frequency energy. Discriminating between real electric arc faults and benign high frequency energy sources is therefore more difficult than simply detecting a high frequency. However, a residential electric arc detection unit must have a low interference disconnect speed, that is, low false alarm rate. The known electric arc detection units that have the necessary false alarm rate are therefore complex and expensive. To reduce the costs of electric arc detection units, some known circuit breakers include central processing units that execute algorithms to eliminate possible sources of noise, such as tools and household appliances (e.g., motors, welders, switches). Such known algorithms include Fourier analysis and other frequency domain-based approaches. The noise sources are removed from the primary signal by sorting the resulting noise from said sources, and then using said classified signals to identify noise signals and sources in the primary signal. Then, the noise signals are subtracted from the primary signal so that the noise portion of the signal is eliminated. The functional requirements for digital signal processing based on the elimination of noise sources requires the correct classification of noise signals followed by data storage, i.e. storage of the portion of the primary signal associated with the noise signal. The processing power necessary to provide this function is high and increases linearly with the number of noise sources present as well as with respect to the square of the frequency range resulting from the requirements of the Fourier Transform. It would be desirable to provide protection for a residence from electric arc-type faults, including location and fault isolation. It would also be desirable to provide such protection at a reduced cost compared to the expenses associated with the use of sophisticated arc detection units. BRIEF DESCRIPTION OF THE INVENTION A device for detecting electric arcs of a signal provided by a current detector includes a specific analog mixed digital application integrated circuit (ASIC) that employs a central processing unit (CPU) with a reduced processing load. digital signal (DSP) and programmed to execute a correlation function for electric arc detection. The use of a standard central processing unit is possible because the overload of digital signal processing necessary for Fourier analysis is eliminated by the mixed analogue digital application specific integrated circuit architecture. Additionally, by enabling the use of a standard central processing unit, the manufacturing cost of the mixed analog digital application specific integrated circuit can be substantially less than the manufacturing cost associated with known electric arc detection units. In an exemplary embodiment, the mixed analogue digital application specific integrated circuit includes a power supply configured to be coupled to an AC power line to supply power to the components of the mixed analogue digital application specific integrated circuit. Additionally, the mixed analogue digital application specific integrated circuit includes a current detector coupled to a current conductor of, for example, a circuit breaker. The current detector is placed adjacent to the current path of the switch so that the sensor generates a signal representative of current in the conductor. The mixed analogue digital application specific integrated circuit additionally includes a first analog to digital converter (ADC) coupled in series with the current detector. The first analog-to-digital converter has its output coupled to a central processing unit (CPU). The central processing unit may, for example, be a central processing unit for general purposes, which is well known in the art. The central processing unit may use the output signals of the first analog-to-digital converter to implement overcurrent interruption algorithms, which are also well known in the art. The central processing unit includes an output coupled to a digital-to-analog converter (DAC) and the central processing unit supplies the digital-to-analog converter with a digital signal representative of a portion of the detected current. The digital-to-analog converter is coupled to an adder, which is also coupled to an output of the current detector. The adder output is coupled to a second analog to digital converter (ADC) and the output signal of the second analog to digital converter is supplied as an input signal to the central processing unit. An output of the central processing unit is coupled to a trigger or actuator, for example a trigger of a circuit breaker. In operation, the current detector produces an analog signal representative of current in the circuit breaker conductor. The analog signal is converted to a digital signal by the first analog-to-digital converter, and the digital signal produced by the first analog-to-digital converter is supplied to the central processing unit. The central processing unit processes the received digital signal and filters the received digital signal to remove, for example, the noise portion of the digital signal. The filtering function can be achieved by standard digital signal processing techniques. Then, the central processing unit provides the digital-to-analog converter with a digital signal substantially free of noise, for example a 50 Hz or 60 Hz signal substantially free of noise. The digital-to-analog converter converts the noise-free digital signal to an analog signal, and the substantially noise-free analog signal is provided to the adder. The adder subtracts the substantially noise-free analog signal from the analog signal provided by the current detector so that the 50 Hz or 60 Hz signal component is removed therefrom. Subtraction of the 50 Hz or 60 Hz signal component from the detector output signal provides an improvement in differential sensitivity. The signal produced by the adder is provided to the second analog-to-digital converter which converts the output signal of the adder into a digital signal, which is supplied to the central processing unit. The output signal of the second analog-to-digital converter substantially contains the noise generated by the electric arc with the 50 Hz or 60 Hz signal component removed for post-sensitivity processing. The central processing unit executes a correlation function using the digital signal received from the second analog-to-digital converter. A correlation function that can be used in the central processing unit is a sliding windows function that simulates real-time fourier frequency analysis, thus eliminating the need for digital fourier analysis and therefore reducing the processing power of the required central processing unit and the expenses associated with it. Although the identification of the electric arc includes the frequency range of 1 KHz to 10 KHz, the detection can be limited to several hundred Hz, such as 300 Hz, or up to several tens of KHZ, such as 20 KHz, according to the processing speed available for simple central processing units. As higher processing speeds are available at substantially the same cost with the advance of semiconductor circuits, the range covered by the corrector can be extended. The exact selection between the frequency range for the corrector and the number of shots can be related to the accuracy of the detection. By limiting the frequency range from 300 Hz to 20 KHz, contributions from stray noise sources such as radio transmission, switchable power supplies and rectifiers are substantially eliminated and the electric arc energy in this frequency range is detected from predominant way. To further improve the accuracy of the detection, a 50 Hz or 60 Hz half-cycle overlay identification frequency can be used, thus distinguishing the arc from the identification of parasitic electric arcs, such as those generated by motor brushes operating at different frequencies. The correlation algorithms employed by the invention are based on detection, not elimination of noise sources. To perform the type of correlation function, one possibility is to provide the calculation of a series of band-pass filters and perform them in multiples or fractional multiples of the fundamental frequency (ie, 50 or 60 Hz). The filtered signals are then used to determine the energy associated with the noise or electric arc signal in the bandwidth of interest. An alternative is to provide substantial filtering of harmonic rejection of the d igitalized signal before performing the correlation type of signal processing. Another approach is to set the fundamental input signal in phase, and then take lower samples so that all the harmonics of the fundamental frequency (50 or 60 Hz) are in themselves or within controlled bandwidths. This reduces the extension of samples and reduces filtering to a few bands of interest and also reduces the complexity of filtering the fundamental signal and its harmonics. Alternatively, a phase fixation approach can be approximated by tracking the fundamental frequency and using it to take subsamples by an adjustable amount. This approach limits the fundamental frequency and its harmonic components so that they are placed close to them within an imitated bandwidth. If the fundamental frequency changes beyond a set range, the range that was resampled is adjusted to return the fundamental frequency and its harmonics to the desired bandwidth. In the drawings, the similar reference numbers indicate similar components. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of an integrated circuit architecture specific to mixed signal application in accordance with one embodiment of the present invention. Figure 2, is a block diagram of an integrated circuit architecture specific to mixed signal application in accordance with another embodiment of the present invention. Figure 3 is a block diagram of an integrated circuit architecture specific to mixed signal application in accordance with another additional embodiment of the present invention. Figure 4 is a block diagram of an apparatus that can be used between the output of adder 28 and the input to the central processing unit in each of Figures 1, 2, and 3, to more completely cancel the frequency fundamental and its harmonics while retaining the indications of noise spectra of the electric arc. DETAILED DESCRIPTION An integrated signal application-mixed signal (ASIC) architecture in accordance with one embodiment of the present invention is described in detail below. Although the specific mixed specific signal application integrated circuit is sometimes described herein for use in residential applications, it should be understood that said specific mixed signal application integrated circuit can be used in other applications than residential applications. In addition, the specific mixed signal application integrated circuit may be incorporated into known circuit breakers or may be implemented separately from said circuit breakers, and is not limited to any particular type of circuit breaker. Figure 1 illustrates an exemplary embodiment of a specific integrated circuit of mixed signal application 1 0 constructed in accordance with a preferred embodiment of the invention, and includes its energy minister 1 2 coupled to a line of AC power (not shown) either directly or via current transformers. The power supply 12 may conveniently comprise a regulating power supply in parallel. The specific integrated circuit of mixed signal application 1 0 additionally includes a current detector 14 coupled to a current conductor 16 of, for example a circuit breaker. The current detector 14 is positioned adjacent to the current path of the switch so that the current detector 14 can generate a signal representative of current in the conductor 16. The current detector 14 can comprise a current transformer or a transducer current to voltage, both known in the art. The current detector 14 may be separate from the specific mixed signal application integrated circuit 10 or be integral to the mixed signal application specific integrated circuit 10 as illustrated in Figure 1. Additionally, the mixed signal application specific integrated circuit 10 includes a first analog-to-digital converter (ADC) 18 coupled in series with the current detector 14. The analog-to-digital converter 18 has its output coupled to a processing unit. center (CPU) 20. The central processing unit 20 includes a read-only memory (ROM) 22 and a random access memory (RAM) 24 which are used in the detection of electric arcs. The central processing unit 20 may, for example, be a general purpose type 8051 microprocessor, which is well known in the art. The central processing unit 20 includes an output coupled to a digital-to-analog converter (DAC) 26. The central processing unit 20 supplies the digital-to-analog converter 26 with an analog signal representative of a portion of the detected current of the converter. analog to digital 18. The digital-to-analog converter 26 is coupled to an adder 28, which is also coupled to a second analog-to-digital converter 30, whose output is coupled to the central processing unit 20. One output of the central processing unit is coupled to a trigger, for example, the trigger 32 of a circuit breaker. A port of the central processing unit 20 may be coupled to a communications circuit 34 for receiving external communications, for example, commands and externally generated data. The communication function of the mixed signal application-specific integrated circuit 10 can provide bidirectional data transfer. In operation, the current detector 14 supplies an analog signal representative of current in the conductor of the circuit breaker 16. The analog signal is converted to a digital signal by the analog-to-digital converter 18, and the digital signal produced by the converter from analog to digital 18 is supplied to the central processing unit 20. The central processing unit 20 processes the received digital signal and filters the received digital signal to remove, for example, the noise portion of the digital signal. Then, the central processing unit 20 supplies the digital-to-analog converter 26 with a digital signal substantially free of noise, for example, a 60 Hz or 50 Hz signal substantially free of noise. The digital-to-analog converter 26 converts the substantially noise-free signal to an analog signal substantially free of noise that is supplied to the adder 28. The adder 28 subtracts the substantially noise-free analog signal from the analog signal supplied by the current detector 14, removing the signal component of 60 Hz or 50 Hz from the signal supplied by the current detector. The subtraction of the 50 Hz or 60 Hz signal component from the detector output signal is sometimes referred to as differential sensitivity improvement. Specifically, after subtracting the component of the 50 Hz or 60 Hz signal, only the electric arc and signal noise components remain. This signal, therefore, is sensitive to changes in at least the electric arc characteristic in the signal supplied by the detector 14. Then, the analog-to-digital converter 30 converts the output signal of the adder 28 to a digital signal which is supplied to the central processing unit 20. The central processing unit 20 performs a correlation function using the digital signal received from the analog-to-digital converter 30. Alternatively, the correlation function can be implemented in a low correlation unit. the control of the central processing unit 20. A correlation function that can be used in any mode is the sliding window function that simulates real-time fourier frequency analysis, thus eliminating the need for digital fourier analysis and therefore reducing the energy. processing of the required central processing unit and the expenses associated with it. To perform the type of correlation function, a series of bandpass type filters can be used in multiples or fractional multiples of the fundamental frequency (ie, 50 Hz or 60 Hz). The filtered signals are then used to determine the energy associated with the electric arc signal or noise in the bandwidth of interest. Additionally, harmonic rejection filtering of the digitized signal can be performed before performing the correlation type of the signal processing. The processing can be described as: y (j) = (i = 0: m- 1) V (ji) xK (¡) where i = 0: mi for a filter calculation of point m, and (j) = filtered output, V (i) = input signal, and K (i) = correlation filter core. The filter may include a pre-processing of the data to remove the harmonic components if desired. If it is not desirable to expend sufficient digital signal processing power to completely remove the entire 50 Hz or 60 Hz signal via the digital-to-analog converter 26, or if the feedback signal generated by the digital-to-analog converter 26 differs in phase or amplitude with the ideal feedback signal, a portion of the predominant signal of 50 Hz or 60 Hz will remain in the signal digitized by the analog-to-digital converter 30. Additional processing to completely remove the residual frequency of 50 Hz or 60 Hz can be performed with standard processing techniques of digital signal, however, these techniques can have a very intense processing. Another approach is to set the phase of the fundamental input signal and then take sub-samples of the signal so that all the harmonics of the fundamental frequency (ie, 50 Hz or 60 Hz) are within them or within widths of controlled bands. This reduces sample rates and reduces filtering to a few bands of interest, thus reducing the complexity of filtering the fundamental frequency and the associated harmonic signals. Thus, as shown in FIG. 4, a phase locked circuit (PLL) 300 in the embodiment shown in FIG. 4 synchronizes the sampling rate of the analog-to-digital converter 30 to a multiple of the line frequency. fundamental, that is, a multiple mf0 of 50 Hz or 60 Hz, where m is commonly a whole number or a relation and f0 is the dominant fundamental line frequency, nominally 50 Hz or 60 Hz. A simple decimal formator (301 ) resamples the data stream from the highest value mf0 to a lower value mf0 / n where n is the sample value reduction factor. All the signal components of the fundamental frequency f0 and their harmonics are sampled or doubled at lower frequencies, which are filtered more efficiently. As an example, if fo = 60 Hz and m = 100, then the sampling frequency fsampling = mf? ~ 6 KH z. When using factors of n = 100, a transformation filter x - \ H { z) = and exhibiting a delay of 1-z "1 can be used as cancellations of filter 302 to completely cancel out the fundamental frequency and all harmonics while preserving the noise spectrum indicative of the electric arc. Similarly, when using factors of n = 50, a transformation filter ff (*) = -ry and exhibit a delay of 1 -z "1 can be used as cancellations of the filter 302 to completely cancel the fundamental frequency and all the harmonics while preserving the noise spectrum indicative of the electric arc, using n-factors = 25, a transformation filter H (z) = ^ 'Z and exhibit a delay of 1 -z "1 can be used as cancellations of the filter 302 for this purpose, thus, blocking in phase the fundamental frequency using a higher original sampling value as well as a The second sample shows a much smaller sample, the fundamental frequency and all the harmonic components will be reduced to 0 Hz and can be filtered with a direct current removal filter.This leaves a non-fundamental frequency signal resistance in the passband Additionally, if pre-filters are used before resampling occurs, different frequency bands can be attenuated before performing the filtering / resampling process.An alternative to using a phase-locked approach would be to approximate an in-phase blocking approach. tracking the fundamental frequency and sub-sampling the signal by an adjustable amount.This approach limits the fundamental and harmonic components to bring them closer together within an anchor limited band ho. If the fundamental frequency changes beyond a set range, the resampled value is adjusted to return the fundamental and harmonic components to the desired bandwidth.

Many other alternatives to the embodiment illustrated in Figure 1 are contemplated and are possible. For example, the digital-to-analog converter 26 can be replaced by a phase-locked circuit (PLL) under the control of the central processing unit that generates the 50 Hz or 60 Hz signal and supplies it to the adder 28, releasing thus to the central processing unit 20 to implement the filtering function. In another alternative embodiment, the digital-to-analog converter 26 is replaced by a direct digital synthesizer (DDS) circuit under the control of the central processing unit that generates the 50 Hz or 60 Hz signal without requg the processing unit central 20 perform no filtering. The output of the direct digital synthesizer is provided directly to the adder 28. Figure 2 illustrates another additional embodiment of the mixed signal application specific integrated circuit 100, which includes a retention and sampling circuit 102 coupled to the output of the current detector 14, and a delay unit 104 coupled to the output of the sampling and holding circuit 102. The sampling and retention circuit 102 and the delay unit 104 provide a sample of the output signal of the current detector 14 to the adder 28 and compensate for any delay resulting from the processing of the central processing unit 20 and the digital-to-analog converter 26. Of course, the units 102 and 104 can be used in combination with the circuits using a phase-locked circuit or the direct digital synthesizer in place of the digital-to-analog converter 26. Figure 3 illustrates another additional embodiment 200 of an integrated circuit specific application of mixed signal, which includes a filter of 50 Hz or 60 Hz 202. The signal of the current detector 14 is provided to the adder 28 and the filter 202. In this embodiment, the central processing unit 20 does not have to perform the filtering function and the digital-to-analog converter 26 is eliminated, allowing the filter 202 to perform the function of providing a substantially noise-free signal of 50 Hz or 60 Hz to the adder 28. Those skilled in the art will recognize that the apparatus shown in Figure 4 can be used to completely remove the complete residual fundamental frequency of 50 Hz or 60 Hz in the modes shown in Figures 2 and 3 in the same manner as described in conjunction with Figure 1. Although only certain preferred aspects of the invention have been described and illustrated., many modifications and changes will occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all these modifications and changes that are within the true spirit of the invention.

Claims (25)

1. CLAIMS 1. Apparatus for detecting electric arcs of a signal provided by a current detector for detecting current in an AC power line, said apparatus comprising: a central processing unit coupled to the current detector for receiving a signal representative of current detected by the current detector; and an adder having a first input coupled to the current detector, a second input coupled to an output of said central processing unit, and an output coupled to an input of said central processing unit. Apparatus according to claim 1, further comprising a first analog-to-digital converter coupled between the current detector and said central processing unit for converting an analog signal produced by the current detector into a digital signal representative of current detected by the current detector. 3. Apparatus according to claim 1, further comprising a digital-to-analog converter coupled between said central processing unit and said adder to provide an analog signal to the second adder input. Apparatus according to claim 2, further comprising a second analog-to-digital converter coupled between said adder and said central processing unit for providing a digital signal to such a central processing unit converted from an analog output signal produced by the aforementioned adder. Apparatus according to claim 1, wherein said central processing unit comprises a random access memory and a read-only memory. Apparatus according to claim 1, wherein said central processing unit comprises a general purpose microprocessor. Apparatus according to claim 1, further comprising a circuit breaker trigger coupled to an output of said central processing unit. 8. Apparatus according to claim 1, further comprising a communication line, said central processing unit is coupled to said communication line for bidirectional data transfer. 9. Apparatus according to claim 1, further comprising a phase locked circuit coupled between said central processing unit and said adder. 10. Apparatus according to claim 1, further comprising a direct digital synthesizer coupled between said central processing unit and said adder. Apparatus according to claim 2, further comprising a second analog to digital converter coupled to the output of said adder, a decimal former coupled to the output of said second analog to digital converter, a filter of anulation coupled to the output of said decimal former, and a phase locked circuit which couples the output of said second analog to digital converter to a sample value control input of such an analog-to-digital converter for synchronizing the value at which said second analog-to-digital converter samples the alternating current energy in said energy line. 12. Apparatus for detecting electric arcs in an AC power line comprising: a current detector; a central processing unit coupled to receive a signal representative of current detected by said current detector; an adder having a first input coupled to such a current detector, and an output coupled to an input of such a central processing unit; and a first analog-to-digital converter coupled between said current detector and said central processing unit for converting an analog signal produced by said current detector to a digital signal representative of current detected by said current detector. 13. Apparatus according to claim 12, wherein said current detector comprises a current transformer. 14. Apparatus according to claim 12, wherein said current detector comprises a current-to-voltage transducer. 15. Apparatus according to claim 12, further comprising a second analog-to-digital converter coupled between said adder and said central processing unit for providing a digital signal to such a central processing unit, and a digital-to-analog converter coupled between such a central processing unit and said adder to supply an analog signal to a second input of such adder. Apparatus according to claim 12, wherein said central processing unit comprises a random access memory and a read-only memory. 17. Apparatus according to claim 12, wherein said central processing unit is programmed to execute a correlation function. 18. Apparatus according to claim 12, further comprising a circuit breaker trigger coupled to an output of said central processing unit. 19. Apparatus according to claim 12, further comprising a communication line, said central processing unit is coupled to said communication line for bidirectional data transfer. 20. Apparatus according to claim 2, further comprising a second analog adjoint converter coupled to the output of said adder, a decimal former coupled to the output of said second analog to digital converter, an override filter coupled to the output of said decimal former, and a phase locked circuit that couples the output of said second analog to digital converter to a sample value control input of said analog to digital converter to synchronize the value at which said Second Analog to Digital Converter samples the AC power in the aforementioned power line. twenty-one . Apparatus for detecting electric arcs of a signal produced by a current detector to detect current in an AC power line, said apparatus comprises: a central processing unit coupled to the current detector to receive a signal, including a fundamental signal, representative of current detected by the current detector; and an adder having a first input coupled to the current detector, and an output coupled to an input of said central processing unit, said adder is configured to subtract the fundamental signal from the current detector signal. 22. Apparatus according to claim 21 further comprising a retaining and sampling circuit coupled between the current detector and said adder. 23. Apparatus according to claim 21 further comprising a filter coupled between the current detector and a second input of said adder. 24. Apparatus according to claim 21 further comprising a delay unit coupled between the holding and sampling circuit and said adder. 25. Apparatus according to claim 2, further comprising a second analog-to-digital converter coupled to the output of said adder, a decimal former coupled to the output of said second analog-to-digital converter, an attached bypass filter. at the output of said decimal former, and a phase blocking circuit that couples the output of said second analog to digital converter to a sample value control input of said second analog to digital converter to synchronize the value at said second analog-to-digital converter samples the alternating current energy in said energy line. RESU MEN A specific integrated circuit of low cost analog digital signal (ASIC) application includes a central processing unit (CPU) programmed to execute a correlation function for electric arc detection. The use of a standard central processing unit is possible because the need for digital fourier analysis is eliminated by the structure of the mixed signal application-specific integrated circuit. The specific integrated circuit of mixed signal application includes a power supply configured to be coupled to a power line to supply power to the components of the specific integrated circuit of mixed signal application and additionally includes a current detector coupled to a conductor of current to generate a signal representative of current in the conductor. A first analog-to-digital converter (ADC) coupled in series with the current detector has its output coupled to a central processing unit (CPU). The central processing unit provides a digital-to-analog converter (DAC) with a digital signal representative of a portion of the detected current. The digital-to-analog converter provides this signal, in analog form, to an adder, which also receives an output signal from the current detector. The summed analog output signal of the adder is converted to digital form by a second analog-to-digital converter and is provided to the central processing unit. The output of the central processing unit is coupled to a trigger, fe, a trigger of a circuit breaker.