MXPA99009784A - Sharing resources in a digital filter - Google Patents

Abstract

A digital filter (1) has a filter cell (4a) for generating processed data. The digital filter cell includes plurality of coefficient registers (14) which are arranged to circulate a plurality of coefficient values that correspond to a plurality of coefficients such that each of the plurality of coefficients is output once during a predetermined period. One or more data registers (11) are arranged to circulate a data value for a time which is at least as long as the predetermined period such that the data value is output each time that a different one of the plurality of coefficients is output. A circuit (12) receives each output data value and each output coefficient and generates processed data by processing each output data value with each output coefficient.

Description

RESOURCES SHARED IN A DIGITAL FILTER BACKGROUND OF THE INVENTION Field of the Invention The present invention is directed to resources shared in a digital filter. In particular, the invention is directed to a digital filter comprised of cells, which process a plurality of data values and filtering coefficients using the same circuit.

Description of the Related Art Conventional digital filters, such as finite impulse response filters (hereinafter "FIR"), are comprised of a plurality of filtering cells, or "bypass" cells arranged in series. Each filtering cell includes a data logger for storing a data value product of a sampling and a coefficient recorder, which stores a coefficient for that particular cell. In operation, the same data value product of the sampling is fed sequentially to each filtering cell, and is multiplied by a coefficient for that cell. The results of those multiplications are then produced and combined to generate the filter output.

The different types of filter outputs require a different number of filter cells. For example, only two filter cells may be required to simulate the effect of a simple low pass filter. Additional filtering cells may be required, however, to carry out more complex filtration. In this regard, generally speaking, as the complexity of the filter function increases, the number of cells in the filter increases, thus leading to an increase in the filter size. This can be problematic, particularly in cases where a large number of filtering cells are required, but where there is a limited amount of available space. There are different ways to decrease the size of a filter without reducing its effectiveness. For example, it is possible to remove the multiplication circuits of the filter, as described, for example, in U.S. Patent No. 4,862,402 (Shan et al.). One way to decrease the size of the filter, without removing the multiplication circuits, is known as sharing resources. The way to share conventional resources involves using the same multiplication circuit to multiply different data values by different coefficients. Since the multiplication circuit is typically the largest component of a digital filter, reducing the number of multiplication circuits in the filter by sharing resources reduces the size of the filter significantly without reducing its capabilities. The advantages of this reduction in size, however, are mitigated by the way in which the way of sharing resources in a conventional manner reduces the number of multiplication circuits. More specifically, in the way of sharing resources in a conventional manner, two multiplexers are used to control which data values and which coefficients are transmitted to the multiplication circuit. These multiplexers introduce a propagation delay in the filter cell, which reduces the maximum clock frequency at which the filter can operate. In addition, the multiplexers consume additional space, thus reducing the space savings achieved by the reduction in the number of multiplication circuits. In addition to the above deficiencies, the way of sharing resources in a conventional manner does not adequately solve the specific problems of adaptive digital filters. In this regard, an adaptive digital filter includes an adaptation circuit in each branch cell, which is designed to update each of the coefficients of the branch cell, based on a variety of factors, such as the characteristics of the cell. channel, etc., that could affect the transmission of data. Although the adaptation circuit improves the functionality of the filter, the adaptation circuit also increases the size of the filter. More specifically, the algorithms for generating "adaptive" coefficients, such as the least squares algorithm, (hereinafter "LMS") well known, require that a number of multiplication and / or addition operations be performed on the coefficients. Consequently, - several multiplication and / or addition circuits are required in each derivation cell to carry out the additional calculations. For the reasons noted above, this additional circuit increases the total filter size significantly.

BRIEF DESCRIPTION OF THE INVENTION An object, inter alia, of the invention is to provide a way by which to reduce the number of circuits. used in an adaptive digital filter, without adversely affecting the operation of the filter. The present invention solves the above need by providing a way to share the circuit for the adaptation and multiplication of the coefficient within a single filter cell of a digital filter. According to the invention, a plurality of coefficient recorders in the filtering cell circulate the values corresponding to the coefficients, while one or more data recorders in the filtering cell circulate a data value, so that the value of data is produced each time a different coefficient is produced. A circuit, such as a multiplication circuit, within the cell then processes the values and coefficients of the output data. By virtue of the above arrangement, it is possible, within a single filter cell, to process a data value with a plurality of coefficients using a processing circuit. Accordingly, fewer circuits are used in the filter cell, thus resulting in a decrease in the size of a filter including such a cell, without a corresponding decrease in filter capacities. Thus, according to one aspect, the present invention is a digital filter as defined in claim 1. A preferred embodiment of the invention is that defined by claim 2. By virtue of this feature of the invention, it is possible to update multiple coefficient values without significantly increasing the number of circuits in the filter cell, compared to a filtering cell, which updates a single coefficient only.

Another preferred embodiment of the invention is defined by claim 5. This feature of the invention facilitates the feeding of data to the system, so that the resources of the filtering cell can be shared by additional data values. A particularly preferred embodiment of the invention is defined by claim 6. By virtue of this feature of the invention, it is possible to share circuits to update the coefficients in a single filter cell, thereby providing additional reductions in filter size. . According to another aspect, the present invention provides a method for generating processed data in a digital filter cell as defined by claim 10. This method reduces the number of circuits required in a filtering cell, including, in a single cell filter, circuits to adapt the filter coefficients and the circuits used to process those coefficients. In this way, by virtue of this method, it is possible to reduce the number of filtering cells required in the filter, thus also reducing the total size of the filter.

According to another aspect, the present invention provides a digital filter as defined in claim 15. This brief summary has been provided so that the nature of the invention can be understood quickly. A more complete understanding of the invention can be obtained by reference to the following detailed description of the preferred embodiments thereof, in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram showing an adaptable FIR filter according to the present invention. Figure 2 is a block diagram of a first embodiment of a filter cell used in the FIR filter of Figure 1. Figure 3 is a synchronization table showing the circulation of the data values and the coefficient values in the filtering cell of Figure 2. Figure 4 is a block diagram of a second embodiment of a filtering cell used in the FIR filter of Figure 1.

DETAILED DESCRIPTION OF THE PREFERRED MODES First mode Initially, it should be noted that although the present invention can be used with any type of digital filter, the invention will be described in the context of an adaptable FIR filter. In this regard, Figure 1 shows an adaptive FIR filter having filtering cells, which implement a way to share, resources according to the present invention. As shown in Figure 1, the digital filter 1 includes the adder circuit 2, and a plurality of filter cells 4 (4a, 4b, ...). Any number of those filter cells 4 can be included in the digital filter 1, depending on the desired functionality of the filter. The digital filter 1 operates by sampling data from a signal at a predetermined sampling rate, and sequentially diverting the data product of sampling, marked as 6 in Figure 1, to each of the filtering cells 4 according to a signal of sampling clock. For example, the data product of sampling 6 is diverted to the filter cell 4a in response to a first sampling clock pulse. Then, when additional data samples are taken to a next sampling clock pulse, that additional data is diverted to the filter cell 4a, and the data already in the filter cell 4a is diverted to the filter cell 4b, and so on. . Each of the filtering cells 4 processes the data product of the sampling within a single period of the sampling clock signal. This processing can take into account the external power 7, which is shown in Figure 1, and of which detailed examples are described below. After the data product of the sampling have been processed by a filtering cell, the resulting processed data are sent to the adder circuit 2. The adder circuit 2, combine the data sent from each of the filtering cells 4 to generate the filter output 1. Figure 2 shows the internal circuits of the filter cell 4a shown in Figure 1. Since the filter cells 4 are identical in structure, for the purpose of being brief, only the filter cell 4a will be described here. As shown in Figure 2, the filter cell 4a includes the power register 9, multiplexer 10, the data loggers 11, the processing circuit 12, which is preferably a multiplier circuit, coefficient recorders 14 (14a, 14b , 14c, 14d), and logical steps 15, 16, 17 and 18. The arrangement shown in Figure 2 allows the data values to be diverted to the filtering cell 4a to share both the processing circuit 12 and the coefficients produced by the recorders of the coefficient 14, as will be clear from the following description. As shown in Figure 2, the input register 9 is arranged in series with the multiplexer 10 and the data registers 11 (lia, llb, 11c). Both input registers 9 and data recorders 11 may comprise conventional shift registers, which divert data in response to a clock signal. In this regard, as described in more detail below, the input register 9 deviates data in response to the signal of the sampling clock noted above. In contrast, data loggers 11 divert data in response to a circulation clock signal, which has a frequency that is a multiple of the sampling clock signal frequency. This arrangement provides for the multiple displacement of each of the data recorders 11 for each simple offset of the input register 9. The data register sends a data value to the processing circuit 12 at each circulation clock pulse. As shown in Figure 2, the same data value is fed back to the multiplexer 10 via the feedback path 20. The multiplexer 10 also receives the selection signal 21 and an output of the input register 9. The selection signal 21 that the multiplexer 10 diverts data from the recorder 9 during the pulses of the sampling clock, and causes the multiplexer 10 to deviate data from the feedback path 20 during the pulses of the circulation clock. By virtue of this arrangement, during the pulses of the circulation clock, the data values circulate within the data registers 11. However, at each pulse of the sampling clock, an additional data value of the input register 9 is diverted. to the data logger 11, where the additional data value circulates. In this way to summarize, the data loggers 11 circulate a first set of data values for a predetermined time, and, after the predetermined time, the data loggers 11 circulate a second set of data values (which include the additional data values), during the predetermined time, and so on. In this regard, data loggers 11 are designed to circulate the same number of data values. Accordingly, each time an additional data value is fed to the data logger 11, one of the data values already within the data loggers 11 is removed. Specifically, the data values in the feedback path 20 (ie, the data value that was the last to be sent to the processing circuit 12) are removed, since that data value is not fed back to the data logger 11. Since only one data value is removed per sampling clock period, the data loggers 11 generally circulate a data value for a plurality of sampling clock periods before that data value is removed. The exception to this general rule is the case in which a single data value is circulated in a single data logger. In this case, the data value only needs to be put into circulation during a sampling clock period for reasons which will be clarified later. An example of a filter cell having only one data logger is provided in the second embodiment below. The coefficient recorders 14 are arranged to circulate a plurality of coefficient values that correspond to a plurality of coefficients, so that each of the plurality of coefficient values occurs once during a predetermined period. More specifically, the coefficient values are deviated between coefficient registers 14 so that, at a predetermined period, which preferably corresponds to the period of the circulation clock signal, the coefficient recorder 14a sends a coefficient to a circuit 12. In this way, in each period of the circulation clock signal, the processing circuit 12 receives a data value of the data recorder lia and a coefficient of the coefficient recorder 14a. At this time, the processing circuit 12 processes (eg, multiplies) those two values to generate an output for the filtering cell. In this regard, it should be noted that although a multiplier circuit is described here, the processing circuit 12 can comprise any type of circuit, depending, of course, on the type of filtering cell in which the invention is implemented and the type of coefficients that are being shared. With respect to the coefficient registers 14, as shown in Figure 2, the coefficient registers 14 circulate coefficient values by feeding a coefficient sent to the processing circuit 12 again along the feedback path 22. This arrangement allows make the same coefficients circulate among the coefficient recorders 14, thus making it possible for these coefficients to be shared by data values in the data loggers 11. That is, as described above, that the data loggers 11 circulate a data value for a plurality of sampling clock periods before that data value is removed. As a result, the same data value is sent several times to the processing circuit 12 during several periods of the sampling clock signal. Each time the same data value is sent to the processing circuit 12, a different coefficient value is sent to it from the coefficient recorder 14a. As a result, each data value is processed with each coefficient. This process is illustrated below with respect to Figures 2 and 3. In the preferred embodiment of the invention shown in Figure 2, a plurality of logic steps 15, 16, 17 and 18 are arranged between the coefficient 14 recorders. logical stages receive internal inputs 25, 26, 27 and 28, respectively, and, if necessary, calculate the values of the updated coefficients corresponding to the coefficients produced by the coefficient 14 recorders. More specifically, as noted above, the filter cell 4a is an adaptive filter cell, which means that the coefficients therein can be periodically updated to correct undesirable changes in the data values, caused for example by changes in the transmission channel or the like. In the present invention, these updates are made via logical steps 15 to 18, where the external inputs 25 to 28 can comprise the filter error (i.e., a difference between the expected and actual outputs of the filter), or the like.

Thus, in the present invention, the calculation of the coefficient is "separated" into separate line steps, each of which is performed between the appropriate coefficient recorders. In consequence, in those embodiments of the invention, the coefficient values in the coefficient registers 14b, 14c and 14d do not necessarily include the real coefficients, consequently the indications of "primacy" in C2, C3 and C4. Instead, the coefficient values in these coefficient recorders can represent intermediate values of the calculation of the actual coefficients. This feature of the invention is advantageous, since it makes it possible to carry out the circulation and update of the coefficients simultaneously, thereby reducing, even more, the amount of physical computing components required to implement the filter cell 4a. In the preferred embodiments of the invention, logic steps 15 through 18 update the coefficients using the well-known LMS algorithm. However, it should be noted that the invention is not limited to the updating of the coefficients using this algorithm, and that any such algorithm can be used. Figure 3 shows a synchronization or timing table, which is used to explain the operation of digital filter cell 4a from times TO to T13 for data values from 1 to 8 and coefficient values from 1 to 4. More specifically, as shown in Figure 3, at the time TO, the values of the coefficients of 1, 2, 3 and 4 are in the coefficient registers 14a, 14b, 14c and 14d, respectively, while the values data of 1, 2 and 3 are in the data loggers lia, llb and 11c, respectively, and a data value of 4 is in the input register 9. The following charts the path of the data value 4 through the filtering cell 4a to illustrate how they share ^ the processing circuit 12 and the coefficient values 1, 2, 3 and 4. It should be understood, however, that the following description which relates to the data value 4 applies equally to all data values (for example, the values s of data 1, 2, 3, 5, 6 ...-) fed to the filter cell 4a. To begin, at the time TI, in response to a signal indicating that a sampling clock pulse has occurred, the data value 4 is diverted to the data recorder 11c and the data value 5 is diverted from an external source ( not shown) to the input register 9. This allows the data values 2, 3 and 4 to circulate in the data recorders 11. The circulation times for those values are indicated by the bracket 30 in Figure 3. It is say, as shown in Figure 3, at the time TI the data value 4 is in the data logger 11c, at the time T2 the data value 4 is in the data logger llb, and at time T3 the data value 4 is in the data recorder lia. From the data logger lia, the data value 4 is sent to the processing circuit 12 and fed back into the multiplexer 10. As noted above, the circulation clock pulses (as opposed to the sampling clock pulses) control the deviation of a data value 4 between data recorders lia, llb and 11c. At the same time that the previous circulation of the data value 4 takes place in the data recorders 11, the coefficient values from 1 to 4 are being put into circulation in the coefficient recorders 14, according to the circulation clock signal . That is, as shown in Figure 3, at time TI the value of coefficient 2 is in a coefficient recorder 14a, at time T2 the value of coefficient 3 is in a coefficient recorder 14a and at time T3 the coefficient value 4 is in the coefficient recorder 14a. Thus, at time T3 (ie, at the same time that the data value 4 is sent from the data recorder lia), the coefficient value 4 is sent to the processing circuit 12, where the value of coefficient 4 is processed with the data value 4.

After time T3, at time T4, the data value 4 is again circulated to the coefficient recorder (since the selection signal of 21 has not yet indicated the reception of the pulse of the sampling clock) and the coefficient value 1 is sent from the coefficient recorder 14a. Thus, after time T4, the four coefficient values (ie, 1, 2, 3 and 4) have been sent once during the time that the data value 4 has been circulating in the data loggers 11. Accordingly, at time T5 (that is, at the input of a sampling clock pulse), the coefficient values start a new circulation cycle, circulating in a sequence 2-3-4-1 shown in the brackets 31 in Figure 3. Also at time T5, the selection signal 21 indicates multiplexer 10 that a sampling clock pulse has been received. Thus, at time T5, the data value 5 is diverted to the coefficient data recorder 11c from the input register 9, while, at the same time, the data value 2 is removed from the data recorder 11. That is, at this point, the data value 2 is fed to the multiplexer 10, which selects the data value 5 and not the data value 2 to divert it to the coefficient data recorder. This allows the data values 2, 4, and 5 to circulate in the data loggers 11, and the data value 6, which was fed to the sampling clock pulse, in the input register 9. The circulation times for the data values 3, 4 and 5 are shown by the bracket 32 in Figure 3. The circulation of the data values 3, 4 and 5 continues in the manner described above, concurrently with the circulation of the coefficient values 1 , 2, 3 and 4 in the coefficient registers 14. As a result of these circulations, at time T6, the data value 4 is fed to the processing circuit 12 and the coefficient value 3 is also sent to the processing circuit 12. Subsequently, the circulation of the data values 3, 4 and 5 continues until the data value 6 is diverted to the data logger 11c at time T9. In this regard, the data value 6 is diverted to the data logger 11c in response to an indication that a sampling clock pulse has been received. The sampling clock pulse also causes the data value 7 to be fed to the input register 9, as shown. Also, at time T9, the data value 4 is sent to the processing coefficient 12 together with the coefficient value 2 of the coefficient recorder 14a. Subsequently, the circulation of the data values 4, 5 and 6 in the data loggers 11 continues (see bracket 34 in Figure 3), while the coefficients continue to circulate concurrently in the coefficient 14 recorders. As shown in FIG. Figure 3, during this same circulation cycle, at time T12 the data value 4 and the coefficient value 1 are sent to the processing circuit 12 via the data recorder lia and the coefficient recorder 14a, respectively. Subsequently, at time T13, the data value 4 is removed from the data recorders 11 in the manner noted above. Thus, it is clear from the previous example, that the filter cell 4a processes the data value 4 with each of the coefficients 1, 2, 3 and 4. This is highlighted by the values enclosed in a circle of Figure 3. In addition, the filter cell 4a does this using the same processing circuit. Accordingly, the invention manages to share the coefficient values in the processing circuit 12 with a single filter cell.

Second Modality At this point, it should be noted that the invention is not limited to using four data values and four coefficients in the manner discussed above. Instead, any number of coefficients and data can be used in a filter cell, as long as the data recorders in the filter cell circulate a data value for a time, which is at least as long as the period during which the coefficients are circulated, so that the data value is introduced each time that a different coefficient is produced. Furthermore, it should also be noted that the invention need not be implemented using the logical steps interposed between the coefficient recorders. In this regard, Figure 4 shows an example of a two coefficient filter and a data logger, in which different logical stages are not interposed between the coefficient recorders. The embodiment of the invention shown in Figure 4, namely, the filter cell 40, includes the input register 41, the data recorder 42, the multiplexers 44, 45, 46 and 47, the storage recorder 48, the circuit rounding / truncation 49, the multiplier circuit 50, the summing circuit 51, the (combination) update circuit of the coefficient 52, and the coefficient registers 53 and 54. In this embodiment of the invention, the operation of the filter cell 40 it is essentially that of the filter cell 40a shown in Figure 2. Accordingly, the focus here will be on the operational aspects of the filter cell 40 that they deviate from those of the filter cell 40a above.

In this regard, the operation of the input register 41, the multiplexer 45 and the coefficient registers 53 and 54, is substantially the same as the operations of the corresponding features described above. Consequently, a detailed description of them will be omitted here in order to be brief. However, if that matters, in the filtering cell 40, a single data value (as opposed to the plurality of data values) circulates within the data logger 42 during the period of the sampling clock signal. In addition, it should also be noted that the multiplexer 44 is provided in series with the input register 41 to select a data value to be fed to the recorder 41. A multiplexer positioned similarly to the filter cell 4a shown above can also be added. The filter cell 40 includes the storage recorder 48, which was not included in the filter cell 4a above. The storage recorder 48 stores the product of a data value and each coefficient. At predetermined time periods, for example, at each sampling clock pulse, the multiplexer 47 provides those values for the summing circuit 51, which adds up those values and sends the sum of those products from the filtering cell 40. It also provides a rounding / truncation circuit 49 for sending / truncating updated coefficient values before multiplication with a data value. The coefficient update circuit 52 is used to update the coefficient values on the basis of, for example, external information such as the filter error (i.e., the difference between the expected and actual filter outputs), cell data previous or subsequent filtering, etc. The multiplexer 46, which is controlled by the bifurcation of the read / write signal 56, also provides the filter cell 40 - with the ability to read coefficients of, and write coefficients a, a filter cell. In operation, the filter cell 40 circulates the coefficients in the coefficient recorder 53 and 54, and circulates a data value in the data recorder 42. This circulation is identical to that described above, except that the update circuit of the data 52, updates the values of the coefficients, instead of the interposed logical stages. Likewise, the deviation of additional data to, and from the input register 41, is identical to that described above. Consequently, in order to be brief, a detailed description of these processes was omitted here. The present invention has been described with respect to particularly illustrative embodiments. It should be understood that the invention is not limited to the embodiments and modifications thereof described above, and that various changes and modifications may be made by those skilled in the art, without departing from the scope of the appended claims. In the claims, any reference signs placed in parentheses will not be construed as limiting the claims. The word "comprising" does not exclude the presence of other elements or steps, in addition to t those listed in a claim. The invention can be implemented by means of physical computing components that comprise several different elements, and by means of a properly programmed computer. In the device claim several means are enumerated, several of which means can be incorporated by one and the same product of the physical computing components.

Claims (15)

CHAPTER CLAIMEDICATORÍO Having described the invention, it is considered as a novelty and, therefore, the content is claimed in the following CLAIMS:

1. A digital filter having a filtering cell for generating processed data, the filtering cell is characterized in that it comprises: a plurality of coefficient registers, which are arranged to circulate a plurality of coefficient values corresponding to a plurality of coefficients, so that each of the plurality of coefficients is sent and produced once during a predetermined period; one or more data loggers, which are arranged to circulate a data value for a time, which is at least as long as the predetermined period, so that the data value is produced or sent each time it is produced or sent one of the plurality of different coefficients; and a circuit, which receives each output data value and each output coefficient and generates processed data by processing each output data value with each output coefficient.

2. The digital filter according to claim 1, characterized in that it further comprises a plurality of logical steps arranged between the plurality of coefficient registers to effect the processing of the coefficient values to generate each one of the plurality of coefficients that they are produced by the plurality of coefficient recorders.

3. The digital filter according to claim 2, characterized in that the logical steps carry out the processing that updates the values of the coefficients, according to a change in a data value.

4. The digital filter according to claim 2, characterized in that the logic steps perform a least squares algorithm on the values of the coefficients to update each of the plurality of coefficients.

The digital filter according to claim 1, characterized in that it also comprises an input data logger, arranged in series with one or more data loggers, which receive an additional data value from an external source to the filtering cell; where, during the predetermined period, the input register diverts the additional data value to one or more data loggers, so that one or more data loggers circulate the additional data value.

The digital filter according to claim 5, characterized in that one or more of the data loggers comprise a plurality of data loggers, which circulate a plurality of data values; and where the plurality of data loggers circulates a first set of data values during a time corresponding to the predetermined period, after the predetermined period, the plurality of data loggers circulates a second set of data values during a time that corresponds to the predetermined period, where the second data set includes the additional data value of the input data logger and has the same number of data values as the first set of data values.

The digital filter according to claim 5, characterized in that it also comprises a multiplexer, placed between the input data recorder and one or more recorders, the multiplexer is used to determine if additional data values should be diverted towards one. or more data loggers, based on a signal corresponding to the predetermined period.

8. The digital filter according to claim 5, characterized in that the predetermined period corresponds to a sampling period of the digital filter.

9. The digital filter according to claim 1, characterized in that the circuit comprises a multiplier circuit, which multiplies each output value by each output coefficient to generate an output product.

10. A method for generating processed data in a digital filter cell, the method is characterized in that it comprises the steps of: circulating a plurality of coefficient values among a plurality of coefficient recorders in the digital filter cell; sending each of a plurality of coefficients from the plurality of coefficient recorders once during a given period, the plurality of coefficients being based on the plurality of values of the coefficients; circulating a data value between one or more data loggers, for a time, which is at least as long as the predetermined period, the data value is sent from one or more data loggers each time it is produced or is sent one of the plurality of coefficients; and process each output data value and each output coefficient to generate a processed data value.

The method according to claim 10, characterized in that it also comprises, before the sending step, the step of processing each of the plurality of coefficient values, to generate each of the plurality of coefficients.

The method according to claim 10, characterized in that it further comprises the steps of: receiving, in an input register, an additional data value from a source external to the filter cell; and diverting the value of additional data into one or more of the data loggers, during the predetermined period, so that one or more of the data recorders circulate the additional data value.

The method according to claim 12, characterized in that the deviation step circulates a plurality of data values among a plurality of data loggers; and where a first set of data values is circulated for a time corresponding to the predetermined period, and after the predetermined period, a second data set is circulated for a time corresponding to the predetermined period, where the second set of values The data set includes the additional data value of the input data logger, and has the same number of data values as the first set of data values.

14. The method according to the claim 12, characterized in that it further comprises the step of determining when to divert the additional data value towards one or more of the registers, on the basis of a clock signal corresponding to the predetermined period.

15. A digital filter, characterized in that it comprises: a plurality of filter cells, each one of them. filtering cells process a plurality of data values, together with a plurality of coefficient values, to generate an output or product of the filtering cell; and an adder circuit, which adds the product of the filtering cell of each of the plurality of filtering cells, to generate a filter output; wherein each of the plurality of filter cells comprises: a plurality of coefficient recorders, which are arranged to circulate a plurality of coefficient values corresponding to the plurality of coefficients, so that each of the plurality of coefficients, it is produced once during a predetermined period; one or more data loggers, which are arranged to circulate a data value for a time, which is at least as long as the predetermined period, so that the data value is produced each time a different one is produced of the plurality of coefficients; a multiplier circuit, which receives each output data value and each output coefficient and generates an output product; a storage recorder, which stores the output product of each output data value and each output coefficient; and an adder circuit, which adds the output values stored in the storage recorder, to generate an output of the filtering cell for the filtering cell.