MXPA99008548A - Computer memory organization - Google Patents

Abstract

In a memory in a computer system, buffers are defined by a buffer management system. A set Buffers command defines a number (NP) of pools of buffers, and for each pool, a pool size (PS) of the number of buffers in the pool and the size (BS) of the buffers in that pool. The buffer management system is initialized to store the buffer sizes and to cumulate and store the pool sizes. To address a buffer, the buffer management system determines the address of the start of the buffer from the desired pool and buffer numbers, using the stored information. Also, for updating a paged flash memory, a page Pn of the flash memory (4024) is copied as an image page into RAM memory (4022), and the image page is updated and written back into a different page in the flash memory. A main record table (22) is held in a separate non-volatile memory (EEPROM 4026), identifying valid page pages in the flash memory, and is updated when a page in the flash memory has been updated. The main record table includes a CRC error detection section (25), and is copiedinto a back-up record table (23) immediately after it has been updated.

Description

ORGANIZATION OF COMPUTER MEMORY The present invention relates to computer memories, and more specifically to the division of the memory areas therein and / or to the updating of the contents of the flash memory. This finds particular application in a receiver / decoder of a transmission and reception system, in particular a receiver / decoder of a television system and / or digital interactive satellite radio. However, it will be evident that this is not limited to that system or systems of that type, but it can be applied more generally to a wide variety of computer systems. In computer systems, particularly systems where the computer system is incorporated in some larger system such as a receiver / decoder for television or digital radio, the amount of memory is often limited. This means that the memory must be organized in such a way that the use of memory space by the different functions required by the system is minimized. In addition, it may also be necessary to minimize the time required to access at least some parts of the memory. One aspect of the present invention has to do particularly with the provision or organization of buffers in the memory. The conventional technique for providing buffers is by a dynamic system for allocating the required buffers. However, in the present context this standard system has certain drawbacks. This tends to result in the fragmentation of memory, and its speed is restricted by the need for higher operations. In addition, if an expansion of the buffers is required, this could require the movement of memory blocks to create space for expansion. In accordance with one aspect of the present invention there is provided a system for defining and directing buffers in a memory area in a computer system, comprising: group size storage elements for storing a plurality of group sizes; storage elements of buffer size for storing, for each group, a buffer size; and calculation elements for calculating from them the address of a desired buffer in a desired group. Preferably elements are included to determine the group sizes in cumulative form, and stored in that form in the group size storage element. You can define a reserved area at the beginning of each group, and provide elements to select either the cumulative group size address or the output of the calculation elements. The desired group number, the desired buffer number, and the desired byte can be verified for off-link values. Now a variety of types of computer memory are available. A major distinction between the different kinds of memory is between volatile and non-volatile memories. Volatile memory retains its content only while energy is supplied to memory, and loses its contents as soon as the power supply is cut off, while non-volatile memory retains its content indefinitely even if the power supply is cut off. The other major distinction is between the recordable memory and the read-only memory. Volatile memory is generally known as RAM, whereas there are different kinds of non-volatile memory. RAM is usually recordable, while read-only memory is known as ROM. This last distinction is not necessarily hard-and-fast. Any memory must of course be writable in some sense at least once, but some kinds of ROM-like memory can have their content changed, albeit with some difficulty. Therefore, there are types of memories such as the PROM (programmable memory (ie, recordable) read only), the EEPROM (programmable memory only electrically erasable), and the Flash. Different kinds of memory have different characteristics (for example, different reading times and different costs), so it is often desirable to use a combination of many different classes in a single computer system. Another aspect of the present invention has to do with flash memory. A flash memory is generally similar to ROM, in the sense that it is non-volatile. This also pretends to be used in a way generally similar to ROM, being read but not recorded. However, a flash memory is usually divided into pages, typically each of many kilobytes in length, and writing to flash memory is per page. In more detail, to write to the flash memory, you must delete a whole page, and then you have to write the new content on the deleted page; moreover, this writing has to be essentially a single, uninterruptible operation. (Obviously there may be an intermediate space between erasure and writing). In principle, the information in the flash memory can be organized into units of any size, from a single word upwards. In practice, however, this will normally be organized into blocks of substantial size. A block can comprise data, for example, permanent or semi-permanent information tables, or a program or subroutine. The sizes of the blocks will normally be selected to be smaller than the page size (if a block is larger than a page, it will usually be feasible to divide it into sub-blocks that are smaller than the page size). Typically, when updating a flash memory it is desirable to retain some of the information that is already in it. This requires, therefore, that the page being updated be read into the RAM to form an image of the page; then you can update this image in RAM by inserting any new information that will be entered into the page. At the same time, you can delete any information on the page that is no longer required. Then the updated image can be written back into the flash memory. In general, the size of the block will not be fixed; that is, different blocks will be of different sizes. Obviously this can cause difficulties when some existing blocks are going to be discarded, and fresh blocks will be added. These difficulties can be greatly overcome by allowing the blocks to be mobile, so that when a page is updated, the blocks that are to be retained on the page are configured, so that the areas not used on the page they merge into a single large unused area. If the blocks are mobile, then they can not be addressed by fixed addresses. Rather, some kind of location data structure or block address must be maintained, so that the blocks can be effectively searched through the use of some kind of name or descriptor. With blocks of different sizes, this requires information about both the locations and the nature of the blocks. This can be achieved in different ways. In this way you can keep a detailed directory of the blocks (their locations and nature) at the beginning of the flash memory, or you can keep a location directory of the blocks at the beginning of the flash memory, and each block can include a header that of the nature of the block. Alternatively, a separate block location data structure can be maintained for each page of the flash memory. All these block location data structures have the common characteristic that flash memory update is required for any change in their content. Writing a fresh block requires * obviously updating the flash memory; the deletion of a block also requires updating. Although it is not necessary to physically delete the block, the block location data structure has to be updated to indicate that the block is no longer valid. We have realized that the need for updating flash memory can be restricted to the addition of fresh blocks; in other words, the blocks can be deleted effectively without requiring the update of the flash memory. To achieve this, the block location data structure is maintained, at least partially, in an external memory, outside the flash memory itself, preferably in an EEPROM memory. The external memory may substantially contain the entire block location data structure, ie the addresses and descriptors of the blocks. Alternatively, the external memory may contain only the locations of the blocks in the flash memory, with the descriptors of the blocks being included in the flash memory as headers of the blocks themselves. In both cases, the external directory can be organized either as a single structure for the entire flash memory or on a per-page basis.

However, it is preferred to minimize the size of the external memory by maintaining in this only the validity of each block, with the addresses and descriptors of the blocks being kept in the flash memory itself. This reduces the external memory to a bitmap of the validity of the blocks. To erase a block in the flash memory, all that is required is to change the bit for that block in the external memory from "valid" to "invalid". Returning to the general page update procedure described above, this procedure has a problem. If the power supply to the system is interrupted during this procedure (or if any other interruption or major system failure occurs), the content of the RAM will be lost, so that the updated image of the page that is lost will be lost. it is being written inside the flash memory. The information previously on the flash memory page that is being updated will have been deleted, as a preparation for writing the updated page back into the flash memory. (And the updated page will have been written back into the memory only partially, so that some of its content will have been lost, and since the precise point at which the loss of energy occurred will not usually be known, it is not usually it will be known exactly how much of the updated page content has been written into the flash memory. An object of the present invention is to mitigate or overcome this problem. In accordance with this aspect, the present invention provides a flash memory system in a computer, wherein the flash memory is divided into separately recordable pages, comprising: elements for copying a page from the flash memory as an image page, within of the RAM memory and update the image page; elements to write the page of image of return inside a different page in the flash memory; a main record table, contained in a separate non-volatile memory, which identifies the valid pages in the flash memory; and items to update the main record table when a page has been updated in flash memory. The memory containing the main register table is preferably the EEPROM memory. The access to the flash memory will normally be through the main registration table. In normal operation, the main registry table will register some pages of the flash memory as valid and others as invalid, "invalid" meaning that page that does not contain valid information. A page may be invalid in different ways; this way it can be empty, it could have been copied successfully on another page, or the writing of it could have been interrupted. In the present system, the update of a page involves copying the page that is being updated from its existing page in the flash memory to another page (with the copying involving the update of the content of the page). In such a way that the present system must always keep at least one page as invalid; the page or invalid pages can be described equally as "spare". When a page is updated, the main record table is updated only after the copying of the page is completed. In this way, if the copying of a page is interrupted, the main record table will remain unchanged, in such a way that the original page will remain valid and the new page will remain as a replacement. Copying can be either retryed or abandoned later. Even with the system just described, there is a potential difficulty. The system described so far depends on updating the main record table. Therefore, it is important to ensure that the integrity of this main record table is high. Since the update of the main record table will be very fast compared to the update of a page of the flash memory, it may be possible to verify the status of the power supply immediately before updating the main record table, using a power supply that has sufficient capacity to keep the system operating for at least as much as required to update the main record table. Preferably, however, the main record table includes an error detection section, and it itself copies into a backup record table, immediately after it has been updated. Then the system will include elements to check the main log table to see if it has errors, when it is used to access the flash memory, and to use the backup log table if the main log table has an error. In this way, if the main registry table has an error, the system treats the last update of the flash memory as invalid, just as if the update had been interrupted. Of course it is possible that the copying of the main record table within the backup record table is interrupted. However, this copying occurs only after the main update of the main registry table has been completed.

"Any subsequent access of the flash memory will involve verification of the main log table, the main log table will be free of errors, so that you will not need to access the backup log table, and its defective status will be irrelevant. During the next update of the flash memory, however, the main log table will be updated.This update can be interrupted, as described above, and if this is done, then the backup log table has to be used to access Flash memory like this was before the update, so it is undesirable to allow the backup registry table to be defective.This can be conveniently achieved by copying the main log table into the backup log table. as the first step in updating the flash memory (or at least before writing the updated image page) of the RAM, in the spare page of the flash memory). From the above description it follows that the information or blocks of data in the flash memory are not located in fixed positions. Since the flash memory pages are updated, then the data blocks in them are moved from page to page, and they can also change their positions on the page. Therefore some form of directory is required, in such a way that blocks of data can be found when required. This directory information can be maintained in the log table or on the flash memory pages themselves, or divided between those two locations. We have noticed that in general the directory information does not normally change, unless the data blocks themselves are changed, therefore it is convenient to store it in the flash memory together with the data blocks. However, there is a directory-type information element that can change without changing the data itself; that is, whether a block of data is valid or not. Therefore it is convenient to store the validity information of the data block in the record table. This allows a block of data to be deleted effectively, without having to update the flash memory; all that needs to be done is to change the block indicator from valid to invalid. Of course, if the page is updated with that block at some later time, the blocks with invalid page indicators will not be copied to the image page in the RAM, so that they will be deleted in a more physical sense. that point. (In fact these will remain on the old page, which becomes the new replacement page, but of course they are inaccessible there, and when that new replacement page is used for the next update of the flash memory, its physical deletion will be complete .) Therefore, the record table preferably contains, for each page, a set of validity indicators of the data block, which can conveniently be in the form of individual bits. this increases the size of the record table, which in turn means that a variety of techniques can be used to provide the error detection section; it is preferred to use a cyclic redundancy check (CRC), although an error detection or correction code or a random check type function may be used. The validity indicators of the block for a page in the record table must be linked, of course, to the same blocks on that page in the flash memory. This can be done by keeping the blocks on the page in flash memory in the same sequence as their indicators in the log table. However, it is preferred to provide a header on each page in the flash memory, which contains a set of pointers to the actual locations of the blocks on that page; this allows greater freedom in the configuration of the same blocks on the page.

The identification information (for example, the name of the block) for each block on the page can be included either in the page header or as a block header at the beginning of the block itself. The last option is the one adopted in the preferred modality. This identification information can include information of the block link, such that a larger unit of data can be divided into 2 or more blocks. Another aspect of the present invention provides a receiver / decoder for use in a digital transmission and reception system, which includes a system or memory system or flash memory as described above. Preferably, the receiver / decoder also comprises elements for receiving a compressed MPEG-type signal, elements for decoding the received signal, for providing a television and / or radio signal, and elements for supplying the signal to a television and / or radio . The preferred features of the present invention will now be described, purely by way of example, with reference to the accompanying drawings, in which: - Figure 1 shows the overall architecture of a digital television system, according to the preferred embodiment of the present invention. Figure 2 shows the architecture of an interactive system of the digital television system. Figure 3 shows the configuration of the files inside a module downloaded into the memory of an interactive receiver / decoder. Figure 4 is a simplified block diagram of the relevant parts of the computer system. Figure 5 is a diagram of the organization of a part of the RAM memory. Figure 6 shows the structure of a Set Intermediate Memories command. Figure 7 is a diagram of the structure of the memory management unit. Figure 8 is a block diagram of the system. Figure 9 shows the logic diagram of the flash memory and the registration tables. Figure 10 shows the logical diagram of a flash memory page, and a subsection of the recording table. In Figure 1 an overview of a digital television system 1000 is shown. The invention includes a mostly conventional digital television system 2000, "which uses the known MPEG-2 compression system to transmit compressed digital signals." In more detail, the 2002 MPEG-2 compressor is a transmission center receiving a stream of digital signals. (typically a stream of video signals.) The compressor 2002 is connected to a multiplexer and encoder 2004 by means of the link 2006. The multiplexer 2004 receives a plurality of additional input signals, assembles one or more transport streams and transmits digital signals compressed to a transmitter 2008 of the transmission center by means of link 2010, which of course can take a wide variety of forms, including telecom links.The 2008 transmitter transmits electromagnetic signals via the 2012 uplink, to a transmitter-receiver 2014 by satellite, where they are processed electronically and transmitted through of the 2016 speculative descending link to the land receiver 2018, conventionally in the form of a proprietary dish or rented by the end user. The signals received by the receiver 2018 are transmitted to an integrated receiver or decoder 2020 owned or rented by the end user, and connected to the television set 2022 of the end user. The receiver / decoder 2020 decodes the compressed MPEG-2 signal to a television signal for the television set 2022.

A conditional access system 3000 is connected to the multiplexer 2004 and the receiver / decoder 2020, and is located partially in the transmission center, and partially in the decoder. This allows the end user to access the digital television transmissions from one or more transmission providers. You can insert a smart card, capable of deciphering messages related to commercial offers (that is, one or many television programs sold by the transmission provider), within the receiver / decoder 2020. Using the decoder 2020 and the smart card, the end user can buy commercial offers either in a subscription mode or a pay-per-event mode. An interactive system 4000, also connected to the multiplexer 2004 and the receiver / decoder 2020, and again partially located in the transmission center and partially in the decoder, allows the end user to interact with different applications by means of a modulated return channel 4002. -desmodulated. Figure 2 shows the general architecture of the interactive television system 4000 of the digital television system 1000 of the present invention. For example, the interactive 4000 system allows an end user to buy catalog items on the screen, check local news and climate maps on demand, and play games through their television set. The interactive system 4000 comprises in general four main elements: - an originating tool 4004 in the transmission center (or some other place), to allow a transmission provider to create, develop, debug and test applications; an application and data server 4006, in the transmission center, connected to the originating tool 4004, to enable a transmission provider to prepare, authenticate, and format applications and data for forwarding to the multiplexer and encoder 2004 for insertion into the MPEG-2 transport stream (typically the private section thereof) to be transmitted to the end user; a virtual machine that includes a runtime machine (RTE) 4008, which is an executable code installed in the receiver / decoder 2020 own or rented by the end user, to allow the end user to receive, authenticate, decompress, and load applications within working memory 2024 of receiver / decoder 2020 for execution. Machine 4008 also runs resident, general-purpose applications. The machine 4008 is independent of the hardware and operating system; and a modulated-demodulated back channel 4002 between the receiver / decoder 2020 and the application and data server 4006, to enable signals that tell the server 4006 to insert data and applications into the MPEG-2 transport stream upon request of the end user. The interactive television system operates using "applications" that control the functions of the receiver / decoder and different devices contained therein. The applications are represented on the machine 4008 as "resource files". A "module" is a set of files and resource data. Many modules may be required to form an application. A "memory volume" of the receiver / decoder is a storage space for the modules. An "interface" is used to download modules. The modules can be downloaded into the receiver / decoder 2020 from the MPEG-2 transport stream. Now the elements mentioned in the previous paragraph will be described in more detail. For the purposes of this specification, an application is a piece of computer code for controlling high-level preference functions of the receiver / decoder 2020. For example, when the end user places the focus of a remote controller on a button object that is seen on the screen of the television set 2022, and presses the validation key, the sequence of instructions associated with the button is executed. An interactive application proposes menus and executes commands on the end user's request, and provides data related to the purpose of the application. The applications can be either resident applications, that is, stored in the ROM (or FLASH or other non-volatile memory) of the receiver / decoder 2020, or transmitted and downloaded into the RAM or FLASH of the decoder 2020. The examples of the applications are; - • An Initialization Application. The receiver / decoder 2020 is equipped with a resident initialization application which is an adaptive collection of modules (this term being defined in more detail later herein), which allows the receiver / decoder 2020 to be immediately operative in the MPEG environment. 2. The application provides core characteristics that can be modified by the transmission provider if required. It also provides - an interface between the resident applications and the downloaded applications. • An Ignition Application. The application of ignition allows any application, whether downloaded or resident, to run on the receiver / decoder 2020. This application acts as a loading operation on the arrival of a service, in order to start the application. The ignition is discharged into the RAM and, therefore, can be easily updated. This can be configured in such a way that the interactive applications available on each channel can be selected and executed, either immediately after downloading or after preloading. In the case of pre-loading, the application is loaded into the 2024 memory, and activated by powering on when required. • A Program Guide. The Program Guide is an interactive application that gives complete information about programming. For example, it can give information about, say, the one-week television programs provided by each channel of a digital television bouquet. By pressing the key on the remote controller 2026, the end user accesses an added screen, above the event that is displayed on the television set 2022 screen. This added screen is a navigator that gives information about the current and future events of each channel of the digital TV corsage. By pressing another key on the remote controller 2026, the end user accesses an application that visually displays a list of information about the events during a week. The end user can also search and select events with simple and custom criteria. The end user can also directly access a selected channel.

• One Pay Per View application. The pay-per-view application is an interactive service available on each Pay Per View channel of the digital TV bouquet, in conjunction with the 3000 conditional access system. The end user can access the application using a TV guide or channel navigator. Additionally, the application automatically starts as soon as the Pay Per View event is detected on the Pay Per View channel. Then the end user is able to buy the event in progress either through his smart daughter 3020 card or via communication server 3022 (using the modem, a telephone and DTMF, MINITEL or similar codes). The application can be either resident in the ROM of the receiver / decoder 2020 or downloadable within the RAM of the receiver / decoder 2020. • A PC Download application. Upon request, an end user can download computer software using the PC download application. • A Magazine Browser application. The magazine browser application comprises a cyclic video transmission of images with navigation of the end user via buttons on the screen. • A questionnaire application. The questionnaire application is preferably synchronized with a transmission questionnaire program. As an example, multiple selection questions are displayed on the 2022 television screen visually, and the user can select a response using the remote 2026 controller. The questionnaire application can inform the user if the answer is correct or not, and can keep score of the user. • An application of Shopping by Television. In one example of the television shopping application, goods for sale are transmitted to the receiver / decoder 2020, and displayed visually on television 2022. Using the remote controller, the user can select a particular item to buy it. The order of the article is sent via the modulated-demodulated return channel 4002 to the application and data server 4006, or to a separate sales system, whose telephone has been downloaded to the receiver / decoder, possibly with an order to charge the account to a credit card that has been inserted in one of the 4036 card readers of the receiver / decoder 2020. • A Telebanca application. In one example of the telebanking application, the user inserts a bank card into one of the receiver cards 4036 of the receiver / decoder 2020. The receiver / decoder 2020 marks the user's bank, using a telephone number stored on the card bank or stored in the receiver / decoder, and then the application provides a number of facilities that can be selected using the remote 2026 controller, for example, to download an account statement via the telephone line, transfer funds between accounts, request a checkbook, etc. • An Internet Browser application-. In an example of the Internet browser application, user instructions are entered, such as a request to view a web page that has a particular URL, using the remote 2026 controller, and these are sent through the modulated return channel 4002. -desmodulated to application server 4006 and data. The appropriate web page is then included in the transmissions from the transmission center, received by the receiver / decoder 2020 via the uplink 2012, the transmitter-receiver 2014 and the descending 2016 link, and is displayed visually on the television 2022. The applications are stored in the memory locations in the receiver / decoder 2020 and are represented as resource files. Resource files include graphics object description unit files, variable block unit files, instruction sequence files, application files, and data files. The graphic object description unit files describe the screens, the man-machine interface of the application. The variable block drive files describe the data structures that the application handles. The instruction sequence files describe the processing operations of the applications. The application files provide the entry points for the applications. Applications made in this way can cause data files, such as icon library files, image files, character font files, color table files, and ASCII text files. An interactive application can also obtain data online by making entries and / or outputs. The machine 4008 only loads into its memory those resource files that it needs in a given moment. These resource files are read from the graphic object description unit files, instruction sequence files, and application files; the variable block drive files are stored in the memory after a procedure call to load the modules and remain blocked there until a specific call is made to a procedure to download the modules. With reference to Figure 3, a module 4010, such as a television shopping module, is a set of resource and data files comprising the following: a single application file 4012; an indeterminate number of files 4014 of the graphic object description unit; an indeterminate number of 4016 files of variable blocks unit; an indeterminate number of 4018 instruction sequence files; and where appropriate, 4020 data files, such as icon library files, image files, character font files, color table files and ASCII text files. In the MPEG data stream, each module comprises a group of MPEG tables. Each MPEG table can be formatted as a number of sections. In the MPEG data stream, each section has a "size" of up to 4 kbytes. For the transfer of data through the serial and parallel port, "for example, the modules are divided in a similar way into tables and sections, the section size varying with the means of transport." The modules are transported in the current. MPEG data in the form of data packets of typically 188 bytes, within respective types of data streams, for example, video data streams, audio data streams and teletext data streams. preceded by a packet identifier (PID) of 13 bits, a PID for every packet transported in the MPEG data stream A table of program maps (PMT table) contains a list of the different streams of data, and defines the content of each data stream, in accordance with the respective PID A PID can notify a device of the presence of applications in the data stream, the PID being identified using the PMT table. Referring to Figure 4, the receiver / decoder comprises a memory 4022 RAM coupled to a microprocessor 20, which is also coupled to a flash memory 4024, a memory 4024 'EEPROM, and a memory 4026 ROM on a bus 21. The 4022 RAM memory is also coupled to a DMA unit 22 (direct memory access), through which data (e.g., from an MPEG bit stream) can be input directly into the RAM memory. The RAM is 256 kbytes long, and is divided into 3 areas: an area 24 that is reserved for use by the system manufacturer; an area 25 that is reserved for use by a virtual machine (VM), and a user area 26 that is used to contain a variety of information such as buffers, applications 30, 30 ', 30", data, and so on. . The system is defined by a functional specification that gives the manufacturer considerable freedom to design the hardware to implement the system; the memory area 24 is in effect used as an interface between the functions specified by the functional specification and the hardware. The VM in area 25 is in effect a kind of operating system for the computer system, and the VM and the microprocessor 20 can be considered together as a runtime machine (RTE) 4008. A variety of different applications within the memory at different times. Communication between the VM and the applications is necessary, and between the different applications themselves, this communication is handled mainly by means of the intermediate memories, which are common to the VM and to the various applications. In the present system, a command (the Set Intermediate Memories command) is used to define a buffer area 32 in the user area 26, and the division of that buffer area into individual buffers. This defines a number of buffer groups; for each group, the size of the buffers in the group and the number of buffers in the group are given. Figure 6 shows the logical format of the Set Intermediate Memories command. It comprises an initial entry 35 that defines the number of groups NP, followed by a set of entries 36, 36 ',, one for each group, with each group entry consisting of a first sub-entry 37 that defines the group size PS of the group (i.e., the number of buffers in the group), and a second sub-entry 38 that defines the size of the buffer BS of the buffers (ie, the number of bytes in the buffers) in the group. For convenience, these and other parameters that are used later are listed: NP: number of groups per group - PS: group size (number of buffers in the group) BS: size of the buffer PN: group number BN: number buffer (in the group) B &W: byte number (in the buffer) As shown in Figure 5, in the user memory area 26, the buffer groups are sequentially configured from the beginning of that area. The actual scheme shown is for 3 groups, with Group 1 consisting of 5 medium-sized buffers, Group 2 consisting of 6 small-sized buffers, and Group 3 consisting of 1 large-sized buffer. It will also be noted that each group of buffers includes a reserved 16-byte section at its beginning. This section is divided into a 12-byte subsection that is available to users for use as buffer flags, and so on, and a 4-byte subsection that is reserved for the use of the VM. The RTE 4008 implements a buffers manager that can be considered as forming an address path 27 between the collector bar 21 and the user area 26 of the RAM memory 4022. Figure 7 shows the logical organization of the buffer manager . This is initialized -firstly by means of a command to Set Intermediate Memories, under the control of the microprocessor 20; it is then used to direct any desired buffer. In the buffer manager, the sub-inputs PS and BS for each group are fed in turn to a multiplier 35, which forms its products PS * BS. An accumulator 36 is initialized with the value 64k (which represents the start address of the user area 26 of the RAM 4022), and is fed with the PS * BS product sequence by means of an adder 37, which adds 16 in each product; this 16 represents the size of the section reserved at the beginning of each group. Accumulator 36 thus contains, in succession, the starting addresses of each of the groups of buffers in succession. These group start addresses are fed to a cumulative address register 38 in which they are stored in sequence. In addition, during initialization, the number of NP groups is stored in a number of the group register 39, the sizes of the groups are stored in a record 40 of group sizes, and the sizes of the BS buffers are stored in the same sequence in a register 41 of buffer sizes. After initialization, buffers can be directed. To direct a buffer, the desired buffer is defined by means of a PN group number for the desired group, a buffer number BN for the desired buffer in that group, and a byte number B and N for the desired byte inside that buffer. The group number PN is used to select the appropriate entries for that group of the accumulative register 38 and the register 40 of buffer sizes. The buffer size BS is fed to a multi-plicator 45, wherein it is multiplied by the number of buffers BN. The resulting product is fed to an enhancer 46 which adds 16 to the product. The output of the cumulative register 38 is fed to an adder 47, where it has added to it the byte number B and N. The output of the increment 46 is fed to an adder 48, where it is added to the output of the adder 47. The output of the adder 48 passes through a multiplexer 49 as the desired address; that is, the address of the desired byte of the desired buffer of the desired group. The buffers manager also includes the error verification circuitry. The group number PN is fed to a comparator 53 which is also fed with the number of groups NP of the register 39, to verify that the selected group number is not greater than the number of groups; that is, to verify that the selected group is within the buffer area. The buffer number is fed to a comparator 54 which is also fed with the output of the selected input in the group size register 40, to verify that the selected buffer number is not greater than the number of memories. intermediates in the selected group; that is, to verify that the selected buffer is within the selected group. The selected byte number is fed to a comparator 55 which is also supplied with the size of the buffers in the selected group, to verify that the desired byte number is not greater than the length of the buffer; that is, to verify that the selected byte is within the selected internal memory. All these comparators are fed to a common output, which produces an ERR error signal if any of the checks fail. So far the description has assumed that a buffer is being directed. However, one might wish to direct the initial reserved or special 16-byte area of a group of buffers. The selection between these two options is controlled by an N / C signal, which selects between the normal accesses to the buffer and what might be called for convenience buffer control operations. For normal accesses, buffers are selected; the reserved initial area of a group of buffers is only selected for control operations. The N / C signal is fed to the multiplexer 49. For normal accesses to the buffer, this signal selects the output of the adder 48, as described above. For control operations in the reserved area of a group, however, the multiplexer selects rather the output of the direct adder 47. Since this path from the cumulative register 38 does not pass through the incrementer 46, this results in the selection of the desired byte in the reserved area of the group, rather than in one of the buffers after that reserved area. For control operations in the buffer area, it is necessary to disable the comparator 55. Therefore, the N / C signal enables this comparator for normal access to the buffer memory and disables it for control operations. Another comparator 56 is also fed with the byte number B and N and the number of bytes in the reserved areas of the groups, that is, 16, and is enabled by means of the N / C signal for the accesses to the system. This comparator verifies that the desired byte number is not greater than 16; that is, it verifies that the selected byte is within the reserved area at the beginning of the selected group. Obviously, this check can be refined to discriminate between accesses to the 12-byte subsection that is available for users to use as buffer flags, and so on, and the 4-byte subsection that is reserved for the use of the RTE. . As shown in Figure 9, if desired, the Set Intermediate Memories command can also include a User Memory End parameter 34, which defines the end of the user's memory area 26. The last entry in the Set Intermediate Memories command would be stored in an appropriate register, and can be used to verify that the area of the buffer memory does not extend beyond the end of the user's memory area 26. (This is generally extremely unlikely, since space has to be left for applications , 30 ', 30' ', However, this could happen if the system is designed in such a way that the area of the buffer can be located somewhere in the middle of the user's area, rather than in its beginning , as described above . ) In principle, the Set Intermediate Memories command can be used to initialize the buffer area at any time. However, • re-initializing the buffer area will effectively result in the loss of all (or almost all) of the information that is already in the buffers, so the Set Intermediate Memory command will normally be executed only in the initialization of the system. Referring to Figure 8, the system comprises a flash memory 4024, a memory 4022 RAM, and a memory 4026 EEPROM, all coupled to a microprocessor 120 through a bus 121. (Alternatively, the EEPROM memory may be directly coupled to the microprocessor 120.) As shown in Figure 9, the flash memory is divided into 8 pages P1-P8 of equal size. From these pages, page P8 is reserved for the use of the manufacturer; the remaining pages are free for the user to use. Figure 9 also shows the record 122 of the main record table and the record 123 of the backup record table, which are resident in the EEPROM 4026. The information in these tables are somehow in compressed and encoded form. Specifically, the final section 125 of table 122 is a CRC byte, and section 126 before that is a page number identifying the replacement page. The first section 127 of table 122 consists of 6 subsections 127-1 to 127-6, one for each of the valid flash memory pages (ie, the 6 pages that were moved away from the replacement page and the page P8 reserved). These subsections correspond to these remaining pages in sequence. Figure 10 shows the logical schema of a Pn page of the flash memory and a 127-m subsection of the log table, and the relationship between them. (Depending on where the replacement page is located, m can be equal to n-1.) Considering the flash memory page first, it can contain a maximum of 16 data blocks. The page has a header 130 that contains 16 sections, one for each possible data block. Each header section 130 contains an offset or pointer at the start of this data block; this pointer is in effect the address of the block inside the page. The blocks 131, 131 ', .... of data on the page can therefore be in any order. Each data block contains a respective header 132, 132 ', .... which may contain a variety of issues related to the block, such as the name of the block, a version number, the length of the block, information of its state, and so on. The 127-m subsection of the register table consists of 16 bits, each bit being a validity indicator of the block for the corresponding section in the page header 130, as shown. Now we will describe the process of updating a page in the flash memory. All the manipulations that are required for updating the page are performed by the microprocessor 120. First, the main record table in the record 122 is checked to see its validity; that is, the CRC of sections 126 and 127 is calculated and compared to the CRC stored in section 125. The main record table is then copied into register 123 of the backup record table (and, if desired , then you can check the backup log table to see its validity, to ensure that the copying was free of errors). Then, the page that is being updated (the old page) is copied from the flash memory to the RAM memory. Section 127-m is extracted from the main record table for that page, and any blocks of data marked as invalid from the image of the page in the RAM memory are deleted. The new data blocks are written in the image of the page. It could be that the new data blocks do not easily fit into the spaces between the remaining original data blocks. These remaining blocks will generally be separated by blank areas of different sizes. Therefore these are changed above the page image to "squeeze" the unused areas between them, to effectively move the unused areas to the bottom of the page image, to form a single area not used. This ensures that the new data blocks can be written to the page image (provided, of course, that the page capacity is not exceeded). Of course the header of the block is updated in the image of the page, by means of changing its pointers to the new positions of the blocks of data in the image of the page. The subsection of the record table for the page being updated was previously extracted from the record table. Now the extracted subsection is updated, by means of establishing bits of validity for any new blocks of data that have been added to the image of the page. Then, the entire section 127 of the record table of record 122 of the main record table is extracted. The subsection that corresponds to the page that is being updated (the old page) is effectively deleted. This is the subsection that was previously extracted by itself, and has been updated. This new subsection (corresponding to the new page, ie the spare page within which the updated page is being written) is inserted into the sequence of subsections at the appropriate point. For this, the subsections have to be changed together for any pages between the old and new pages, to fill the subsection that has been deleted and make room for the new subsection. Then, the image of the updated page is copied into the RAM memory on the replacement page, as identified by the spare page number in section 126 of the main record table. Then, the page number in the spare page section is changed to the page number of the old page, which now becomes the new spare page. Then, the updated record table is copied into register 122 of the main record table. Finally, the updated content of the record 122 of the main record table is copied to the record 123 of the backup record table, and, if desired, the content of the main record table can be checked in the record 122 and / or from the backup log table to see its validity. When the system is rebooted, for example, after a power interruption, the two log tables can be checked to see their validity; if it is found that anyone is invalid, it can be replaced by the valid one (that is, the content of the valid registration table that is being copied into the invalid registration table). It will be understood that the present invention has been described above purely by way of example, and any modifications of the detail may be made within the scope of the invention. Each feature described in the description may be provided, and (where appropriate) the claims and drawings independently or in any appropriate combination. In the preferred embodiments mentioned above, certain features of the present invention have been implemented, using computer software. However, it will of course be clear to the experienced person that any of these features can be implemented, using the hardware. Additionally, it will be readily understood that the functions performed by the hardware, computer software, and the like, are performed on or using electrical or similar signals. The cross reference is made to our pending requests, all of them having the same filing date, and titled Signal Generation and Transmission (Lawyer Reference Number PC / ASB / 19707), Smart Card for use with a Transmission Signal Receiver. Key, and Receiving System (Lawyer Reference Number PC / ASB / 19708), Transmission and Reception and Conditional Access System for it (Lawyer Reference Number PC / ASB / 19710), Downloading a Computer File from a Transmitter through a Receiver / Decoder to a Computer (Lawyer Reference Number PC / ASB / 19711), Transmission and Reception of Television Programs and Other Data (Lawyer Reference Number PC / ASB / 19712), Downloading Data (Lawyer Reference Number PC / ASB / 19713), Computer Memory Organization (Lawyer Reference Number PC / ASB / 19714), Development of Television or Radio Control System (Attorney Reference) Number PC / ASB / 19715), Extracting Data Sections from a Transmitted Data Stream (Lawyer Reference Number PC / ASB / 19716), Access Control System (Lawyer Reference Number PC / ASB / 19717), System of Data Processing (Lawyer Reference Number PC / ASB / 19718), and System of Transmission and Reception, and Receiver / Decoder and Remote Controller for it (Lawyer Reference Number PC / ASB / 19720). The descriptions of these documents are incorporated herein by reference. The list of applications includes the present application.

Claims (44)

1. A system for defining and directing buffers in a memory area in a computer system, comprising: group size storage elements for storing a plurality of group sizes; storage elements of buffer size for storing, for each group, a buffer size; and calculation elements for calculating from them the address of a desired buffer in a desired group.

2. A system, according to claim 1, which includes elements for determining the sizes of the groups in cumulative form, and storing them in that form in the group size storage element.

3. A system, according to any of the previous claims, which includes elements to define an area reserved at the beginning of each group.

4. A system, according to claims 2 and 3, which includes elements to select either the direct cumulative group size or the output of the calculation element.

A system, according to any of the previous claims, which includes elements for verifying the out-of-link values of the desired group number, the desired buffer number, and the desired byte.

6. A system for defining and directing buffers in a memory area, substantially as described herein.

7. A memory system in a computer, comprising flash memory that is divided into separate recordable pages; the RAM memory, the non-volatile memory separated to contain a main register table that identifies the valid pages in the flash memory; elements to copy a page from the flash memory as an image page in the RAM memory, and update the image page; elements to write the image page again on a different page in the flash memory; and items to update the main record table in non-volatile memory when a page has been updated in flash memory.

A memory system, according to claim 7, wherein the main registration table identifies a spare page in flash memory, the writing elements being configured to write the image page on the replacement page identified in the flash memory. .

9. A memory system, according to claim 8, wherein the update element is configured to update a spare page identifier in the main record table, when a page in the flash memory has been updated.

10. A memory system, according to any of claims 7 to 9, wherein a valid page of the flash memory contains valid information.

11. A memory system, according to any of claims 7 to 10, wherein: the main register table includes an error detection section; and where are provided: a backup record table within which the main record table is copied, immediately after it has been updated; and items to check the main log table to see if it has errors, when it is used to access the flash memory, and to use the backup log table if the main log table has an error.

12. A memory system, according to claim 11, wherein the error detection section is a CRC section.

A memory system, according to any of claims 7 to 12, wherein the record table includes, for each page, a set of -block validity indicators for the data blocks in the corresponding page.

14. A memory system, according to any of claims 7 to 13, wherein the identification information for the blocks in a page is included in the page.

15. A memory system, according to claim 14, wherein the identification information for each block is included in that block.

16. A memory system, according to any of claims 7 to 15, wherein said separate non-volatile memory is EEPROM.

A memory system, according to any of claims 7 to 16, wherein the table or tables of record include a spare page identifier and a sequence of subrecords, each relating to a respective valid page.

18. A memory system substantially as described herein.

19. A method for updating a flash memory divided into separate recordable pages, comprising: copying a page from the flash memory as an image page, into the RAM memory and updating the image page; write the image page back inside a different page in the flash memory; provide a main record table, contained in a separate non-volatile memory, which identifies the valid pages in the flash memory; and update the main record table when a page has been updated in flash memory.

20. A method, according to claim 19, wherein the main record table identifies a spare page in the flash memory, the image page being written within the spare page identified in the flash memory.

21. A method, according to claim 20, wherein a spare page identifier is updated in the main record table when a page in the flash memory has been updated.

22. A method, according to any of claims 19 to 21, wherein a valid page of the flash memory contains valid information.

23. A method, according to any of claims 19 to 22, comprising; provide a backup record table, inside which the main record table is copied, immediately after it has been updated; and check the main log table to see if it has errors, when it is used to access the flash memory, and use the backup log table if the main log table has an error.

24. A method, according to claim 23, wherein the error detection section is calculated as a CRC.

25. A method, according to any of claims 19 to 24, wherein, for each page, a set of block validity indicators is included for the blocks of data on the corresponding page, in the record table.

26. A method, according to any of claims 19 to 25, wherein the identification information for the blocks on a page is included in the page.

27. A method, according to claim 26, wherein the identification information for each block is included in that block.

28. A method, according to any of claims 19 to 27, wherein the table or tables of record are stored in an EEPROM.

29. A method, according to any of claims 19 to 28, wherein a spare page identifier and a sequence of subrecords, each related to a respective valid page, are included in the table or tables of record.

30. A method, according to any of claims 19 to 29, wherein the main record table is verified to see its validity, before copying the page of the flash memory as an image page within the RAM memory.

31. A method, according to claim 30, wherein the main record table is copied into the backup record table, immediately after verification of the main record table to see its validity.

32. A method, according to claim 31, wherein the backup record table is verified to see its validity, immediately after the copy of the main record table within it.

33. A method, according to any of claims 19 to 32, wherein the valid data blocks are reconfigured in the image page, to eliminate unused spaces between them.

34. A method for updating a flash memory divided into separately recordable pages, substantially as described.

35. A flash memory system in a computer, where the data is contained in blocks in the flash memory, and a data structure "of location of blocks is maintained, which determines the locations and the descriptors of the blocks, where the block location data structure is maintained, at least partially, in an external memory outside the flash memory itself 36.

A flash memory, according to claim 35, wherein the external memory is an EEPROM.

A flash memory, according to any of claims 35 and 36, wherein the external memory can substantially contain the entire block location data structure

38. A flash memory, in accordance with any of the claims 35 and 36, where the external memory contains only the locations of the blocks in the flash memory, with the descriptors of the blocks being included in the flash memory as enc beepers of the same blocks.

39. A flash memory, according to any of claims 37 and 38, wherein the external directory is organized as a single structure for all flash memory.

40. A flash memory, according to any of claims 37 and 38, wherein the external directory is organized on a per-page basis.

41. A flash memory, according to any of claims 35 to 40, wherein the external memory contains for each block only one validity bit, with the addresses and descriptors of the block being kept in the flash memory itself.

42. A receiver / decoder for use in a digital transmission and reception system, including a system or memory system or flash memory, according to any of claims 1 to 18 or 35 to 41.

43. A receiver / decoder , according to claim 42, characterized in that it also comprises: elements for receiving a compressed MPEG-2 type signal; elements for decoding the received signal to provide a television and / or radio signal; and elements to supply the signal to a television and / or radio.

44. A receiver / decoder for use in a digital transmission and reception system, substantially as described herein.