MXPA99007033A - Method and apparatus for reliable operation of universal voice grade cards - Google Patents

Abstract

A fiber to the curb communication system providing telephone service to subscribers using line cards which are pluggable into a broadband network unit. The line cards provide telephone service to up to six lines per card. The cards are programmable from a central location, and the system includes self-testing of the cards, ring generator testing and provides for testing of the telephone lines from the system to the subscriber's location.

Description

METHOD AND APPARATUS FOR THE RELIABLE FUNCTIONING OF UNIVERSAL VOICE DEGREE CARDS BACKGROUND PE THE INVENTION Sidewalk fiber systems (FTTC) can provide both traditional telecommunications services and old telephone service (POTS) as well as advanced services such as Digital Video Switched (SDV) and high-speed data access. Due to the range of services that can be supported, it is possible that FTTC systems are widely developed by telephone companies when installing new lines and updating their networks. Since POTS is the basic telephone service used by more than 100 million subscribers in the U.S., it is essential that the service be reliable. The FTTC team provides POTS service through the use of a printed circuit board that contains electronics that support one or more telephone lines, typically a universal voice grade (UVG) card. UVG cards are located in a broadband network unit that is typically located in the neighborhood near a group of houses. In a widespread FTTC development there will be millions of UVG cards for BNUs, and telephone companies will maintain large inventories of these cards for installation and maintenance.

The malfunctioning of a UVG card may take place due to the fact that the card has an electrical fault, or it may occur due to an error in the software, including hardware programmable state machines contained within the card. In addition, it is possible that a UVG card may be incompatible with a particular FTTC system due to design flaws or defective manufacturing. The key aspects in the operation of the UVG card include the proper functioning of any application-specific integrated circuits (ASICs) on the card, the proper functioning of the state machine that controls the different states of the line including hanging, off-hook and ringing, as well as the ability to modify the state machine in case of a programming error or system change, and the ability to properly test the communications channel formed by the circuit on the UVG card and the twisted pair lowering cable that connects the card to residential telephone wiring. For the above reasons there is a need for methods and apparatus to identify the type and source of UVG cards in the FTTC system, to properly test the operation of any ASICs on the UVG card, to check the software of the state machine and to download new versions of state machine software, as well as test the subscriber's telephone line.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a fiber network to the sidewalk; Figure 2 shows a functional block diagram of the broadband network unit illustrated in Figure 1; Figure 3 shows a functional block diagram of a portion of a UVG card used in the broadband network unit of Figure 1; Figure 4 shows a functional block diagram of the broadband network unit of the common control circuit; Figures 5A, 5B and 5C show the electrical schematic of a portion of a UVG card; Figure 6 shows a functional block diagram of the application-specific integrated circuit used in a UVG card; Figure 7 shows the TDM interface signals between the common control of the broadband network unit and the UVG cards; Figure 8 shows a format for the common serial data bus that couples the common control of the broadband network unit to the UVG cards; Figure 9A illustrates the format of a downstream channel for communication from the broadband network unit of the system to UVG cards; Figure 9B illustrates the format of an upstream channel for communication from UVG cards to the broadband network unit; Figure 9C shows a format for control common to UVG card control messages; > Figure 9D illustrates commands used in the system; Figure 10 shows a procedure for initializing, authenticating and testing a UVG card; Fig. 1 1 shows a loop start state diagram for a UVG card such as illustrated in Fig. 3; Figure 12 shows a complete state diagram for a UVG card such as that illustrated in Figure 3; Figure 12A shows the state machine control diagram for a signaling preprocessing layer for a state machine in accordance with an embodiment of the present invention; Figure 13 shows a configuration for ringing relays, channel test and low access test on a UVG card of the prior art; Figure 14 shows a staging relay, channel test and integrated low access test in combination with a low test resistor according to one embodiment of the present invention; Figure 15 illustrates the correctors used on UVG cards in the system; Figure 16 illustrates the timbre generating circuit used in the system; Figure 17 illustrates the microcontroller, an SRAM and a PROM used in the system; Figure 18 illustrates the TIUA used in the system; Figure 19 illustrates the identification memory, implemented by an EEPROM, used in the system; Figure 20 illustrates the inputs and outputs of the signaling preprocessing state machine in accordance with one embodiment of the present invention and Figure 21 illustrates a data structure for a state in the described system.

BRIEF DESCRIPTION OF THE INVENTION In one embodiment of the present invention, a method for communicating with a voice grade card in a sidewalk fiber telecommunication system is provided. In the method, a frame synchronization signal is provided to the voice grade card, and a frame-based time division multiplexed signal is also provided to the card based on a frame including a frame aerial channel, thirty channels of voice and a control channel. A frame-based time division multiplexed signal that includes an aerial frame channel, a plurality of voice channels and a control channel is transmitted from the card to the telecommunications system. In another embodiment of the present invention, a voice grade card is provided to provide telecommunications services in a sidewalk fiber telecommunications system, the card has means for receiving a frame synchronization signal, means for receiving a signal multiplexed by downstream time division based on frame including a first aerial frame channel, thirty voice channels and one control channel. The card also includes means for transmitting a frame-based time division multiplexed signal including a frame aerial channel, thirty voice channels and a control channel. In addition, a circuit is provided for testing the loop of a voice-grade telecommunications circuit, the circuit includes at least one test relay that connects at least one common test bar to a pair of resistors that are in the configuration of parallel circuit and which connect the relay to a twisted lowering torque having a tip wire and a bell wire, as well as a low test resistor placed in a shunt configuration between said tip wire and said bell wire. In another embodiment of the present invention, a method is provided for testing a ring generator circuit on a voice grade card in a telecommunications system. The test method includes generating a first pulse train signal having a first duty cycle and applying this signal to the buzzer generating circuit, then measuring the DC voltage output of the buzzer generating circuit. In addition, a second pulse train signal having a second duty cycle is applied to the ring generator circuit and the DC voltage output of the ring generator circuit is measured. In order to determine whether the ring generator circuit operates acceptably, the first and second DC voltages are compared to predetermined levels that are known as acceptable. In a further embodiment of the present invention, a ring generator test circuit is provided which includes a means for generating a first pulse train signal having a first duty cycle and a second pulse train signal having a second different duty cycle and means for applying the output of the pulse generating circuit to the buzzer generator and means for measuring an output voltage from the buzzer generating circuit that originates from the application of the first and second train signals of impulses. In another embodiment of the present invention, a method and apparatus for testing a ring generator on a voice grade card in a sidewalk fiber telecommunications system is provided. In the method, a first digital pulse train signal is applied to the ring generator and the ringing frequency of the ring generator circuit is measured. Subsequently, a second pulse train digital signal different to the ring generator is applied and the ringing frequency of the ring generating circuit is measured. Finally, the method is completed by determining whether the first ringing frequency and the second ringing frequency are within acceptable operating limits. The circuit for testing a timbre generator operating in accordance with the above method includes a pulse train generating circuit for generating the first and second pulse train digital signals. Means are provided for applying the output of the pulse generating circuit to the timbre and means for measuring the frequency of an output of the timbre generating circuit in response to the application of the first and second pulse train signals. In still another embodiment of the present invention, a method is provided for controlling telephone line states in a fiber-to-sidewalk telecommunications system having a voice grade card to provide voice telecommunications services. In this method, (i) the output status information is stored for the line states, (ii) a variable representing a number of branches for the states it is stored, (iii) information of the branch condition that includes Signal data, line status and synchronizer information indicating branch conditions is stored. In addition, branch address information is stored and the condition information of the branch is compared to determine if branch conditions have been met. Finally, the step of withdrawing information from subsequent output data and branch address information is carried out when the branch conditions are met. A method for testing a voice grade card in a sidewalk fiber telecommunications system is provided. In this method, a first active value is provided to the card, the first active value and a second active value stored on the card are used to generate a data stream comprising bits. The generated bits are compared with a predetermined bit pattern to determine if the card is working properly. A controllable voice grade card is provided for a sidewalk fiber telecommunications system, the card being controllable by four-byte messages received in a control channel. A method for communicating with a controllable voice grade card in a sidewalk fiber telecommunications system is provided, the method includes receiving a first message with a downstream command code, and transmitting a response message with a code of upstream response, where the response code is equal to the downstream command code plus a hexadecimai value. In one embodiment of the present invention, a method for communicating a control message to a controllable speech grade card is provided, the method is carried out by dividing the control message into a plurality of sub-portions.; placing said message sub-portions in a plurality of frames of a frame-based time division multiplexed signal; sending a plurality of frames of said frame-based time division multiplexed signal to the card and assembling the control message sub-portions to create a control message to control the voice grade card. Also in accordance with the invention, a computer-readable medium comprising a plurality of state data structures used to define a state of a telephone equipment is provided. The data structure for each state includes one or more branch data structure, each branch data structure defining a state transition that the telephone equipment will take after receiving an entry. Each string data structure includes data elements A and B, where A defines bit positions in which the input must have 1s for a state transition to take place, and B defines bit positions in which the input must have Os for the state transition to take place. Finally, the data structure includes a data element that defines the address of the state data structure for the next state of the telephone equipment. In a further embodiment of the present invention, a state machine is provided for a voice grade card used in a sidewalk fiber telecommunications system having a broadband network unit. The state machine includes a signaling preprocessing layer that includes a plurality of branches. The signaling processing layer receives signaling information from the broadband network unit and provides control information. The state machine further includes a main control layer having a plurality of branches, the main control layer receiving outputs from the signaling preprocessing layer and providing control of a plurality of branches in the main control layer to control the operation of the telephone equipment connected to the voice grade card.

DESCRIPTION OF PREFERRED MODALITIES TABLE OF CONTENTS I. Sidewalk fiber systems A. Overview of the system B. Overview of the broadband network unit C. Overview of the universal voice grade card II. Universal Voice Grade Card A. General Overview of Universal Voice Grade Initiation B. Universal Voice Grade Card Authentication C. Universal Voice Grade Card Test 1. Ringer Generator Test 2. Auto TIUA test D. Description, operation and discharge of the state machine E. Two-layer state machine F. Flexible state machine III. Circuit and loop test of the universal voice grade card I. Sidewalk fiber systems A. Overview of the system Figure 1 illustrates the FTTC 1 system comprising a broadband digital terminal (BDT) 100, which is connected by an optical fiber 200 to broadband network units (BNU) 1 10A and 1 10B. The BNUs 1 10A and B each contain an optical receiver and transmitter for receiving signals from and sending signals to the BDT 100, as well as one or more UVG 140 cards that are connected to residences 175 by means of a twisted pair lowering cable. 260. In the residence 175 the indoor twisted pair cable connects the telephone 185 to the twisted pair lowering cable 260. The BDT 100 is connected to telecommunication networks by means of a public switched telecommunications network (PSTN) switch 10, and networks for advanced services such as network 7 of non-synchronized transfer mode (ATM). The FTTC system can be controlled through the use of an element management system (EMS) 150 which is software that runs on a workstation or computer that is connected to the BDT 100. The EMS 150 provides the ability to provide services or equipment, which is to carry out the ability to modify the state of the equipment in the system or provide new services. The EMS 150 can typically be operated locally by an operator at the workstation or PC, or remotely via a connection through the switch 10 of the PSTN or the ATM network 7. The EMS 150 also provides the ability to monitor and control the UVG 140 cards in the NBU 1 10.

Telecommunications systems are based on standards that have been developed over many years and ensure compatibility of equipment from different manufacturers, as well as providing clearly defined and precise specifications for different types of telecommunications services so that these services can be provided throughout geographical boundaries in a network with several generations of analogue and digital telecommunications equipment. For FTTC systems, the specification TA-NWT-000909 of Bellcore, entitled "Generic Requirements and Objectives for Fiber in the Loop Systems ", edition 2, December 1993, provides a comprehensive description of the requirements for FTTC systems, as well as the signaling and transmission requirements for UVG circuits, and is incorporated herein by reference in its entirety.

B. Overview of the broadband network unit A block diagram of the NBU 110A shown in Figure 1 is illustrated in Figure 2. The NBU 1 10A contains a broadband network unit power source (BNUPS) 804 which receives a voltage from an external source in the power supply manifold 848, and can activate terminal equipment through connections made in the 4-drop manifold 856. The BNU 1 10A also contains BNU (BNUCC) common control 800 which it receives signals from the optical fiber 200 in an optical connector 844. The BNUCC 800 contains the circuitry for sending and receiving optical signals, as well as a microprocessor and associated software to communicate with the BDT 100 and control the UVG cards 140. The NBU 100A illustrated in Figure 2 includes four UVG line cards indicated with the Reference characters 140A-140D. The transfer of information between the BNUCC 800 and the UVG 140A-140D cards is provided by a common bar in series indicated in Figure 2 as 882A-D. A common bar communicates between the BNUCC 800 and the associated UVG card. Each UVG card includes three UVG 812 circuits as illustrated in Figure 2. Each UVG 812 circuit provides POTS service to two lines. Figure 3 illustrates in block diagram form the circuits for two of the POTS lines provided by the UVG 140A card. A detailed electrical schematic of the circuitry for these two lines is illustrated in Figures 5A, 5B and 5C, which will be described below. Each UVG 140A-140D card includes an 860A-860D connector respectively to provide POTS service to 6 lines. Figure 15 illustrates in detail a connector 860, which illustrates the signals for the respective terminals in the connector. In addition, terminal connections are also illustrated in Table 4 below. Returning to Figure 4, a functional block diagram of the BNUCC 800 which is part of the broadband network unit 110A is illustrated. As will be appreciated with reference to figures 2 and 4, the BNUCC 800 provides the Interface between the optical output of the broadband digital terminal 100 and the UVG cards. As indicated above, the input to the UVG cards is in time-division multiplexed signal (TDM) format. Referring to Figure 4, which is a functional block diagram of the BNUCC 800, the BNUCC 800 includes circuitry for converting optical TDM signals into electrical TDM signals that are provided to the UVG 140A-140D cards. This starts with the BDT 100 and the fiber connection via fiber optic 200, a single fiber connection carrying synchronized digital hierarchy ("SDH") ATM data. These SDH-type data are intercepted in the BNUCC 800 by the bidirectional lenses (BIDI) 401. The BIDI 404 convert the optical signal received on the fiber 200 into an electrical signal of 155 megahertz (which are ATM data type SDH). The SDH type ATM signals are provided to the BNUA 402. Initially, the first block in which the SDH type ATM signals are processed is the SDH 403 type frame former, which shuts off the 155 megahertz input signal for the box formation so that you can synchronize and determine where the data is and where the different components of the SDH type box format are. Once this occurs, the tables are delineated with respect to the location of the message formation bytes and all the data. The frame former 403 stores both the input and output data to the SDH type stream, to provide communication to and from the UVG 140-140D cards. The cross-connection box in TIUI 404 also works in the reverse direction to properly direct upstream information (from UVG cards to BIDI 401 lenses to place data in the correct DSO of the SDH type box. TIUI 404 includes a cross-connection table that is programmed by the 405 microprocessor to direct the appropriate DSOs from the SDH type stream to the UVG cards 140A-140D. This corresponds to the 4 megahertz interface as described in figure 8 and to the frame format interface between the BNUCC800 and the cards UVG The microprocessor 405 programs those cross-connections of the messages it receives from the BDT100 on the same SDH-type link in a different section of the frame. MO The power supply interface (PSI) 406 is coupled to the microprocessor 405 to monitor the power supply both to know how much energy is being consumed and to know its status in controlling the LEDs and relays 410 and 41 1. This is an interface of slow speed that allows communication to occur between the BNUCC 800 and the 804 power source.

The PSI 406 is also controlled by the 405 microprocessor.

Also included in the BNUCC 800 are several LEDs 408 which are controlled by the microprocessor 405 or the BNUA 402. Test circuit 407 is connected to the test pair 409 of the rear plane connector 860 (FIG. 15) to all UVG cards to allow that the individual test circuitry tests any of the line card lines. With six lines per UVG card, and with four UVG line cards in one BNU, a single set of test circuits in the BNUCC 800 is allowed to test any of the twenty-four twisted pairs by means of test pair 409. The 405 microcontroller it also controls that test circuitry.

Overview of the universal voice grade card The UVG 140A-D card illustrated in Figures 1 and 2 provides POTS service to a number of residences, one of which is indicated by the 175 reference character, served by the NBU 1 10, and can provide this service through a land line interface or loop start / union line interface. Typically, 6 subscriber circuits (POTs lines) are served from each UVG 140A-D card. Referring to Figure 2, the UVG card 140A contains three double line UVG circuits 812 such as that illustrated in Figure 3. Although not shown, the UVG 140B-D cards also include three UVG 812 circuits. The UVG 140 card also provides metal test access to the communications channel formed by the UVG circuit and to the twisted pair lowering cable 260. The detection functions loop, ringer and ringer trip are provided, as is the open-end condition (ground-free start condition) and ringer ground detection. A ring generator is included on each UVG 140A-D card, which is capable of providing 40 V rms on a 5-ring charge (REN). The ring generator circuit 890 is illustrated schematically in FIG. 16 and illustrated in block diagram form in FIG. 3. With reference to FIG. 16, the ring generator circuit 890 is implemented using a Lucent Technology timbre generator microcircuit. designated L7590, with associated electrical components as indicated. The output of the bell generator 890 is provided on line 896. In further reference to Figure 3, the UVG card 140A is shown in block diagram form. In Figure 3, only one UVG circuit 812 is illustrated for reasons of simplicity, however it will be appreciated with reference to Figure 2 that each UVG card includes three UVG 812 circuits. Each UVG card includes a TIU ASIC circuit that provides an interface between the common control of BNUCC800 and the UVG circuits 812. In Figure 3, the TIUA is indicated with reference character 880. A better appreciation of TIUA 880 will be made with reference to Figure 6. Referring to Figure 6, the TIUA 880 comprises a TDM demultiplexer 601 which receives from the BNCC 800 lower TDM data (TDMDD), TDM clock (TDMCLK) and TDM frame synchronization (TDMFS). The TDM demultiplexer 601 outputs the different components of each frame, including parity, separates signaling and data link information (message formation) and error bits. That information is carried both to data link block 602 and to signaling block 603. Lower PCM data flows out through 389 to DSLAC ™ circuits. The signaling information is found one base per line, and in this way there are six signaling lines flowing in the internal state machine 604 and also to the microprocessor interface 605. The data link information also flows in the state machine internal 604 and the μP 605 interface. The data link data is updated every 500 microseconds as described below in the section describing the r, data link information. The data link information comprises four bytes, the command, two bytes of address and one byte of data as Shown in Figure 9C. Two times in a superframe, every four regular frames, a new data link message is received. A portion of the data link message is provided in each frame, and after receiving four of these, a complete message is assembled and presented to both the internal state machine 604 and the interface microprocessor 605. Figure 8 describes a complete table and shows that on channel 31 there is a control number 1 (CTL # 1) and a control number 2 (CTL # 2). For each frame, from frame 1 to 8 of the superframe, a piece of the data link message is associated, be it a command, a high address, a low address or data. The TDM demultiplexer 601 keeps track of which frame it is in, and accumulates the data link message out of four of these submessages and presents it both to the internal state machine 604 and to the microprocessor interface 605. The signaling is updated in each frame and is associated with channels one to six. The TIUA 880 is configured such that the UVG line card can be controlled either by the internal state machine 604 or by the use of the microcontroller 884 in conjunction with the TIUA 880. The control terminal determines which of the two controls the remaining part in the correct time segments to create the upstream frame illustrated in figure 8. Finally, the PWM bell 609 creates a modulated width pulse signal which is an input (inaudible) to the ring generator 890. The The output signal that comes from the ring PWM is a 20-hertz signal that describes a trapezoid and feeds it into the ring generator 890 that creates a high-voltage signal that represents that pulse width-modulated signal. The information that is provided to the TIUA 880 from the BNUCC 800 is provided on the common bar 882A, which is a common bar of four conductors and carries the signals indicated in figure 7 that will be described below. In addition to TIUA 880, each UVG card also includes a microcontroller and SRAM. For the UVG 140A card, these are indicated respectively with the reference characters 884 and 887. The circuit diagrams for the microcontroller 884 and SRAM 887 are illustrated in Figure 17. The microcontroller 884 can be implemented using generally available products such as for example, a Motorola 68HC11 D3 microcontroller which is the device illustrated in Figure 17. Figure 17 also illustrates the SRAM 887 which in this mode is a 32K x 8 SRAM. An SRAM suitable for this purpose is an Integrated Device Technology SRAM called IDT 712565A. Of course, other manufacturer's devices having the indicated source capacity can also be used as a substitute. The TIUA 880 can be implemented using for example a 10K access FPGA as illustrated in Figure 18. The device illustrated in Figure 18 can be purchased from Xilinx Corp., the device being Illustrated in FIG. 18 is an XC 5210 device. The EEPROM used in the line card can be for example a 93C46 device from a provider such as Atmel or SGS Thomson, National Semiconductor, which is illustrated in FIG. 19. Returning to FIG. UVG circuit 812 illustrated in Figure 3, it will be noted that a dual subscriber line sound processing circuit device, indicated with the reference character 900A / B, is coupled to the TIUA 880. The 900A / B device converts the signals PCM received from TIUA 880 in analog signals that are provided to the subscriber line interface circuits indicated as 906A and 906B, which will be described below. The device 900A / B can be implemented using any commercially available circuitry, such as an Advanced Micro Devices microcircuit called Am79c031. Advanced Micro Devices uses the term DSLAC ™ as a trademark for its dual subscriber line sound processing circuit devices. For reasons of convenience, the term DSLAC ™ is used when reference is made to circuit 900A / B. The AM79C031 device of Advanced Micro Devices is described in detail on pages 2-73 to 2-1 16 of its publication No. 09875, rev. G: amendment 10, issued in December 1994, which is incorporated in the present reference manner in its entirety. An alternative design choice for a dual sound line subscriber sound circuit is the Siemens SiCoFi device.

The 900A / B DSLAC ™ uses a simple 4-wire PCM interface for sound and a second 4-wire serial command interface for programming, and SLIC control / status. The TIUA 880 provides all the signals of PCM and control interface, with control and status information available through registers. As illustrated in Figure 5C, the PCM interface consists of the two PCM road signs indicated as PCMUP and PCMDN, a clock of 4,096MHz indicated as PCMCLKBUF, and a frame synchronizer (sync) indicated as PCMFS. The frame sync signal is a frame start indicator, and the 900A / B DSLAC ™ device provides a time slot allocation circuit with interim records to allow full programming capability. The 900A / B DSLAC ™ device also allows up to 7 clock delays in the transmission or reception PCM; used in conjunction with the TSC oriented byte, this allows a programmable bit offset of the PCM in both directions, relative to the SOF marker. All these functions are accessible through the serial data link via the 884 microcontroller and the TIUA 880. A control interface is used for a combination of real-time and non-real-time information. At startup, it is used to configure the internal DSP of the 900A / B DSLAC ™ circuit. During service, it is used to activate and deactivate the appropriate sections of the DSLAC ™ device. During the timbres, it is used to control the control bits to SLIC A and SLIC B.

The control interface consists of four signals: data (bidirectional), clock and selections of two microcircuits-one for each channel. Multiple channels of the DSLAC ™ device can be accessed at a time by activating several CS terminals simultaneously. These terminals are controlled by the microcontroller 884 by means of a register within the TIUA 880. For obvious reasons, only one channel of the DSLAC ™ device can be read at any time. All commands written to the DSLAC ™ device that require entering additional bytes must have those bytes sent as the next bytes N. Any command that expects to see data output from the DSLAC ™ device should see those bytes as the next bytes N on the interface. No more input command bytes will be accepted by the DSLAC ™ device until all N bytes have been issued by the DSLAC ™ device. See the AMD data sheet for a description of the valid DSLAC ™ device commands. Note that not all commands have the additional bytes associated with them. In general, the write commands are at even command values, and the read commands are at a non-command value within the 900A / B circuit of the DSLAC ™ device. The DSLAC ™ device provides 5 general purpose l / O terminals to control SLIC functions. These terminals are accessed through the serial interface. All five terminals can be provided as inputs (from failure to restart) or outputs. The mapping of the C bits of the 900A / B DSLAC ™ device to the input terminals on SLIC A 906A and SLIC B 906B is shown in Table 2. All five terminals are used as outputs.

TABLE 1 DSLAC ™ device control interface The outputs of the 900A B DSLAC ™ device at the inputs to the subscriber line interface circuits 906A and 906B are illustrated in Figures 5A, 5B and 5C. The subscriber line interface circuits 906A and 906B can be implemented using commercially available devices such as the Advanced Micro Devices product called Am7949. The Advanced Micro Devices Am 7949 subscriber line interface circuit is described in detail on pages 1-141 through 1-156 of its publication18507, Rev: A amendment 10, date of issue: December 1994, which it is incorporated herein by reference in its entirety. Circuits 906A and 906B are illustrated in Figures 5A and 5B respectively, each operating with an associated line card access switch indicated as 91 OA and 91 OB respectively to provide POTS service to lines 260A and 260B. Each SLIC provides a constant current battery supply to the subscriber loop, which must be programmed to provide an output of 22mA to a TER of 450O (given the tolerances of the SLIC power supply, this will guarantee a loop current of 20mA ). Each SLIC also performs loop and ringer trip detection, tip and bell polarity inversions, provides ringer relay drivers and provides a battery switching function to allow the use of two different battery voltages. Each UVG 140A-140D card uses two different battery voltages, one for the standby state (free), and one for the active state; this results in a lower total power consumption for the circuit than if only the battery voltage were used. The SLIC also carries out VF coupling from 2 to 4 cables. The reception signal (D-A) is input to a current sum node. { RSN, current gain = 00} , along with a DC feedback voltage that comes from the line drivers. The Vtx of the transmission signal is directly coupled to the transmit amplifier of the DSLAC ™ device. Within each SLIC is a loop current detector, an earth-ground detector and a comparator for the detection of the ringer trip. The output of these detectors is internally combined to form the IDET signal. The active detector is selected by means of the control cables C1-C3, and the cable E1. These cables also determine the status of the ringer relay driver. { status of "ringing", 001.}. , polarity reversal, tip opening or open tip and bell circuits. See table 1.

TABLE 2 SLIC control states -SS The E1 cable selects between a loop detector (measures the sum of current in the tip and ringer cables) and a ground-key detector (measures the current only on the bell cable). Two batteries are provided for the SLIC, one for the hanging conditions (approximately -50Vdc), and the other for the off-hook conditions (approximately -24Vdc). The main reason for having the highest battery voltage in the hanging condition is for compatibility with the mechanized loop test equipment ("MLT") used by the Bell operating companies. In the BNU application as illustrated in figure 1 this requirement does not apply. The switching between the two battery voltages is controlled by the terminal BSW on the SLIC, with a high logic enabling the hanging battery and a low logic enabling the battery off-hook.

The microcontroller 884 controls signals C1, C2, C3 and BSW through the C bits of the 900 A / B DSLAC ™ device. The IDET emission that comes from the SLIC 906A / B will be read by a status register in TIUA 880. There are three relay functions in the UVG circuit; these functions are provided by a Lucent Technology solid state relay indicated in Figures 5A and 5B with the part number 7583 of Lucent Technology, which are detailed in the description of the line card access switches (LCAS) 91 OA and 91 OB. Each SLIC has two integrated relay drivers available. One is controlled by the control bits C1-C3, and is activated when the SLIC is in the status of TIMBRADO (C3C2C1 = 001). The second It has a separate control input to the SLIC. Both drivers are NPN collector transistors essentially open with a diode support 7.2 V zener to ground for protection against the rear EMF of the coils and EMR. Due to polarity error in the output of the ringer relay driver, the bell relay in the LCAS is driven directly from the TIUA 880. The ringer travel circuit is composed of a comparator in the associated SLIC that detects the current through a ring power resistor 100O. It uses a pair of RC networks through the inputs to the I comparator that filter the AC portion of the ring signal. The input of the I comparator (DA) on the most positive side of the ringing source will be more positive than the input (DB) on the more negative side of the ringing source for a hanging line. When the line is off-hook, the voltage in RB voltage of 2.5V to RDC (-2.5V for normal polarity and + 2.5V for polarity) The microcontroller 884 controls signals C1, C2, C3 and BSW through the C bits of the 900 A / B DSLAC ™ device. IDET coming from the SLIC 906A / B will be read by a status register in TIUA 880. There are three relay functions in the UVG circuit, these functions are provided by a Lucent Technology solid state relay indicated in figures 5A and 5B with the part number 7583 of Lucent Technology, which are detailed in the description of the line card access switches (LCAS) 91 OA and 91 OB. Each SLIC has two integrated relay drivers available. One is controlled by the control bits C1-C3, and is activated when the SLIC is in the status of TIMBRADO (C3C2C1 = 001). The second has a separate control input to the SLIC. Both conductors are essentially open collector NPN transistors with a 7.2 V zener diode support to ground for protection against the rear EMF of the EMR coils. Due to the polarity error in the output of the ringer relay driver, the bell relay in the LCAS is driven directly from the TIUA 880. I The ringer travel circuit is composed of a comparator in the associated SLIC that detects the current through a ringing power resistor I 100O. It uses a pair of RC networks through the inputs to the comparator that filter the AC portion of the ring signal. The comparator input (DA) on the most positive side of the ringing source will be more It remains relatively constant and the voltage in DA drops so that the difference of the two voltages reverses the polarity and the output of the comparator changes from high to low. Additional filtering is required to protect against transdifferential losses in the IDET when the on or off ringing is changed; this may require a routine in the software to completely ignore the I DET signal cable for 50msec after the ringing is removed, to allow the energy stored in the line and the timbre to discharge. The ringer travel comparator is automatically switched on and off the circuit by the SLIC, based on the status of the control cables. External components are used in connection with each SLIC to program the output level of the constant current source and also to set the current detection value of the loop current detector. The output level of the constant current source is determined by two resistors RDC1 and RDC2. These resistors are connected between the terminals RSN & DRC on the SLIC. The battery power circuit produces a voltage of 2.5V to RDC. { -2.5V for normal polarity and + 2.5V for polarity 1 inverted} . The output of the current level by the supply circuit is determined by the following ratio: i IFEED = (2.5 * 200) / (RDC1 + RDC2) Making RDC1 and RDC2 both equal to 1.3 1.3 Kohms will provide approximately 22mA of loop current .

A capacitor (CDC) connected to the midpoint of the two RDC resistors controls the speed at which the battery supply circuit reacts to changes in the condition of the loop. { such as during polarity reversals, or when changing from the ringing state to the active state after a ringing trip, when the power supply attempts to change from an open loop condition to a closed loop condition} . According to AMD, this capacitor must be chosen in such a way that the time constant produced by CDC and RDC1 / RDC2 is approximately 1.5 msec. This is equivalent to a 0.27μF capacitor. The travel threshold of the loop detector is established by the resistor Rd. The terminal RD has a current output that is equal to the loop current divided by 292; The internal detector has a threshold set to 1.25 V by an internal reference. The voltage at the RD terminal is therefore equal to the current per Rd: lthre8h / 292) * Rd = 1.25 or Rd = 365 / lthresh A capacitor Cd can be added to provide some delay in hanging time to off hook to switch partially transdifferential losses, and is typically chosen for 0.5 ms of delay. However, no capacitor is used in the TIU RD cable since IDET filtering is provided anywhere.

As will be appreciated with reference to Figure 3 and Figures 5A and I 5B, the 91A and 91 Line Card Access (LCAS) circuits 91 are used respectively to couple SLIC A 906A and SLIC B 906B to subscriber lines 260A and 260B respectively. LCAS 91 OA and 91 OB can be implemented using conventionally available circuitry such as that of AT &T indicated by part number ATTL7583 (shown in schemes of Figures 5A and 5B). There are three functions in the UVG 812 circuit that require relay operations: one is stamped, and the other two are to provide access test access and exit test to the CIRCUIT and the LOW. The circuits LCAS provide all three of these relay functions, plus integrated SLIC protection, current limiting, and thermal shutdown. The LCAS bell relay portion also provides a zero-cross current switching mechanism in the release. This eliminates the need for external circuitry to perform this function, and should serve to minimize impulse noise within the system. Ideally, the ringing should be applied at a zero voltage junction, and removed at a zero current junction. The LCAS satisfies the requirement of zero current shutdown; thanks to the low level of the ringing value used, the ignition of Zero voltage is not as critical as zero current shutdown.

In the discussion state, the LCAS provides approximately 20O of Impedance coupled on the tip and bell cables. This will tend to provide some current limitation for the SLIC in the event of an overvoltage / overcurrent condition in the line. By controlling the order and synchronization of the operation of the control cables to the LCAS, information can be obtained whether to do before breaking or breaking before doing. The UVG card is operated in the break mode before doing. i The LCAS provides several protection functions. The switches will limit the dynamic current to approximately 2.5A during a lightning fast shock and thermally to 250mA during a lower power cross condition. During an extended power crossing, the switches will fully open and enter the thermal shutdown mode. In addition, a diode bridge offers tertiary protection bypassing small overvoltage j conditions to ground and battery and high overvoltage conditions | ground current. The functions of the LCAS are controlled by means of the control cables for input test, output test and ringing. These signals will be driven from a control register in the TIUA ASIC and are common to all six lines of the TIU card; Each LCAS has an integrated transparent latch, and this latch is controlled by six RLYLNSEL signals that come from the TIUA. The following table shows the relationship of the control inputs to the switch states.

TABLE 3 A 918A loss surge protector is used to protect the LCAS 91 OA from excessive voltages. Similarly, the 918B surge protector is used to protect the LCAS 91 OB. A suitable design choice for the loss protection surge protectors 918A and B Teccor P2103 200 V Sidactor. The protective resistor 920A consists of two resistors, one in series with the tipped line (T) 266A and one in series with the timbre line (R) 268A which together form the twisted pair lowering cable 260A. The line power resistors serve to protect the UVG circuit from overvoltages, in particular overvoltages caused by lightning strikes. Thick film or wire wound fuse protection resistors are typically used. A suitable design choice for a line feed resistor in the line feed section 920A is a 50O thick film resistor on a ceramic substrate. As described in figure 3, the line feed section 920B (which has the same structure as 920A) is used for line 260B. A gas tube or carbon block device in place 175 is used in conjunction with the surge protector 918 and the line power section to provide protection against overvoltages. The line supply section 920 has sufficient strength so that in the event of a lightning strike the voltage of the location remains high enough to activate the gas pipe or carbon block in addition to activating the surge protector 918. The connectors of UVG card 860 allow the connection of the UVG card to backplane interconnections 808 that provide connectivity to the BNUCC 800. The backplane interconnections 808 provide connections to a number of signals including data bars containing telecommunication data for subscribers, as well as control information that comes from the BDT 100 or the BNUCC 800 and energy and ground for the UVG card itself.

Table 4 illustrates a typical terminal use for a 3x32 European DIN connector that can be used for the UVG 860 card connector. The 860 connector is also illustrated schematically in Figure 15.

TABLE 4 'I Terminal connections for UVG 860 card connector The superscript 1 (1) above indicates an initial contact termination of first level -: terminal removed. I TIUA 880 can be implemented using a field-programmable access arrangement (FPGA). In the system described here, TIUA 880 is implemented using a Xilinx Corporation FPGA 5210TQ144 microcircuit which is illustrated in Figure 18. Of course, it will be recognized that FPGAs of other manufacturers can be used to carry out the present invention. The following table 5 establishes the signal name in number of terminals and explanatory notes in a description of the signals related to the terminal.

TABLE 5 In Table 5, the BB annotation indicates backplane signals, CD i indicates DSLAC ™ device signals, P indicates processor signals, EE indicates EEPROM signals and M indicates memory signals.

In addition to TIUA 880, a serial PROM, which may be a part of Xilinx Corporation number XC17256, is used in conjunction with programming. This serial PROM is illustrated in Figure 17 and indicated by reference character 880-A. In addition to the signal and power terminals established above in Table 5, the following table 6 indicates the terminals necessary for programming together with the signal name. The table also includes a description of the programming function that is carried out, as well as the terminal is in an input / output or in both.

TABLE 6 The communications between BNUCC 800 and its associated UVG 140A card are provided on the common bar 882A as illustrated in figures 2 and 3. With reference to figure 3, the communication channel includes in a TDM current below the first cable indicated information by TDMDD, providing data for the six subscriber lines. The second channel, the common upstream TDM serial bus, is indicated by TDMDU, contains data of the six subscriber line circuits in control and question inserts for the i BNUCC800. This common bar has three states when TIUA 880 does not actively drive data over the common bar. This allows other cards to share this common bar. Then, a clock signal is provided to TIUA 880 on the common bar indicated TDMCLK, this being the clock of the main system operating at 4,096 MHz. Finally, a sync signal is provided to TIUA 880 by means of the common bar indicated TDMFS - This signal provides synchronization between TIUA 880 for communication in the upper and lower common bars. This signal has a code for frame sync and a different code for sync for superframe. In Figure 7 the downstream frame sync is indicated with the reference character 936. The superframe will occur every eight frames. In Figure 7 the sync of the superframe is indicated by the reference character 938. This signal is in the high state when a sync frame code is not being transmitted. The frame sync code is ($ EA) which is 11101010, and the superframe code is ($ CC), which is 1100. As used here, $ indicates hexadecimal. When a correct frame code is received the next bit after the last bit of the frame code is taken as the first bit of the next frame. Although in Figure 7 the words upstream and downstream are shown as being in sync, the upstream and downstream data may be out of sync, by using the derived parameter in the TIUA. The derivation governs the number of clock cycles that have been delayed upstream. The ability to have a time synchronization derivation with bit resolution between the upstream and downstream frames offers several advantages both by minimizing the delay of transmission of voice signals as well as by reducing the amount of memory needed to store information frames . Being able to provide a wide derivation of bits, it is possible to access information as soon as it arrives without regulating the complete picture. The ability to create bit resolution to decrease delays in other portions of the system including DSLAC ™ devices can be achieved by placing a large byte register in TIUA 880 that can be programmed for a delay corresponding to an integer number of clock cycles, providing essentially a fine time control that can be used in conjunction with the byte time regulation control found in commercially available DSLACs.

Common control interface The BNUCC 800 is connected to TIUA 880 through a common serial TDM busbar. This common bar is designed to support a maximum of six PTOS interfaces. The serial TDM bar of the BNU consists of a common 4.096 MHz clock provided on TDMCLK, a common 125-us box sync provided on TDMFS, an individual upstream TDM data provided on TDMDU and a single downstream TDM data provided on TDMDD. Referring to Figure 8, the frame sync marks the first bit of a frame (the MSB of the first time segment). Each frame consists of 64 DSO's (or time segments) and is grouped into 32 channels (2 DSO's I per channel). The first DSO in a channel is the TDM PCM data and the second DSO is the associated bit orientation signaling. The first channel (# 00) is reserved for the OH box and the last channel (# 31) is reserved for the control. The OH channel is used to monitor the performance of the link. The second DSO (sig DSO) is used to verify the parity of the common bar. It contains the result of a cumulative XOR for each byte in the table. The first byte is inverted, which is equivalent to starting with all ones instead of all zeros. There are two control time segments: CTL # 1 and CTL # 2. CTL # 1 dsO (@ channel # 31 DSO data) is used to perform a slow access protocol to the TIUA hardware. CTL # 2 DSO (@ channel # 31 sig DSO) is reserved except for the two higher MSbs. The MSb indicates whether an upstream parity error has occurred. It is one if an error occurred in the last frame. The second MSb indicates an AIS error when it is high (in-one). The third MSb incurs a power error when high (in-one). This will be put in a register for the local processor to read along with the parity error upstream. The data upstream carries only the message and the parity error bit. The CTL1 channel uses the 1-ms superframe dimension to create two 4-byte messages per superframe for a simple protocol of Control / response between BNUCC 800 and TIU. Referring to Fig. 8, a single frame is illustrated, indicated with reference character 931. The downstream data channel is also illustrated.

TDMDD indicated with the reference number 932, the TDMFS sync channel denoted 934 and the clock (TDMCLK) at 940. Within table 931 is included, As mentioned above, channel 31 includes two control time segments CTL # 1 and CTL # 2 indicated in figure 8 with the reference characters 960 and 962. Table 931 includes channels 0 to 31, in the figure 8 channel 0 indicating itself with the reference characters 950 and 952. Similarly, channel 1 is indicated with the reference characters 954 and 956. With reference to the , Figure 9A, downstream channel 31 is illustrated, and it will be appreciated that DS0-1 can be used for a multi-frame message to provide control signals to TIUA 880. Similarly, with reference to Figure 9B, the channel 31 is also used for a multi-frame message in the upstream direction. The format for an upstream control message is illustrated in Figure 9c. As used herein, the eight frames illustrated in FIG. 9C are stamped in a superframe. An example of commands and addresses for upstream and downstream messages is illustrated in Figure 9D.

One advantage of commands and directions for upstream and downstream messages is that they can be implemented in a software-based line card in which a microprocessor is present and 1 »external memory, but they are designed in such a way that a simple machine based on hardware (e.g. TIUA 880). This is achieved by using short codes as illustrated in Figure 9D. The elimination of the microprocessor and the associated memory would have obvious cost advantages. In a preferred embodiment, downstream messages contain a command byte to indicate the action to be taken, and are generated 'lO answers upstream using the downstream command byte plus the hexadecimal value of $ 80. Upstream messages that do not require data transmission from the card repeat the data sent downstream to allow BNUCC 800 to confirm that the messages were received properly. , 15 II. Initialization of the universal voice grade card A. Overview of the initialization of the universal voice degree. The basic operation of the UVG 140 card can be understood as from Figure 10, which illustrates the steps that can occur when a UVG 140 card is installed in BNU 110A. After installation, a step A0 is carried out to check parity bytes in signals coming from the UVG 140 card. An A4 parity byte test is carried out by BNUCC 800 to determine if the parity bytes are correct . The parity byte is calculated through a cumulative xor for each byte in the table. The first byte is inverted, which is equivalent to starting with all ones instead of all zeros. An example of this is that if in a certain table all the bytes in the table are zero except for the parity of the previous table, the parity for this table will be the parity of the previous inverted table. This means that if the given parity was (1001 1001) the new parity would be (01 100110). To better describe this procedure, a list of the calculated parity against the data in a table is shown below. (All values are in hexadecimal and the table is O assumed to start at the first data value). Data: 01: 10: FF: AA. Parity: FE: EE: 1 1: BB. If they are correct, the A8 card identification takes place, requesting the UVG 140 type and revision card which is typically stored in 5 EEPROM 886. In case the A4 parity byte test fails, another indication of check parity bytes A0, since it may be the case that the UVG 140 card has not yet been inserted in the BNU 1 10 yet, or has not been activated. After the A8 card identification, a step of 0 authentication may occur, whereby a key or cryptographic function is used to generate a signature for the card that identifies the card as an authentic product that is known to satisfy the parameters of reliability and quality necessary. The A8 authentication occurs locally to the UVG 140 card.

The results of the A8 authentication are transmitted to the BNUCC 800 and can also be transmitted to the BDT 100. An authentic card test A16 is carried out to determine if the results of the A8 authentication are correct, which is effectively equivalent to verifying the signature of the card. The BNUCC 800 or the BDT 100 can determine in the authentic card test A16 that the card has not passed A17 authentication, or if the card is determined to be authentic the system will move to A20 card self-test. The A20 card self-test may include the download of a self-test from the BNUCC 800 or BDT 100 to the TIUA 880, which initiates a self-test procedure to ensure the integrity of the circuitry, the connections to the printed circuit board of the UVG 140 card and the functionality of some or all of the circuitry and components on the UVG 140 card. After self-test A20, a self-test pass test A24 is carried out either on the BNUCC 800 or the BDT 100. This test can be It is simple to compare a short test result of few bytes with an expected test result that is stored in the BNUCC 800 or BDT 100, or the comparison of a long sequence of several hundred bytes generated by the self-test with a long sequence stored. In any modality, the final result will be a determination that the UVG card is or is not working properly. In case the card is not working well, it is considered that the A20 self-test has failed. If it has been determined that the card works properly, it will proceed to download the A28 software.

After connection, activation or restart, the UVG card 140 will have a sufficient function to interpret the following data link messages: read memory, write memory, start, establish upstream derivation, unlock and restart. The following table 6A illustrates the data link function codes.

TABLE 6A Data link function codes #Define cD1 FuncNil 0 / * Null function * / #Define cD1 FuncRead 1 / * Read memory * / #Define cD1 FuncWrite 2 Write memory * / #Define cD1 FuncOffset 3 Set upstream derivation / #Define cD1 FuncGo 4 / * Activate code loaded * / #Define cD1 FuncTesLpbk 0x22 / * Test loop * / #Define cD1 FuncUnlock 0x55 / * Unlock message interface * / #Definit cD1 UnlockAddr 0x1234 / * Address value to unlock * / #Define cD1 UnlockData 0x77 / * Data value to unlock * / #Define cD1 FuncReset 0x69 / * Command for restart * / #Definit cD1 ResetAddr 0x5ab3 / * Address value for restart * / #Define cD1 ResetData 0x96 / * Data value for restart * / #Define cD1 ReplyBit 0x80 / * Join this bit to indicate r * / #if O #Define cTiu Load Add r 0x1600 / * Where the downloaded TIU code goes * / #else #Define cTiuLoadAddr 0x2000 / * Where the downloaded TIU code goes * / #endif In a microcontroller / software mechanization as described here, this function is implemented by software loaded at the time of manufacture, in a non-volatile memory (eg, a programmable ROM once) in the microcontroller microcircuit 884, and by hardware (fixed logic or programmable from an integrated non-volatile memory). In hardware mechanization, this would be provided by fixed logic or by programmable logic loaded from an integrated non-volatile memory. After the connection, activation or restart, the data link to the UVG card deactivates all functions except restart and unlock. This protects against false data link actions during transient insertion and start conditions. The UVG 140 card includes a non-volatile identification memory U19 accessible by means of registers t * mapped in the address space accessible by means of the data link to the UVG card. Current machining maps serial access terminals (selection of microcircuit, serial clock, serial input and serial output) of memory device U19 directly in bits in TIUA registers 880; TIUA records (address scale $ 8xxx) are accessible through the UVG and the functions of reading memory and writing memory. ? The BNUCC 800 provides a UVG card activity detector, which detects transitions in the upstream TDM common bar (TDMDU) separately for each UVG card slot in the BNU. When the BNUCC 800 software observes a period of sufficient activity in a bar upstream of the UVG card, it assumes a UVG card is present, and card monitoring begins. The BNUCC 800 software initiates a unlock message in the data link. This provides a distinctive pattern (1 in a probability of 2? 32 of false indication assuming a random content in all message fields) that instructs the UVG card to allow all types of operation of subsequent data link. The BNUCC software sends a message to establish upstream derivation in the data link. This allows the UVG card to establish its PCM bus branch upstream, which is necessary for the data link message formation of the upstream UVG card to work properly. The BNUCC 800 software reads the identification of the UVG card by means of the data link access described above to the serial identification memory U 19. The BNUCC 800 software can interpret the identification of the UVG card and the authentication directly, or you can send these responsibilities to the BDT 100, or you can duplicate the effort or combine between BNUCC 800 and BDT 100. The BNUCC 800 or BDT software selects a suitable software image, or a programmable state machine control, for the specific type and revision of the hardware of the indicated UVG card and removed in the previous step in which the U19 memory of the UVG identification card was read. BNUCC 800 obtains this image, either from its own non-volatile memory, or by pieces from its communication link with the BDT 100 and sends this image byte by byte to the UVG card, using commands to write memory on the data link. of UVG card. The integrity of reception of the image by the UVG card can be verified by observing the response messages of the writing memory returned by the UVG card, and comparing them with the expected sequence of addresses. This step provides an initial and rapid identification of large faults in the microcontroller or hardware of the UVG card.

The integrity of the reception of the image by the UVG card can be further verified by carrying out a sequence of read memory messages to the card, observing the returned responses and comparing them with the values in each direction of the image. This step can provide an indication of faults in the memory of the UVG card, particularly troubleshooting. The BNUCC 800 software sends a start message to the card UVG For the microcontroller machining described here, the address field of the start message contains an address to which the microcontroller of the UVG card goes, to start the downloaded software. For a state machine implementation, this could contain a state machine start address or code. The BNUCC 800 software sends a unlock message. This unlocks the data link for the running software or the state machine. The BNUCC 800 software sends a message to establish upstream derivation. This establishes the upstream derivation for the running software or the state machine. The BNUCC 800 software sends provisional information using write memory data link commands to the pseudo records area located on the $ 9xxx scale. The BNUCC 800 software establishes force-state controls per line in the provisioning information using the previously described mechanism to establish each line-state machine running in the appropriate initial state. After receiving the provisioning or service, BDT 100 Software Status Changes, BNUCC 800 may from time to time establish strength-by-line controls at new values (suitable conditions for out-of-service or in-service conditions).

B. Authentication of the universal voice grade card The A16 card authentication of the UVG 140 card can be based on one or several well-known encryption techniques. To use these encryption techniques, a secret key is stored on the UVG 140 card, and typically within the TIUA 880. After requesting authentication by the BDT 100 or the BNUCC 800, the secret wire is used to calculate a signature, since either by using a one-way mathematical function whose inverse is difficult to copy, or by using an initialization key generated by BDT 100 or BNUCC 800. The signature can be calculated within TIUA 880, microcontroller 884 or a combination of these devices. The signature is the result that is sent to the BDT 100 or BNUCC 800 for the authentic card test A16. Cryptographic techniques have been extensively investigated and well understood by those skilled in the art. The article by James L. Massey entitled "An Introduction to Contemporary Cyptology", and published in Proceedings of the IEEE, vol. 76, no. 5, May 1988, describes a number of cryptographic techniques, as does Federal Information Processing Standards Publication 186, Digital Signature Standard (DSS). The following US patents also describe cryptographic techniques: US patent. 5,231, 668 by Kravitz entitled "Digital Signature Algorithm"; US patent 4,200,770 by Hellman et al., Entitled "Cryptographic Apparatus and Method", issued April 29, 1980; patent E.U. 4,218,582 by Hellman et al., Entitled "Public Key Cryptographic Apparatus and Method, "issued August 19, 1980; U.S. Patent 4,405,829 by Rivest et al., Entitled" Cryptographic Communications System and Method, "issued on September 20, 1983; and U.S. Patent 4,424,414 by Hellman and others., Entitled "Exponentiation Cryptographic Apparatus and Method", issued on January 3, 1984. The aforementioned article and the US patents. all are incorporated by reference in the present. Although the key inside the UVG 140 card can be a stored secret key or a secret key sent through a secure medium, the The key may actually be the result of a self-test or secret function contained within TIUA 880. In this case, cryptographic methods can be used to calculate and transmit a signature to the BNUCC 800 or BDT 100, but originate as part of the card self-test. TO 20. The authentication is not limited to a particular modality, but which can be a combination of the self-test and a cryptographic technique. Similarly, the A20 card self-test can be considered an A12 card authentication when the self-test includes a function that serves as a key. In this alternative embodiment, the authentication steps A12 and A20 card self-test shown in FIG. 10 are combined, same as the authentic A16 card test and the A20 self-test pass test. Failure to pass any of these combined tests results in a state that is the combination of authentication not passed A17 and self-test not passed A21.

C. Universal Voice Grade Card Test 1. Ringer Generator Test Since the 890 ringer generator is a critical component of the UVG 140 card, an individual test can be used to determine that it is functioning properly. In one mode of the generator test a constant duty cycle pulse train is applied as the digital pulse train signal 892, the result being a constant DC voltage output as the ring voltage signal 896. In this In this embodiment, at least two different constant duty cycle pulse trains, generated by circuitry at TIUA 880, are applied to ring generator 890, the result being two different CD voltages that appear as the ring voltage signal 896. The test circuitry in the BNUCC 800 looks for these two levels of DC voltage. This test can be used to verify that the buzzer is working correctly. The test circuitry for measuring DC voltage levels is well known to those skilled in the art. In alternative form, the variable tested may be the frequency of the timbres instead of the voltage amplitude. This method has several advantages. The hardware for this type of test is retained for the current circuit, which is simple and is already adapted to the common control card. The change in TIUA is simpler than changing the amplitude method. To support this type, this type of TIUA test will have the potential for ring frequency programming. The generator will be able to change from 20 Hz to other frequencies. The common control program will be able to confirm that the predetermined frequency sequence is being followed, or that TIUA responds correctly to the frequency controls. The ring generator will be tested to correctly generate several frequencies and potentially different pulse widths. If the timbre generator circuit is working correctly, it will be able to generate all the expected frequencies. 2. Self-test of TIU A The following method provides in-system testing for valid and operational UVG cards. The basic concept for this scheme is that BDT 100 sends a link message for the transmission of data to BNUCC 800, which includes a seed value. The BNUCC 800 then sends this seed to, for example, the line card 140A. The seed is used point with a seed incorporated as the starting point of a linear feedback change recorder (LFSR). The output of the LFSR will then cover a subset of the TIUA scrutiny string. The subscriber apparatus is chosen to avoid conflicts with BNUCC800 communications and line service functionality. The circuit of the chosen subscriber apparatus is timed N times to generate a next state of the circuit. This next state is then sent upstream in its entirety to BNUCC 800 through the message portion of the BNUCCdOO-line card interface. TIUA 880 in turn sends this data stream to BDT 100 via the link for data transmission. The step where TIUA 880 generates internal following state based on LFSR can be repeated a number of times to generate a sufficiently long data stream from TIUA 880 to provide an acceptable coverage. The method used by BDT 100 to verify the data stream generated in this way is flexible. It may consist of verifying the total bit stream or a non-linear transformation of the data against a look-up table stored in the memory. This method allows the verification table to be updated and / or expanded at any time during the life of the product, since it is kept in the program, and the LFSR in the TIUA with the logic is entirely deterministic.

D. Description, Operation, and Discharge of the Status Magnet Description and Operation of the Status Magnet The status machine in each UVG line card provides control functionality for each of the subscriber circuits 812 on the UVG 140 card. As noted above, the state machine for a line card can be implemented using an internal state machine 604 in TIUA 880, or by the combination of the μp interface 605 and the microcontroller 884 (FIG. 3). The state machine in a given UVG card 140 can control six subscriber circuits, as is achieved in three dual line UVG circuits 812. The state machine interprets the signaling coming from the PSTN switch 10, and controls the circuit subscriber to provide ringers, and monitor the subscriber line through the tip terminal 266 and the ring terminal 268 to determine when the telephone 185 is hung and unhooked. The state machine uses information from the switch PSTN 10 together with the telephone state 185 to properly configure the subscriber circuit for each state and to go from one state to another. Figure 1 1 illustrates the different states that are used in the ship start UVG circuits, in which the signaling by closing the subscriber circuit through the formation of a closed circuit between, for example, the terminal of tip 266A and bell terminal 268A. In the figures 1 1 and 12, text in uppercase letters in the states indicates received signaling information. Figure 12 illustrates the states that are used in a ground-start UVG circuit, in which ground is applied to the tip terminal 266A or the bell terminal 268A as a signaling method. In the figure 12, dotted lines represent ground start mode information. Referring to FIG. 12, the downed state of energy of BO is the initial state when the subscriber circuit has been put in the power down mode by the microcontroller 884. This state may be the result of the subscriber circuit not has been provided or activated yet, or by a failure or problem of power supply in BNU 1 10. The free start-to-ground state occurs only when the subscriber circuit is in a ground-to-ground circuit, and it is the delinquent state when the circuit is operational, but there is no activity on the subscriber line, which corresponds to no ring since the telephone handset 185 is being hung.

The fundamental state of the bell B6 occurs only when the subscriber circuit is a ground-to-ground circuit and corresponds to the bell terminal 268 that is being grounded. This state reflects the fact that the subscriber is requesting the dial tone to make a call. The standby state of four is the nominal state for the ship start circuits when the telephone 185 is hung and is not calling. The off-hook state B12 occurs when the telephone handset 185 is in the off-hook position, due to the fact that the subscriber is initiating a call, or why a call has arrived as indicated by the ringing, and the subscriber has answered the call. The next disconnection state B16 typically indicates that the other user in a hung communication places the telephone handset of that user's telephone in a suspended position. The signal of disconnection front is particularly useful to answer machines, modem and fax machines since it indicates to that equipment that the communication has finished. The hung state B8 occurs when the subscriber has returned the telephone handset to the hung position, but before the subscriber circuit is placed in the waiting state of four. The hung state may also occur as part of the pulse dialing, in which the dialing pulses are formed by hanging signals from the dialing circuit of the telephone 185. Similarly, a flash-hook signal is communicated to the switch of PSTN by hanging status.

In the bell state B20, the ring voltage 896 is being applied to the line by the solid state relays 910, causing the telephone fc 185 to call. The B24 release status occurs when the line to is in a state of ringing B20 and is being signaled to remove the ringing voltage 896. This may be because a ringing trigger has occurred (indicating that the ringing user has answered the line), there is a waiting period in the ringing sequence corresponding to the normal ringing tone, or a system failure has occurred that has caused the system intervene to eliminate the ringer to avoid it being in a constant ringing mode. The ringer release state B24 also provides a period of 25 ms (half a bell cycle), during which time the ring voltage 896 remains removed by the solid state relays 910.

The SLIC 906 can be reconnected to the subscriber circuit by the status relay ^ 15 solid after this period of 25 ms in the release status of bell B24 The silent status of ring B28 represents the silence interval between ring signals. Typically, the ring rate is 2 seconds on and 4 seconds off. If the subscriber circuit is in the silent ringer state for more than 5 seconds, the user who is supposed to call hanged is assumed, and that for the ship's start circuit, the subscriber circuit must return to the standby state B4. For ground start circuit, the system will return to ground free state B1.

The circuit state variables and the signaling they provide are defined in table 7. From this table it can be seen that the signaling is generated in the upstream direction (towards the PSTN 10), and that the control signals control the solid state relays implemented by LCAS A (91 OA) and LCAS B (91 OB), the ring generator 890, the DSLAC ™ 900 A B device, and SLIC and 906A and 906B circuits. Tables 7 to 17 provide detailed descriptions of the variable, condition and status value for each of the state variables for each of the states shown in Figures 11 and 12. Table 18 gives the transition signaling conditions of state and the transitions that occur. The state machine is completely downloadable from BNUCC 800. TABLE 7 Variables and definitions of circuit status Definition of UPSIG circuit state variables Upstream ABCD signaling message that the on-line circuit must be sending SLIC bits State in which SLIC must / can be set for this state Select Battery status (ie, suspended battery or off-hook battery) LCAS Bits State that the LCAS control bits should be set for this state RING EN Ringer generator status BUSY LED BUSY status LED (high / low not yet defined) Device Power up / down: sends commands over the common DSLAC ™ bar in DNSIG series (valid) Valid downstream ABCD signaling messages that the on-line circuit must receive IDET Expected indication of the SLIC IDET terminal. [for example, hanging / off-hook] TABLE 8 Description of low energy status or not equipped Status variable Condition UPSIG value Open loop [ABCD = 01011 SLIC bits OPEN CIRCUIT [C3C2C1 = 000] Select battery -48V [B2EN = 1] LCAS Bits Free [TESTIN = 0, TESTOUT = 0, RING = 0,] RING ON OFF [RNG EN * = 11 BUSY LED OFF DSLAC device I M Low power [Serial data link command DNSIG (Valid) Neglect I DET Ignore TABLE 9 Description of GS free status Status variable Condition UPSIG value Open loop [ABCD = 01011 SLIC bits Open tip [C3C2C1 = 0001 Select battery -48V [B2EN = 1] LCAS bits Free [TESTIN = 0, TESTOUT = 0, RING = 0.1 RING IN OFF [RNG IN * = 11 BUSY LED OFF Device DSLAC IM Low power [Serial data link command DNSIG (Valid) LCFO, LCF, RNG I DET To ground, no bells TABLE 10 Description of the fundamental state of the timbre Status variable Condition UPSIG value To earth, with timbres [ABCD = 0101] SLIC bits Open tip [C3C2C1 = 000] Select battery -48V [B2EN = 1] LCAS Bits Free [TESTIN = 0, TESTOUT = 0, RING = 0,] RING ON OFF [RNG IN * = 1] BUSY LED OFF DSLAC device I M Low power [Serial data link command] DNSIG (Valid) LCFO, LCF I DET Ignore TABLE 11 Standby status Status variable Condition UPSIG value Open loop [ABCD = 01011 SLIC bits Standby [C3C2C1 = 0001 Select battery -48V [B2EN = 1] LCAS bits Free [TESTIN = 0, TESTOUT = 0, RING = 0.1 RING IN OFF [RNG ON * = 1] BUSY LED OFF DSLAC device, M Low power [Serial data link command] DNSIG (Valid) Neglect. { LCFO only for GS lines} I DET Colorado 1If the line is provided for full-time transmission in hung state, then the DSLAC ™ device must be in the high power mode in the standby state.

TABLE 12 Description of the status in off-hook position [conversation! Status variable Condition UPSIG value Closed loop [ABCD = 0101] SLIC bits ACTIVE / INVERTED [C3C2C1 = 0001 Select battery -24V rB2EN = 11 Bits of LCAS Free [TESTIN = 0, TESTOUT = 0, RING = 0,] RING IN OFF [RNG ON * = 1] BUSY LED ON DSLAC IM device High energy [Serial data link command] DNSIG (Valid) LCFO, LCF, RLCF I DET Off-hook TABLE 13 Description of the status in hanging position Status variable Condition Value UPSIG Open loop [ABCD = 0101] Bitios of SLIC OPEN CIRCUIT [C3C2C1 = 000] Select battery -24V [B2EN = 11 Bits of LCAS Free [TESTIN = 0, TESTOUT = 0, RING = 0,] RING ON OFF [RNG ON * = 1] BUSY LED OFF Device DSLAC IM Low power [Data link command in seriel DNSIG (Valid) LCFO, LCF, RLCF I DET Hung TABLE 14 Description of the status in disconnected position Status variable Condition Value UPSIG Open loop GABCD = OIOH Bit of SLIC OPEN CIRCUIT [C3C2C1 = 000] Select battery -48V [B2EN = 1] LCAS bits Free [TESTIN = 0, TESTOUT = 0, RING = 0.1 RING ON OFF [RNG_EN * = 1] BUSY LED OFF DSLAC device I Low power [Data link command serial] DNSIG (Valid) LCFO, LCF I DET Hang The UPSIG bits should indicate that the loop is closed, even if the line must be indicating a hanging condition.

TABLE 15 Description of the status in the ring position Status variable Condition UPSIG value Open loop [ABCD = 0101] SLIC bits Calling [C3C2C1 = 000] Select battery -48V [B2EN = 1] LCAS bits Free [TESTIN = 0, TESTOUT = 0, RING = 0,] RING ON OFF [RNG ON * = 11 BUSY LED OFF Device DSLAC IM Low power [Serial data link command] DNSIG (Valid) LCFO, LCF, RNG I DET Hung TABLE 16 Description of the ringer release status Status variable Condition UPSIG value Open loop [ABCD = 0101] Active SLIC bits [C3C2C1 = 000] Select battery -24V [B2EN = 1] LCAS bits All off [TESTIN = 0, TESTOUT = 0, RING = 0,] RING ON OFF [RNG ON * = 11 BUSY LED ON / OFF ON or OFF, depending on the condition of UPSIG DSLAC device, M Low power [Serial data link command] DNSIG (Valid) LCFO, LCF, RNG -RNG would be received only during a ring train I DET Suspend / Ignore TABLE 17 Description of status silently by rings Status variable Condition UPSIG value Open loop [ABCD = 01011 SLIC bits OPEN CIRCUIT [C3C2C1 = 0001 Select battery -24V [B2EN = 1] LCAS bits Free [TESTIN = 0, TESTOUT = 0, RING = 0,] RING IN ON [RNG IN * = 1] BUSY LED OFF Device DSLAC IM Energy low / high1 [Serial data link command] DNSIG (Valid) LCFO, LCF, RNG I DET Hung2 1If the line is provided for transmissions in hanging position, then the DSLAC ™ device must be in high power mode in the silent state by ringing. 2 Even when the line leaves the ringer state due to a ring train, the conditions imposed by the circuit during the ringer release state may result in the I DET terminal providing a hang indication when it enters the state of silence by stamps. In the case of a ring train, this indication must change to the off-hook position in a short time.

TABLE 18 Transitions and state transition signaling conditions Status condition signaling Transition transition Next status = Low power or no DNSIG = free LCF equipped DNSIG = LCFO Next status = GS free Next status = ring basis No change; remains in state I DET = Base of free GS stamps Next status = Free of GS DNSIG = LCFO calling DNSIG = RNG Next status = in DNSIG = LCF wait (this will usually be followed by a ring code) Remain on base of IDET ring - Base Returns to the free status of GS. supposed Ringer base I DET = No base for a ringer abortion ringing in progress DNSIG = LCF Next status = off-hook Next status = off-hook Stands on hold I DET = Off-hook Next status = DNSIG = LCF calling Hold DNSIG = RNG Ignore DNSIG = RLCF Next status = DNSIG = LCFO free status of GS [only GS lines; ignore for the LS line] TABLE 18 (CONTINUED) Condition of State signaling Transition transition Remains in common state Next status = I DET = Off-hook hanging Puts SLIC in mode Off-hook I DET = Hung ACTIVE; [conversation] DNSIG = LCF DNSIG = RNG remains in DNSIG = RLCF common status Ignore puts SLIC in REVERSE ACTIVE Mode = remains in common state DNSIG = LCFO Next status = front disconnect Remains in common state Next status = disconnected IDET = hung IDET = off-hook Put SLIC in ACTIVE mode; DNSIG = LCF remains in common state DNSIG = RNG Next state DNSIG = RCLF Equal calling Hanging Puts SLIC in REVERSE ACTIVE mode; DNSIG = LCFO remains in common state Next status: Time out of 2 free of GS seconds [only GS lines; ignore this for LF lines] Next status = on hold TABLE 18 (CONTINUED) and. Two layer state flaw In one embodiment of the present invention the state machine is divided into two layers: a signaling preprocessing layer, and a main control layer. The two layers are effectively independent state machines, coupled by minimal information; the signaling preprocessing layer accepts TR-303 signaling from the digital transmission facility at a 3ms interval, and sends a signaling code of f R-NWT-000303 conditioned and augmented to the main control layer. The increase of the signaling code tR-NWT-000303 includes an additional code status to indicate the start of the connection line conditioning (in response to some failure of the transmission facility). The signaling preprocessing state machine 2001 (Figure 20) conditions the incoming telephony signaling states, provides this signaling conditioned to the main state machine, and maintains a series of alarm conditions per line. The alarm conditions can be recovered as complementary outputs from the 2001 state machine to monitor the equipment and systems, to signal conditioning conditioning and alarm processing follow the requirements established in TR-NWT-000303 Bellcore in combination with Additional information of the specifications of TR-NWT-00057, TR-TSY-000008 and TA-NWT-000909, Beilcore each of which is hereby incorporated by reference in its entirety.

The associated signaling of each line arrives, by standards of TR-NWT-000303, at an interval of 3ms. The incoming signaling for a given line can be referred to as Sigln. Note that signal processing processing for multiple lines per unit can be impiemented in Hardware by applying an individual shared state machine control to receive and issue status information, which are connected to the control in a rotating time interval succession. The implementation described here is in programs that, for reasons of runtime efficiency, instantly give a different code for each line, by means of a macro-spread that distributes parameters the common source code with the number of lines (for example, the variables named L1P.DSIG, L2P.DSIG and consecutive). A hardware implementation can share the control logic to a succession of 6 500 microseconds, producing a service interval of 3ms per line. The incoming signaling is predated through the SiglnMap programmable function table [Sigln] described in Table 19 below to transform the invalid signaling codes for the specific service type, into other signaling codes such as a signal indication of alarm (AIS). This matted signal is referred to herein as DSIG (downstream signaling). In the following example, for normal POTS service, the output goggle follows the decimal equivalent of the input code comment along the ordinate of table 19. In table 19, as well as in other portions of the description, the following acronyms have the indicated meanings: RLCF of fed loopback current note; CFA of carrier wave failure alarm note; CGA of note carrier wave group alarm; of digital signal note DSO, level 0; LCf of fed current loop note; and LCFO open loop current note fed.

TABLE 19 SianlnMapp = or, TOOOO: stamped -R * / 2, / * 0001: undefined * / 2, / * 0010: DSO AIS * / 2, / * 0011: undefined * / 4, / * 0100: RLCF * / 5, / * 0101: LCF * / 2, / * 0110: undefined * / 7, / * 0111: DSO Yellow * / 2, / * 1000: reserved * / 2, / * 1001: reserved * / 2, / * 1010: undefined * / 2, / * 1011: undefined * / 2, / * 1100: undefined * / 2, / * 1101 reserved * / 2, / * 1110 undefined * / 15, / * 1111 LCFO * / The preprocessing state machine 2001 maintains status information within each line, a volatile history memory of the mapped signaling described above. This is maintained in a 5-step change logger, changed once per 3ms signaling interval. The state machine 2001 has individual access to each stage of this volatile memory. These signals are referred to herein as DSM1 (downstream signaling minus 1), DSM2. This signaling history is used to implement the storage requirements for freezing, thawing and validating confirmation of 2 intervals and 4 signal intervals described below. The mapped signaling is also mapped a second time through two programmable frames, each of which represents individual value Boolean functions. These functions (SigThawabie [Sigln] (Table 20 below) and SigThawableWith Yellow [Sigln] (Table 21 below) are provided as inputs for the 2001 preprocessing state machine to control the defrosting of the signaling. illustrate the signaling for operation of normal POTS, 1 denotes TRUE TABLE 20 SignlnMapp = TABLE 21 SigninMap with yellow [1 = The signaling preprocessing state machine 2001 maintains status information on each line, a state recorder denoted as PPState. The modality written in the present requires 7 stages. The signaling preprocessing state machine 2001 also maintains status information on each line through a synchronizer (PPTimer) which can be set by the output function of the state machine, with decrements once every 3ms (stopping after decreasing to 0), and which can be tested for zero / non-zero values by the control function of the state machine. An individual signal, InFacRed, is applied across all lines, and indicates that the incoming transmission facility can not be used (in the red alarm of the installation).

A complete series of inputs that affect the transition for the signaling preprocessing state machine 2001, with respect to a given line is: PPState, PPTimer, DSIG, DSM1, DSM2, DSM3, DSM4, DSM5, the two results of the table of programmable functions of Sig Thawable [Sigln] and Sig Thawable With Yellow [Sigln], and the signal InFacRed, which applies equally to all lines. The reference character 2001 is used to denote a state machine that can be implemented as described above. In relation to figure 20, the first output of the signaling preprocessing state machine 2001, with respect to a given line is the processed signaling, called CurDsig (downstream signaling). This signaling consists of the signaling code ABCD specified by TR-NWT-000303 for the given service type, plus an additional state to indicate the conditioning of the junction line. The conditioning of the junction line is mutually exclusive with the other signaling code states. The second output of the state machine 2001, with respect to a given line, is a set of alarm bits: Freeze (signaling that is frozen) TC (Conditioning of the junction line), TCNY (suppresses yellow while in conditioning of the junction line), CFA (carrier wave fault alarm), CGAAIS (carrier wave group alarm: cause of AIS), CGAYEL (carrier wave group alarm: cause of Yellow), CGARED (group alarm of carrier wave, causes failure of the incoming installation).

The control of the machine is illustrated in the diagram of Figure 12A.

The nodes in the diagram are marked by the state names. The arcs in the diagram are marked by a transition condition. Table 22 below explains the meaning of the transition conditions in Figure 12A.

TABLE 22 Transition conditions In case two or more of the above transition conditions must be TRUE after the evaluation, only the transition for the lowest number TRUE condition in Table 23 below will be considered.

TABLE 23 The states of the processing state machine 2001 are assigned as described in Table 24 below.

TABLE 24 State definitions The alarm outputs of the state machine 2001 are defined in the following table 25 by the state function. A "1" means that the alarm is asserted.

TABLE 25 Alarm outputs The zero-zero state of Table 25 indicates that no alarm is used for the given line, and that the signaling is passed from the 2001 preprocessing state machine to the main state machine. The signaling preprocessing state machine 2001 is in control of the signaling sent to the main state machine. The last recently received entry of the volatile memory of the signaling history change recorder DSM5, is mapped through the table of programmable functions SigFreezeTof] (table 26 below), to create the signaling code FSIG (frozen signaling), the which is kept within the status information per line. The SigFreezeTo [] map of Table 26 determines the frozen signaling value to be used during a signal freezing interval. A specific example of the fundamental reason for this function is to map the ring signaling (code 0 = with the loop current fed (code 5) so as not to ring by telephones during a signaling freeze. from Normal POTS The nomenclature of the output code follows the decimal equivalent of the binary input code comment along the ordinate of the frame: TABLE 26 SigFreezeTo [l = In Table 27 below, the signaling output processed from the signaling preprocessing state machine 2001 is defined by the following state function. DSIG denotes DSIG as defined in 1 above, FSIG denotes the frozen signaling mapped as described in Table 25 above, and TC denotes the special conditioning signaling code of the junction line.

TABLE 27 F. Flexible Status Slot The UVG card status machine allows control of the telephone line based on signaling and line condition (for example, off-hook or on-hook), and can be achieved in the form of a machine program-based status in which a microprocessor examines the different input states and synchronization, and determines the appropriate output state. The advantage of the program-based state machine is that it can be altered by changing the code that forms the state machine. The disadvantage of the program-based state machine is that it requires a microprocessor and RAM to be present on the UVG card. The space and energy required by the microprocessor, together with the cost, can make the microprocessor-based UVG card less than optimal. An alternative mechanism to achieve a state machine is the hardware state machine, in which the logic gates are made wired in a configuration that forms the state machine. The advantage of said state machine is that it avoids the use of a microprocessor. The main disadvantage of said state machine is that once it is manufactured, the state machine can not be modified. Since there are small but significant differences in the signaling formats of different telephone switches, it may be necessary to make changes to ensure proper operation of the telephone line. One modality that avoids the disadvantages of the program and hardware state machines is the flexible state machine, in which a number of variables can be programmed in registers in the card.

UVG, which in a preferred embodiment, are in TIUA 880. These registers contain information that in combination with one or more simple logical operations, form a state machine. By changing the variables, the parameters of the state machine can be varied. The programming of these registers can be achieved through BNUCC 800. This method involves establishing a list of state structures that contain information specific to the state and all the branch information. In the following statement, A and b represent two series of bits that specify respectively in each branch which of the inputs need to be established, and which do not need it. This is shown below. Logically, the comparison of A and B is as follows: X = input bits. Yes ((X & A) = A) & ((-X &B) = B)), then refer to ADDR. The data structure used in this method is defined in the following table 28 using pseudocodes similar to the programming language c, and therefore is clear to those skilled in the art. As illustrated in Table 28, the information includes the type of synchronizer, which indicates the time intervals that will determine an out of time condition. The output variable controls the status of the line, for example, the timbres. The number of derivations indicates the number of possible states that can be the transition to the present state. The derivation information contains the specific input variable and the synchronization parameters that need to be compared to determine if a derivation should be made to a subsequent state, and if so, determine which is the construction direction for that subsequent state .

TABLE 28 I State. { Type of synchronizer; // This is a type of output Outputs; Number of derivations or; DERIVATION; Derivation o; // optional derivations Table 29 below illustrates the template for a data structure.

TABLE 29 The template in Table 29 is also described using a programming language similar to the C language. In Table 29, A and B are used comparatively as described above to determine whether a derivation to a new address is appropriate based on the X entry. If no partners are found in the list of BRANCHEs, then the state would remain the same. A banner would indicate if it was the first time in the state, and would adjust the synchronizer to the specified value. This avoids placing the value of the synchronizer in each of the derivations that point to a particular state. The memory would be saturated by a list of state constructs. The address in the memory would serve as the state number. The address and synchronizer values would be saved when switching between the 6 lines. In this way, only one copy of the real state machine would be needed. This method is fast. The only restriction would be the number of derivations since this is a serial process. Since there are 1800 watches per line, it is unlikely that this method could be used in any kind of time problem, since it uses a lot of memory. To find how many bits a state machine would require to describe in this method, the following formula is used: S = state number. B = number of branches. N = number of bits. N = (28 * S) + (30 * B) Equation 1 Assuming: 10 input bits 20 bit synchronizer output of 13 bits-A 1 ms or ticking, this gives up to 8 seconds. At most 8 programmable time values are needed. 10-bit address A state machine decision is required every 3 ms. This leaves approximately 1800 clocks per line Maximum of 8 types of synchronizer Maximum of 32 derivations. The LS state machine that has 8 states would require 644 bits. The complete state diagram would require 940 bits. One possible way to save memory with this method is to use only a state number instead of an address for each derivation. It would be necessary that there be additional logic that will look for the memory for each additional state until it locates the desired state number.

This method would put a limit on the number of states, which otherwise would not exist. It would save 5 bits per derivation if the number of states was not limited to 32. This method would thus save 105 bits in the total state machine. To illustrate how the above method is used in connection with a derivation in the system described herein, Figure 21 illustrates a completed data structure for the hanging status description illustrated in Table 13 above. In the same way, a reference to figure 11 is useful, since it can be seen from this figure that 3 possible derivations are available from the hung B8 state, the first up to the ring status (RNG), the second until the state of off-hook, and the third until the state of waiting. For the purposes of illustration, it will be assumed that the derivation number 1 is calling, then A would be selected as 0000000000, and B would be selected as 1111000000. If the values of A and B are indicated, the derivation A stamp would be executed. If the entries comparatively with the values of BRANCH-1 do not result in a derivation, an additional comparison of the entries with respect to the derivation decision would be evaluated.

Without any of these BRANCHEs being true, the state would remain the same. lll. Loop Test and Universal Voice Grade Card Circuit In the prior art, illustrated in Figure 13, 3 relays were used to connect the common bell bar 897, the common test bar 912, and the common test bar 214 to the subscriber circuit. In the event that any of the line power resistors 920 were open circuits due to excessive current, the test of the channel that examines the signal integrity from the subscriber line interface circuit 906 would fail. In a preferred embodiment, as shown in Figure 14, the use of a solid state relay 91 OA which is in a position in the circuit with only line power resistors 920A-1 and 920A-2, may result in false test results when the twisted down torque is tested, because if either of the 920A-1 or 920A-2 power line resistors are open circuits, the twisted torque down test will indicate a high impedance line, which will pass the test, although Actually the circuit is defective. In this case, the results of the channel tests may indicate that the subscriber line interface circuit 906A and other circuitry in the UVG 140 card is functioning properly, although the UVG card is not actually functional due to the resistor Open circuit line supply 920A-1 or 920A-2. The present embodiment solves this problem by the use of a drop test resistor 925 which is placed in a bypass position between the tip terminal 266A and the bell terminal 268A of the twisted pair lowering cable 260. In case of an open-circuit line supply resistor (920A-1, 920A-2), the twisted pair lowering test will indicate a very high impedance of some minimum resistance, which is due to the down test resistor 925. A circuit open indicates that any of the line power resistors are open. A suitable design choice for the down test resistor is 400 KO.

Claims (5)

1. NOVELTY OF THE INVENTION CLAIMS 1. - In a fiber-to-sidewalk telecommunications system having a fiber-fed terminal with a voice-grade card to provide voice telecommunications services, a method of communication with said voice-grade card, said method comprising ios steps of: a) receiving a frame-based downstream time division multiplexed signal, wherein said downstream time division multiplexed signal comprises a downstream frame aerial channel, a plurality of voice channels, wherein each channel of speech contains data downstream of pulse coding modulation (PCM) and associated downstream signaling information, and wherein said downstream PCM data and said associated downstream signaling information are located contiguously within said multiplexed signal by downstream time division based on frame and a downstream control channel; and b) transmitting a frame-based time division multiplexed signal upstream, wherein said frame-based time division multiplexed signal comprises an upstream frame aerial channel, a plurality of voice channels, wherein each channel of speech contains upstream data of pulse coding modulation (PCM) and associated upstream signaling information, and wherein said data upstream of PCM and said associated upstream signaling information is located contiguously within said multiplexed signal by upstream time division based on frame and an upstream control channel.
2. 2. The method according to claim 1, further characterized in that it comprises the steps of: c) receiving a clock signal having a frequency of 4096 MHZ.
3. 3. The method according to claim 1, further characterized in that it comprises the step of receiving a frame synchronization signal, wherein said frame synchronization signal contains a downstream superframe synchronization code comprising a binary sequence of two bits.
4. 4. The method according to claim 1, further characterized in that it comprises the step of receiving a frame synchronization signal, wherein said frame synchronization signal comprises a downstream frame synchronization code and a frame synchronization code. downstream superframe, wherein said downstream frame synchronization code is the binary sequence 11101010, and wherein said downstream superframe synchronization code is 1 1001100.
5. 5. The method according to claim 1, further characterized in that said downstream frame aerial channel of said frame-based time division multiplexed signal is the first channel in said frame-based time division multiplexed signal. 6. - The method according to claim 1, further characterized in that said downstream control channel is the last channel in said frame-based time division multiplexed signal. 7. The method according to claim 1, further characterized in that in step b), said frame-based time division multiplexed signal is transmitted in a bit-adjustable compensation relationship with respect to a signal multiplexed by downstream time division received based on table. 8. The method according to claim 1, further characterized in that said channel upstream of said frame-based time division multiplexed signal is the last channel in said frame-based time division multiplexed signal. 9. The method according to claim 1, further characterized in that said aerial channel upstream of said frame-based time division multiplexed signal is the first channel in said frame-based time division multiplexed signal. 10. In a fiber-to-sidewalk telecommunications system having a fiber-fed terminal to provide voice services, a voice grade card to provide voice telecommunications services, said voice grade card comprising: a means for receiving a frame-based downstream time division multiplexed signal, wherein said downstream time division multiplexed signal comprises an aerial frame channel, a plurality of voice channels, wherein each voice channel contains data downstream of pulse coding modulation (PCM) and associated downstream signaling information, and wherein said downstream PCM data and said downstream signaling information are located contiguously within said multiplexed signal by time division current bottom based on box and a downstream control channel; and b) means for transmitting a table-top time division multiplexed signal, wherein said frame-based time division multiplexed signal comprises an upstream frame aerial channel, a plurality of voice channels, wherein each voice channel contains upstream data of pulse coding modulation (PCM) and associated upstream signaling information, and wherein said data upstream of PCM and said associated upstream signaling information is located contiguously within said multiplexed signal by upstream time division based on frame and an upstream control channel. 11. The voice grade card according to claim 10, characterized in that said card comprises: c) means for receiving a clock signal having a frequency of 4096 MHz. 12. The voice grade card in accordance with the claim 10, further characterized in that said card is insertable into said fiber-fed terminal to provide voice services, and wherein said voice-grade card further comprises a connector that includes a first row having thirty-two terminal positions, a second row having thirty-two positions in terminal, and a third row having thirty-two positions in terminal, wherein: a) said frame synchronization signal is received on a terminal at position 5 of said second row of said connector; b) said frame-based time division multiplexed signal is received on a terminal at position 4 of said third row of said connector; and c) said frame-based time division multiplexed signal is transmitted on a terminal at position 5 of said third row of said connector. 13.- The voice grade card in accordance with the claim 11, further characterized in that said card is insertable into said fiber-fed terminal to provide voice services, and wherein said voice-grade card further comprises a connector that includes a first row having thirty-two terminal positions and a second one row that has thirty-two positions in terminal and in addition: said clock signal is received on a terminal in position 4 of said first row of said connector; said signal-divided time division downstream signal is received on a terminal at position 4 of said second row of said connector; and said frame-based time division multiplexed signal is transmitted on a terminal at position 5 of said second row of said connector. 14. An insertable voice grade card for use in a fiber-to-sidewalk telecommunications system that includes a fiber-fed terminal that, in conjunction with said insertable voice grade card, provides telecommunications services, wherein a trajectory of -4 communications between said insertable voice grade card and said fiber-fed terminal comprises a time division multiplexed signal 5 frame-based downstream and a frame-based upstream time division multiplex signal, said insertable voice grade card comprising: a) circuitry to receive at least six time division multiplexed signals containing telephone channel information extracted from said signal multiplexed by time division current 10 below frame-based, which comprises up to thirty bits of voice data modulated by pulse coding (PCM), and up to thirty bits of signaling data, each bit of PCM voice data and each bit of signal data being associated with an individual telephone channel; b) circuitry for transmitting at least six time-division multiplexed signals containing 15 telephone channel information inserted in said frame-based time division multiplexed signal, which comprises up to thirty bits of voice data modulated by pulse coding (PCM) and up to thirty bits of signaling data, each bit of PCM voice data and each bit of signaling data being associated with said channel 20 individual telephone; c) circuitry for converting said frame-based downstream time-division multiplexed signals into analog signals, and converting the analog signals into said frame-based time division multiplexed signals upstream; d) a connector that includes a first row of thirty-two terminal positions, wherein said card is configured to receive said time-division downstream multiplexed signal based on a frame on a terminal at position 4 of said first row of said connector, and supplying said upstream time-division multiplexed signal based on fibers, to a terminal at position 5 of said first row of said connector. 15. The insertable voice grade card according to claim 14, further characterized in that it comprises: e) circuitry for receiving and transmitting an aerial frame channel and a control channel. 16. The voidable grade card according to claim 15, further characterized in that said overhead channel of said upstream time division multiplexed signal is the first channel in said upstream time division multiplexed signal based on in frame. ij, 15 17. The insertable voice grade card according to claim 15, further characterized in that said control channel is the last channel of the frame in the time division multiplexed signals upstream. 18.- The insertable voice grade card in accordance with the 20 claim 14, further characterized in that said communication path between said insertable voice grade card and said fiber-fed terminal further includes a frame synchronization signal, and wherein said connector includes a second 32 position row, wherein said The card is configured to receive said frame synchronization signal on a terminal at the position 5 of said second row, wherein said circuitry for transmitting said muitiplexed signal by upstream time division based on a frame includes means for providing said signals. > multiplexed by time division upstream frame-based, said terminal at position 5 of said first row of said connector at a different time in synchronization with a frame synchronization signal received on said terminal at position 5 of said second row . 19. The insertabie voice grade card according to claim 15, further characterized in that said upstream time division multiplexed signals comprise thirty voice channels. 20. In a telecommunications system having a voice grade card for providing voice telecommunications services, a circuit for loop testing, said circuit comprising: a) at least one test relay that connects at least a common test bar to a pair of line resistors, said line resistors being in parallel circuit configuration and connecting said relay to a twisted lowering torque having a lead wire and a bell wire; and b) a drop test resistor placed in a shunt configuration between said tip wire and said bell wire, said drop test resistor having a resistive value so that when a test of said twisted drop pair is made , the presence of an open circuit can be determined due to a deficit in one or more of said line resistors. 21. - In a fiber-to-sidewalk telecommunications system that has a voice grade card to provide telecommunications services . of speech including a ring generator circuit, a method for testing said ring generator circuit, said method comprising the 5 steps of: a) generating a first pulse train signal having a first duty cycle; b) applying said first pulse train signal to said ring generator circuit; c) measuring a first DC voltage output of said bell generator circuit; d) generating a second pulse train signal having a second duty cycle; e) applying said second train signal of I 10 pulses to said bell generator circuit; f) measuring a second DC voltage output of said bell generator circuit; and g) determining whether said first DC voltage and said second DC voltage are within acceptable operational limits. 22. The method according to claim 21, 15 characterized in that said first pulse train signal and said second pulse train signal comprise digital signals. 23. The method according to claim 22, characterized in that said first pulse train signal and said second pulse train signal each have a constant duty cycle. 20 24.- In a telecommunications system that has a voice grade line card to provide voice telecommunications services, a circuit for testing a ring generator, the circuit comprising: means for generating a first train signal of pulses having a first duty cycle and a second pulse train signal having a different second duty cycle; means for applying the output of said pulse train generating circuit to the ring generator; means for measuring an output voltage of said bell generator in response to the application of said first and second pulse train signals. 25.- In a fiber-to-sidewalk telecommunications system that has a voice grade card to provide voice telecommunications services, said voice grade card includes a ring generator circuit, a method for testing said circuit ring generator, said method comprising the steps of: a) applying a first pulse train digital signal to said ring generator; b) measuring a first ringing frequency of said ring generator circuit; c) applying a second digital pulse train signal to said bell generator; d) measuring a second ringing frequency of said ring generator circuit; and e) determining whether said first ringing frequency and said second ringing frequency are within acceptable operational limits. 26.- In a telecommunications system that has a voice grade card to provide voice telecommunications services, a circuit for testing a ring generator, the circuit comprising: a pulse train generating circuit that generates first and second pulse train digital signals, said second pulse train digital signal being different from said first pulse train digital signal; means for applying the output of said pulse train generating circuit to the bell; means for measuring a frequency of an output of said ring generator circuit in response to the application of said first and second pulse train signals. 27.- In a sidewalk fiber telecommunications system that has a voice grade card to provide voice telecommunications services, a method to control the telephone line states, said method comprising the steps of; a) store exit status information comprising line states; b) store a variable that represents the number of branches; c) store branch condition information comprising signaling data, line status and synchronizer information indicating branch conditions; d) store information on the direction of the branch; e) comparing said branch condition information to determine whether said branching conditions are covered; and f) retrieving the information of the address of the information branch of the subsequent exit status when said branch conditions are covered. 28. The method according to claim 27, further characterized in that it comprises the step of: g) repeating step e) until the moment in which one of said branching conditions is covered. 29.- In a fiber-to-sidewalk telecommunications system that has a voice grade card to provide voice telecommunications services, a method to self-test said card, the method comprising the steps of: a) providing a first value of seed to the card; b) using said first seed and a second seed included in said card to generate a data stream comprising bits; and c) comparing the bits of said data stream of step b) with a predetermined bit pattern. «R 4 30. The method according to claim 29, further characterized in that step b), the data stream is generated using a linear feedback shift register. The method according to claim 29, further characterized in that the system includes a broadband digital terminal, the method further comprising the steps of: a) storing the predetermined bit pattern in a memory of said digital band terminal 10 wide; and b) wherein step c) is carried out in the broadband digital terminal. 32.- In a fiber-to-sidewalk telecommunications system, a controllable voice grade card, wherein said controllable voice grade card is controlled by 4-byte messages received in a control channel. 33. The controllable voice grade card according to claim 32, further characterized in that said 4-byte messages comprise a command byte, a high-address byte, a low-address byte and a data byte. 34.- The controllable voice grade card according to claim 33, further characterized in that a control byte value of 69 hexes causes a reset of said controllable voice grade card. 35. - The controllable voice grade card according to claim 33, further characterized in that a command byte value of 3 hexadecimal in combination with a two-byte compensation value allows programming upstream bit synchronization compensation. 36.- In a sidewalk fiber telecommunications system that has a controllable voice grade card, a communication method with said controllable voice grade card, said method comprising the steps of: a) receiving a first message with a downstream command code; and b) transmitting a response message with an upstream response code, wherein said response code is equal to said downstream command code plus the hexadecimal value of 80. 37.- In a sidewalk fiber telecommunications system having a controllable voice grade card, a method for communicating a control message to said controllable voice grade card, said method comprising the steps of: a) dividing said control message into a plurality of sub-portions; b) placing said message sub-portions in a plurality of frames of a frame-based time division multiplexed signal; c) sending said plurality of frames of said signal multiplied by frame-based time division to said card; and d) receiving said plurality of frames and assembling said message and control sub-portions to create a control message for controlling said voice-grade card. 38. - The method according to claim 37, further characterized in that said control message comprises a command byte, a high address byte, a low address byte and a data byte. 39.- The method according to claim 1, 5 further characterized in that it comprises the step of: d) receiving 4-byte messages on said control channel. 40.- The insertable voice grade card according to claim 12, further characterized in that the 4-byte messages in said control channel are received on a terminal in the position 4 of said 10 third row of said connector; and wherein the 4-byte messages in said control channel are transmitted on a terminal at position 5 of said third row of said connector. 41.- The insertable voice grade card according to claim 12, further characterized in that said voice grade card | 15 insertable includes means that respond to receiving a command byte value of 69 hexadecimals to reset said insertable voice grade card, and wherein said command byte is received on a terminal at position 4 of said third row of said connector. 42.- A computer-readable medium, characterized in that 20 comprises a plurality of state data structures, each of which defines a state of telephone equipment, the data structure for each state comprising: one or more branch data structures, each branch data structure defining a transition of state that the telephone equipment will receive after receiving an X input, each string data structure comprising data elements A and B, where A defines bit positions in which the X input must have 1s for the transition of state, and B defines positions of bits in which the input X must have Os for the state transition to occur; and ADDR of data elements that define the state data structure of a next state of the telephone equipment. 43.- The medium according to claim 42, further characterized in that the data structure further comprises data defining an output signal of the telephone equipment in said state. 44.- The computer readable medium according to claim 42, wherein the data structure further comprises data defining a period of time that the telephone equipment will wait in said state before reading the next entry. 45.- In a fiber-to-sidewalk telecommunications system that has a broadband network unit with a voice grade card to provide voice telecommunications services, the voice grade card including a state machine to control the operation of the telephone equipment coupled to said voice grade card, said state machine comprising: a signaling preprocessing layer comprising a plurality of branches, wherein said signaling preprocessing layer receives signaling information from said network unit broadband and provides control information; and a main control layer comprising a plurality of branches, said main control layer receiving outputs from said signaling preprocessing layer providing control of said plurality of branches in said main layer to control the operation of the telephone equipment connected to said signaling card. Voice degree 46.- A voice grade card for use in a sidewalk fiber telecommunications system that includes a fiber-fed terminal that, in conjunction with said insertable voice grade card, provides telecommunications services, wherein a path communication between said insertable voice grade card and said fiber-fed terminal comprises a frame synchronization signal, a downstream time division multiplexed signal based on a frame, and a frame-based time division multiplexed signal, said insertable voice grade card comprising: a) circuitry adapted to receive at least six timeslot multiplexed signals containing payloads of telephone channels, wherein said telephone channel payloads are extracted from said frame-based downstream time-division multiplex signal, which comprises a plurality of downstream bytes of voice data modulated by pulse coding (PCM) and a plurality of current bytes down signaling data, each downstream byte of PCM voice data and each byte downstream of signaling data being associated with an individual telephone channel; b) circuitry adapted to transmit at least six timeslot multiplexed signals containing payloads of telephone channels, wherein said payloads of telephone channels are inserted into said multiplexed signal by upstream time division 3 frame-based, which comprises a plurality of upstream bytes of speech data modulated by pulse coding (PCM) and a plurality of 5 bytes upstream of signaling data, each upstream byte of PCM voice data and each upstream byte of signaling data being associated with an individual telephone channel; and c) circuitry adapted to convert said downstream PCM voice data bytes into analog signals, and adapted to convert the analog signals into said upstream PCM voice data bytes. 47. The insertable line card according to claim 46, characterized in that it further comprises: d) circuitry adapted to receive a downstream box aerial channel, wherein said downstream box aerial channel is the first channel in said signal 15 multiplexed by downstream time division based on frame; e) circuitry adapted to receive a downstream control channel, wherein said downstream control channel is the last channel in said frame-based time division multiplexed signal. 48.- The insertable line card in accordance with the Claim 47, characterized in that it further comprises: f) circuitry adapted to transmit an upstream frame aerial channel, wherein said upstream frame aerial channel is the first channel in said frame-based time division multiplexed signal; g) circuitry adapted to transmit an upstream control channel, wherein said upstream control channel is the last channel in said frame-based time division multiplexed signal. 49. The nsertable line card according to claim 48, characterized in that it further comprises: h) a connector that includes a first row of thirty-two terminal positions, a second row of thirty-two terminal positions, and a third row of thirty-two terminal positions, wherein said card is configured to receive said downstream time division multiplexed signal based on a frame on a terminal at position 4 of said third row of said connector, and provide said signal multiplexed by time division upstream to a terminal at position 5 of said third row of said connector. 50. The insertable line card according to claim 46, characterized in that it further comprises: d) circuitry adapted to receive a frame synchronization signal containing a downstream superframe synchronization code. 51. The insertable line card according to claim 50, further characterized in that said downstream superframe synchronization code comprises a sequence of binary codes of two bits received over multiple frames. 52. The insertable line card according to claim 50, further characterized in that said frame synchronization signal comprises a downstream frame synchronization code. 53. - The insertable line card according to claim 52, further characterized in that said downstream frame synchronization code is the binary sequence 11101010. 54.- The insertable line card according to claim 51, further characterized in that said code Synchronization of downstream superframe is the binary sequence of 11 00 received on two frames. 55.- The insertable line card according to claim 50, characterized in that it further comprises: e) a connector that includes a first row of thirty-two terminal positions, a second row of thirty-two terminal positions, and a third row of thirty-two terminal positions, wherein said card is configured to receive said frame synchronization signal on a terminal at position 5 of said second row.