MXPA99006912A - High dynamic range variable gain amplifier - Google Patents

Abstract

A multi-stage low power, high dynamic range variable gain amplifier (100) comprises an input stage (120) cascaded with one or more current amplifier stages (160A, 160B) whereby the gain of each stage (120) may be independently controlled. The input stage (120) may be comprised of a variable transconductance amplifier (227) using variable emitter degeneration. The current amplifier (160A, 160B) may be comprised of a differential Darlington amplifier (510) coupled to a differential cascode amplifier (520). The transconductance amplifier (227) converts an input voltage signal to a current signal. The variable gain amplifier (100) is designed for efficient low power operation.

Description

HIGH DYNAMIC INTERVAL VARIABLE GAIN AMPLIFIER BACKGROUND OF THE INVENTION I. Field of the Invention The present invention relates to variable gain amplifiers (VGAs) and in particular to VGAs used in communication devices.

II. Description of the Related Art In a wireless communication environment, a wireless communications receiver can receive a signal that experiences rapid and wide variations in signal strength. In receivers such as those used in a broadband digital code division (CDMA) multiple access mobile station, it is necessary to control the power of the demodulated signal for proper processing of the signal. In addition, in transmitters such as those used in a CDMA mobile station, it is necessary to control the transmit power to avoid excessive interference with other mobile stations. These same power control considerations apply to the receivers and transmitters of the narrow band analog FM (FM) modulation wireless communication system.

There are CDMA / FM dual mode wireless communication devices that are required to provide power control of the signals received and transmitted in both digital CDMA and analog FM modulation. In these mobile stations in dual mode, the control process is complicated by the different dynamic ranges and industrial regulation standards associated with the CDMA and FM signals. That is, the magnitude of the received CDMA signals can vary in a range of about 80 dB, while the magnitude of the received FM signals can vary in a range as large as 100 dB. The provision of automatic gain control (AGC) circuitry separately for both CDMA and FM signals increases the complexity and cost of dual-mode mobile stations. Accordingly, it is desirable to provide AGC circuitry that has the ability to operate both with CDMA signals and with FM signals. Figures 1A and IB illustrate an exemplary environment for a VGA performing AGC functions. Figures 1A and IB are a block diagram of a CDMA / FM dual mode 900 cell phone designed, for example, according to the industrial telecommunication standard "Mobile Station Base Station Compatibility Standard for Dual-Mode Wideband Spread Spectrum Cellular System," TIA / EIA / IS-95, generally referred to simply as IS-95.

A VGA and reception and transmission AGC amplifiers 902, 904, respectively, of cellular telephone 900 are used. The receiving part of the front end of the cellular telephone 900 consists of antenna 906, duplexer 908, low noise amplifier (LNA) and mixing circuit 910 and filter 930. As the cellular telephone 900 travels through the coverage area of a CDMA system, the signal level at antenna 906 varies between approximately -110 dBm and 30 dBm. Note that each of these front end elements usually provide the same gain regardless of what signal level is applied to it with respect to the operating range so that the dynamic range of the signal that is applied to receive the AGC amplifier 902 is the same as the dynamic range of the signal at antenna 906, approximately 80 dB. Similarly, when the cellular telephone 900 travels through the coverage area of an FM system, the signal level at the antenna varies approximately 100 dB. The output of the reception AGC amplifier 902 is provided to the specific analog basic band application (BAASIC) 912 integrated circuit that converts the analog signal into a digital signal. The process of converting the analog signal to digital works better if the signal level that is applied to the analog to digital converter remains constant. The reception AGC amplifier 902 performs the function of compensating the variations of the input power so that the output power of the reception AGC amplifier 902 and thus the input to the analog to digital converter, Remains constant. The modem of the ASIC 914 mobile station provides demodulation for both CDMA and FM signals, as well as various digital and power control functions associated with CDMA operation. These functions are well known in the art and are not critical to the present invention, so they are not described in more detail herein. The 916 user interfaces provide the interface for the human operator. These user interfaces 916 are also well known in the art and are not critical to the present invention, so they are not described in more detail herein. The modem of the mobile station ASIC 914 also provides a modulated digital representation of the basic band of the CDMA waveform or a modulated analog representation of the FM waveform to the BAASIC 912. The BAASIC 912 converts the representation of the basic band signals to the form of analogue intermediate frequency (IF) at a constant signal level and supplied to the transmission AGC amplifier 904. The AGC amplifier of the transmitter 904 provides power control to the signal and supplies it to the up converter 918, power amplifier and driver circuitry 920, isolator 922, duplexer 908 and antenna 906. As the cell phone 900 travels through the coverage area of a cellular system, the transmission signal level at antenna 906 varies inversely with the reception power since when the reception power is at a minimum the transmission level is close to the maximum. This variation in the transmission power level is made by the AGC amplifier 904. Note that the input power to the amplifier 904 is normally fixed and the power gain of the amplifier 920 can also be fixed. More information about the automatic gain control circuit in a wireless communication system and about general power control can be found in U.S. Patent No. 5,283,536 entitled "HIGH DYNAMIC RANGE CLOSED LOOP AUTOMATIC GAIN CONTROL CIRCUIT" published on February 1, 1994, U.S. Patent No. 5,107,225 entitled "HIGH DYNAMIC RANGE CLOSED LOOP AUTOMATIC GAIN CONTROL CIRCUIT" published April 21, 1992, U.S. Patent No. 5,267,262 entitled "TRANSMITTER POWER CONTROL SYSTEM" published on November 30, 1993, U.S. Patent No. 5,469,115 entitled "METHOD AND APPARATUS FOR AUTOMATIC GAIN CONTROL IN A DIGITAL RECEIVER" published November 12, 1995 and U.S. Patent No. 5,283,536 entitled "HIGH DYNAMIC RANGE. CLOSED LOOP AUTOMATIC GAIN CONTROL CIRCUIT "published on October 26, 1993, each of which was assigned to the assignee hereof and considered are part of this as a reference. Mobile communication transmitters and receivers such as those described above are designed to have a high compression point, low noise injection and low power consumption. The receivers with high compression point and low noise injection have a high dynamic range since they can detect signals in a wide range of power levels. Transmitters with high compression point and low noise injection have a high dynamic range since they can transmit signals over a wide range of power levels. Receivers and transmitters with low power consumption increase battery life. Therefore, these characteristics are important when designing a variable gain amplifier for a communication system in which signals are transmitted and received over a large range of power levels. A receiver should have the ability to detect information both from a strong signal emission by a strong and nearby transmitter and from a weak signal emission by a low-power, distant transmitter. The degree to which the receiver can detect signals from weak to strong is called its dynamic range. In the same way, a transmitter must have the capability to transmit signals with low power to a nearby receiver and high power signals to a distant receiver. The dynamic range of a receiver is established by its minimum and maximum detectable signal levels. The minimum detectable signal level of a receiver is determined by the noise index of the receiver. In the same way, the minimum transmissible power is established by the noise index of the transmitters if the signal level falls near or below the noise floor. The noise index of a VGA is partly a function of the noise injection properties and the VGA gain. In general, the greater the gain of the receiver, the better its noise index; that is, the best ability is to detect a very weak signal in the presence of noise. The maximum detectable signal level of a receiver can be established by the intermodulation distortion (IMD) execution of the receiver. When multiple signals pass through any device, mixing action between the signals occurs because of the nonlinearities of the device.

For example, a location where analog CDMA and FM systems coexist, third-order IM products from the analog FM system generally fall within the CDMA passband. These IM products act as "disrupters" that contribute to the IMD that may interfere with the detection and demodulation of the desired signal within the receiver. An IMD execution of a VGA is partly a function of its linearity and its gain. In general, the smaller the gain of the receiver, the better is its execution of IMD. This contrasts with the noise index requirements as described above. In this way, the design of a VGA for a receiver with a large dynamic range includes the difficult exchange or balance between the execution of IMD and the noise index. Similar design considerations are pertinent with respect to VGAs for transmitters, with the difference that in general, VGAs for receivers are designed to provide a relatively constant level of output power while VGAs for transmitters are designed to receive power levels. relatively constant inputs and provide a variable range of output power levels. In addition, mobile receivers are designed to be compact, lightweight and have a long lifespan. Mobile receivers are driven by a minimum number of battery cells to reduce their size and weight and improve their portability. Because the battery voltage is proportional to the number of battery cells, the AGC circuitry, including the variable gain amplifier (VGA), must operate at low supply voltages. It is also desirable to increase the life of the battery to increase the period between battery replacement or recharging. Therefore, the AGC circuitry, including its VGA, should consume little power and DC direct current. This requirement of low DC power consumption also implies a design balance similar to that already mentioned. More DC power is required for a high gain amplifier that has good noise index. However, less DC power is required for an amplifier that has good IMD performance. Existing VGA designs are inefficient since they do not have the capacity to sufficiently conserve DC power at low gain levels. What is needed is a VGA with high dynamic range, good noise index and execution of IMD as well as low DC power consumption.

SUMMARY OF THE IHGVEHCIOH According to the present invention, a VGA having high dynamic range, good noise index and execution of IMD and minimum DC power consumption is provided. The VGA can be used in automatic gain control amplifiers (AGC) for chains of transmitters and receivers in a cell phone. The VGA executes the power gain by converting an input voltage signal to a current signal and amplifying the current signal. The amplified current signal can be converted to a voltage signal by terminating the VGA with an appropriate impedance. The VGA is constituted by at least two stages in cascade, one input stage and one current amplifier. The input stage can further be separated into a CDMA input stage and an FM input stage, with the outputs of both input stages coupled to the input of the current amplifier and selectable by a CDMA / FM mode signal. In one embodiment, the FM input stage is single terminal and the CDMA input is balanced. The gain of the VGA can be increased by successively cascading two or more stages of current amplifiers. The gain in transconductance of the input stages can be controlled by a control signal. The VGA of low power and high dynamic range is made using a combination of techniques. In a first embodiment, very suitable for an AGC amplifier that receives in dual mode as the amplifier 902 of Figure 1, the CDMA stage is constituted by a variable transconductance amplifier connected in cascade with a Gilbert cell attenuator. The variable transconductance amplifier converts a variable voltage signal to an output current signal with a transconductance that is controlled by a FET transistor that acts as a variable emission degeneration resistor. The emission degeneracy provides variable local-series feedback that allows the CDMA input stage to handle a wide dynamic range of input signals, while providing good noise index and IMD execution. In the presence of a low level input signal, the channel resistance of the FET transistor can be varied to increase the gain of the input stage, whereby the receiver noise index and the ability to detect weak signals are improved. On the other hand, in the presence of a high level input signal, the channel resistance of the FET transistor can be varied to decrease the gain of the input stage, whereby the IMD performance of the receiver is improved. The Gilbert cell attenuator provides additional current attenuation, so that any subsequent amplification stages are not saturated within their non-linear range when a large input signal is applied. In this first mode, the FM input stage is a bipolar differential amplifier with degeneration of the emitter, followed by a Gilbert cell attenuator. The Gilbert cell attenuator, which also attenuates the current flowing to the next current amplifier stage. Unlike the CDMA input stage, the FM input stages use a fixed gain transconductance stage rather than a variable emission degeneracy because the linearity requirement in the standard (IS-95) for FM signals is much more relaxed than for CDMA signals, allowing the amplifier to saturate earlier in non-linearity. In a second embodiment, very suitable for a transmission AGC amplifier such as amplifier 904 of Figure 1, both the FM and CDMA signals can be handled by a fixed gain transconductance input stage comprising a differential pair with shunt feedback. -series (in series-parallel) to the input, followed by a transconductor and a Gilbert cell attenuator. The shunt-series input feedback allows a linear and exact input impedance without using a brute force equalization. The output of the differential pair can be AC coupled to the transconductor through a pair of capacitors. The transconductor converts the voltage output of the differential pair to a current using a differential amplifier of degenerate emission. The current is then fed to the Gilbert cell attenuator which further attenuates the current flowing to the next stage of the current amplifier. A variable gain input stage is not required because the input level to the AGC amplifier 904 of the transmitter is generally constant. In the first embodiment, suitable for use as a reception AGC amplifier 902, each of the current amplifiers consists of two sections, a differential Darlington amplifier and a differential horn amplifier. These current amplifiers are translinear circuits that allow the current gain to be controlled by varying the ratio of the "tail currents" that polarize the translineal circuit. The current gain of each stage of the current amplifier can be controlled independently by one or more control signals. In the second embodiment, suitable for use as a 904 transmission AGC amplifier, each of the current amplifiers consists of two sections, a differential Darlington amplifier and a single differential pair. The current amplifier is a hybrid of a feedback current amplifier and a translinear circuit. In each of the modalities mentioned above, the gain of the variable gain stages is controlled by a gain control circuit that varies the gain of the current amplifiers according to the applied AGC control voltage (either RX GAIN CONTROL or TX GAIN CONTROL of FIG. 1) ). The gain control circuit includes an exponential function generator that ensures the linearity (in dB) of the VGA in the wide dynamic range. It is therefore a benefit of the present invention to provide a VGA having a high dynamic range with respect to the CDMA signals as well as the FM signals. A mobile receiver that uses a VGA of these can detect signals at wider power intervals. Another is that the VGA consumes a minimum of DC power. Therefore, the VGA can be used in a mobile communication device and advantageously conserves the useful life of the batteries. An additional benefit is that the gain of the VGA can be varied linearly in approximate form in dB by linearly adjusting the DC control voltages.

BRIEF DESCRIPTION OF THE DRAWINGS The particularities, objects and advantages of the present invention will be more evident from the detailed description set forth below when taken considering the drawings in which the references are used consistently and where: Figure 1A and IB are a schematic diagram of an exemplary dual mode CDMA / FM communication device capable of being used with the present invention; Figure 2 is a block diagram of an exemplary triple stage variable gain amplifier of the present invention; Figure 3 is a diagram of the CDMA input stage of Figure 2; Figure 4 is a diagram of the polarization control circuit of the transconductance amplifier of Figure 2; Figure 5 is a diagram of the exponential function generator of Figure 4; Figure 6 is a partial combination of elements of Figures 2 and 3 constructed to illustrate the advantageous properties of the present invention; Figure 7 is a diagram of the current amplifiers of Figure 2; and Figure 8 is a diagram of the tail current generator of Figure 7.

DETAILED DESCRIPTION OF THE PREFERRED MODALITIES The present invention is directed to a monolithic integrated circuit variable gain amplifier (VGA). The VGA provides gain in proportion to a control voltage. The VGA provides exponential voltage gain as a function of the linear increments in the applied control voltage and thereby provides approximately linear power gain in decibels (dB) in direct proportion to the linear increments in the applied control voltage. The VGA can provide linear power gain in a large dynamic range greater than 80 dB (or a factor of 1 to 100,000,000). The VGA provides linear power gain that is tolerant of the process variations that occur during the manufacture of the VGA. The VGA can be used in many applications that include receivers and transmitters. If the VGA is operating in a receiver, the input to it normally varies over a wide dynamic range while the output of the VGA is relatively constant. When the signal level input to the VGA operating in a receiver is small, the VGA gain must be relatively large. When the signal level input to the VGA operating in a receiver is large, the VGA gain should be relatively small. In this way, a VGA operating in a receiver should normally have good noise index performance when relatively high gain and good intermodulation performance is being provided when relatively low gain is provided. If the VGA is operating on a transmitter, the input is normally constant while the VGA output varies over a wide dynamic range. When the output of the VGA signal level needs to be large, the VGA gain must be relatively large and the intermodulation performance must withstand the large signal levels that result. When the output of the signal level from the VGA operating in a transmitter needs to be small, the VGA gain must be relatively small and the VGA noise execution may be important. Figure 2 is a block diagram of a variable gain amplifier (VGA) mode 100 that adjusts the power level to input signal over a wide dynamic range. The embodiment of Figure 2 is suitable for use as receiving amplifier AGC 902 of Figure 1. VGA 100 comprises three stages: input stage 120 and two stages of cascade current amplifiers 160A and 160B. More than one current amplifier stage 160 is cascaded consecutively after the input stage 120 to increase the dynamic range of the VGA 100. In a first mode, the input stage 120 comprises separately an FM input stage. 121 and a CDMA input stage 122 with respective input ports 171 and 170. The input stage FM 121 and the input stage CDMA 122 are alternately connected to the current amplifier 160A by means of switches 123., which are controlled by the CDMA / FM mode selection signal. When the communication device is in CDMA mode, the switches 123 connect the CDMA input stage 122 to the current amplifier 160A and disconnect the FM input stage 121. Conversely, when the communication device is in the FM mode, the switches 123 connect the input stage FM 121 to the current amplifier 160A and disconnect the input stage CDMA 122. Figure 2 also illustrates the bias ports 110, 130, 150A, 150B for the control of the voltages to be applied to VGA 100. The gain of each stage is controlled by the control voltages, which can be generated, for example by the detection circuitry of the receiver which determines the signal strength. Each stage is constituted by a variety of components, among which an active device is included as a transistor. The input signal to the VGA provided at the input ports 170 of the input stage 122 is balanced, i.e., it is divided into two signal patterns each carrying a signal between one hundred and eighty degrees apart. The input signal to the VGA is input via the input port of the VGA 170. However, the input signal to the VGA provided at the input ports 171 of the input stage FM 121 is single ended. The output of the input stage 120 and the input of the current amplifier 160A are coupled through the port 190. Because it operates with low supply voltage, approximately 3.6 volts, the input stage 120 converts the input voltage signal to a current signal that prevents active VGA devices from operating in their non-linear region and distorts the input signal. The low supply voltage of the VGA 100 also decreases the power consumption of the VGA 100. Figure 3 illustrates one embodiment of the CDMA 122 input stage. The balanced signal is input to the input port of the VGA 170. The CDMA input stage 122 comprises a variable transconductance amplifier 227 coupled to a Gilbert cell attenuator 226 and serves four functions. First, the variable transconductance amplifier 227 converts the input voltage signal to a current signal. Second, the combination of the variable transconductance amplifier 227 and the Gilbert 226 cell attenuator allows variable amplification of the signal, which can be varied exponentially (linearly in dB) by linearly adjusting the control voltages at the polarization port 110. Third , the increased emission degeneracy in the variable transconductance amplifier 227 decreases the IMD of the VGA 100 when the input signal voltage is large and the IMD should be more prominent. As the emission degeneracy in the variable transconductance amplifier 227 is increased, the transconductance and thus the IMD, of the input stage 120, decrease. Finally, the decreased emission degeneracy in the variable transconductance amplifier 227 improves the noise index of the VGA 100 when the input signal voltage is small and the noise performance is the most critical. As the emission degeneracy in the variable transconductance amplifier 227 is decreased, the transconductance of the input stage 120 increases, improving the noise index of the receiver. The variable transconductance amplifier 227 consists of two bipolar junction transistors (BJTs) 235 and 236, two current sources 238 and 239 and field effect transistor (FET) 237. The current sources 238 and 239 are connected in series to the emitters of the BJTs 235 and 236. The connection of the source 228 and the drain connection 229 of the FET 237 are connected respectively to the emitters of the BJTs 235 and 236. The balanced signal of the input port of the VGA 170 is applied in the bases of the BJTs 235 and 236. The balanced current output of the variable transconductance amplifier 227 flows from the collectors of the BJTs 235 and 236. The variable transconductance amplifier 227 can be adjusted by varying the emission degeneracy of the BJTs 235 and 236. As a consequence, the gain of VGA 100 can be varied. The emission degeneracy of BJTs 235 and 236 is generated by varying the channel resistance of FET 237. FET 237 is operated as a variable resistor in its ohmic zone and provides variable emission degeneracy for the two BJTs 235 and 236. The voltage The FET 237 drain-source polarization must therefore be less than the cut-off voltage of FET 237. The channel resistance can be varied by adjusting the polarization through the gate-source junction of FET 237 by varying the voltage applied to the polarization port 290. The transconductance of the variable transconductance amplifier 227 can be increased by decreasing the channel resistance of the FET 237. Thus, the present invention, by providing the variable channel resistance through the FET 237 allows both considerations to adapt. of competitive design of noise index as the execution of IMD. In addition, the DC efficiency of the VGA 100 is improved because the CDMA input stage 122 pulls in sufficient DC current necessary to amplify the low level input signals, while reducing the DC current consumption of the amplification stages. of previous current when its transconductance is decreased for high-level input signals. The differential output currents of the variable transconductance amplifier 227 are coupled to the Gilbert cell attenuator 226. The Gilbert cell attenuator 226 varies the current amplitude of a signal applied to its inputs. The Gilbert cell attenuator 226 consists of a first pair of BJTs 231 and 234 and a second pair of BJTs 232 and 233. The attenuation level of the Gilbert cell attenuator 226 is established by a control voltage applied at the polarization port 110. The Gilbert cell attenuator 226 attenuates the output current of the variable transconductance amplifier 227 when the first pair of BJTs 231 and 234 is biased by the control voltage applied to the bias port 110 so that one component of the output current of the variable transconductance amplifier flows through the first pair of BJTs 231 and 234 rather than through the second pair of BJTs 232 and 233. Therefore the balanced currents at port 190 of the Gilbert cell attenuator 226 decrease. Both the variable transconductance amplifier 227 and the Gilbert 226 cell attenuator are polarized by the common power supply 230. The preferred embodiment of the input stage FM 121 is similar to that of input stage CDMA 122 except that FET 237 is replaced by a fixed resistor. As previously mentioned, the fixed resistance of the FM 121 input stage provides a fixed transconductance because industrial standards, such as the IS-95, allow compression of the input signal (for example, VGA is allowed to go non-linear) in a much lower input level than the CDMA input signal. Alternatively, the input stage 120 may comprise only a simple fixed transconductance stage similar to that of the FM input stage 121. This alternate mode would be very suitable especially for use as the transmission AGC amplifier 904 of FIG. 1. As shown in FIG. noted above, one aspect of the design is that the transconductance of the variable transconductance amplifier 227 varies exponentially as the control voltage applied to the bias port 130 of the transconductance bias control circuitry 140 is linearly adjusted. To have this result, the channel resistance of the FET 237 also varies exponentially as the control voltage in the bias port 130 of the transconductance bias control circuitry 140 is linearly adjusted. Figure 4 illustrates one embodiment of the transconductance bias control circuitry 140 that facilitates this result. The transconductance bias control circuitry 140 includes the exponential function generator 360, first and second operational amplifier circuits 353 and 354, low pass filters 352 and current source 341. The exponential function generator 360 converts the control voltage applied in the polarization port 130 to two output currents flowing from the output 358 of the exponential function generator 360 to the first operational amplifier circuit 353. The ratio of the amplitudes of these currents is exponentially proportional to the control voltage. The control voltage, in the exemplary embodiment of Figure 1 is either RX GAIN CONTROL or TX GAIN CONTROL or a scaled or temperature compensated version thereof. The generation of this control voltage is beyond the scope of the present invention and is described elsewhere as in U.S. Patent No. 5,469,115, which is considered to be part of the present reference.

Figure 5 illustrates one embodiment of the exponential function generator 360. The exponential function generator 360 comprises the differential amplifier 465 having outputs that conduct a pair of FET current mirrors 474. The differential amplifier 465 comprises a parallel pair of BJTs 461 and 462 connected to the power source 472. The pair of current mirrors FET 474 comprises four FETs 464,466,468 and 470. Due to the exponential ratio input voltage / output current of BJTs 461 and 462, the ratio of their collector currents is proportional to the differential base voltage between BJTs 461 and 462, which is determined by the control voltage signal. Thus, the change in linear differential voltage across the polarization port 130 results in an exponentially related current at the output 358. The current mirrors 474 simply take the exponentially related current that is generated by the bipolar differential pair 461 and 462. and they supply it for use in the amplifier. The exponential function generator 360 is biased by a power source 400. Again with reference to Figure 4, the first and second operational amplifier circuits 353 and 354 act in cooperation with the exponential function generator 360 to control the channel resistance of FET 237 of Figure 3. The first operational amplifier circuit 353 comprises master FET 344, which is preferably identical to FET 237, reference resistor 346 and differential operational amplifier 348. The output currents from the exponential function generator 360 are coupled to the master FET 344 and the reference resistor 346. The differential operational amplifier 348 causes the voltage to pass through the drain and source terminals of the master FET 344 and the terminals of the reference resistor 346 to be equal by varying the voltage of polarization applied to the gate of FET 344. The polarization voltages applied to the compuert The FET 237 through the polarization port 344 are usually the same. However, the gate bias voltage applied to the FET 237 through the bias port 122 is filtered in a low pass filter to prevent thermal noise from the transconductance bias control circuitry 140 being input to the FET 237. The low pass filtering is carried out by a low pass filter 352 formed by series resistor 350 and bypass capacitor 351. The second operational amplifier circuit 354 causes the master FET 344 and the FET 237 to have the same source voltage. The second operational amplifier comprises a unitary gain operational amplifier 349 and resistors 345 and 347, which detect the source-drain voltage through FET 237 via source connection 228 and drain connection 229. The exponential function generator 360 and the current source 341 connected around the master FET 344 and the reference resistor 346 are designed so that the voltage drop across the reference resistor 346 and consequently through the drain-source of the master FET 344 is less than the voltage of the FET. As a consequence, the operation of the operational amplifier circuits 353 and 354 forces the FET 237 and the master FET 344 to operate at similar idle points in their ohmic regions. Therefore, the channel resistances of both the FET 237 and the master FET 344 are generally identical and vary exponentially with a linearly adjusted control voltage applied to the bias port 130. Figure 6 is a partial combination of elements in Figures 2 and 3 constructed to illustrate the advantageous properties of the present invention. One of the points overcome by the arrangement shown in Figure 6 is the process variation of μcCox and consequently the channel resistance of FET 237 as a function of the voltage applied to its gate. As previously mentioned with respect to Figure 3, the FET 237 controls the transconductance of the variable transconductance amplifier 227. The variable emission degeneracy provided by the FET 237 allows the input stage 120 to handle a wide range of signals. Due to the attenuation caused by the input stage 120 is very critical for the operation of the circuit and the characteristics of the stage set by the FET 237, it is very important to establish the resistive value accurately. Because the channel resistance as a function of the applied gate voltage is difficult to control in part during the manufacturing process, the external control circuit is used to achieve consistency. Figure 6 shows the external control circuit used to immunize the operation of the CDMA input stage 122 to the process variations of the FET 237. The resistor 346 is an on-chip resistor. This resistor becomes large to minimize process variations. Resistor 346 is used as a reference resistor for the control circuit. Note that the total current from the output 358 of the exponential function generator 360 is established by means of the current source 341. So if the current through one of the balanced outputs 358 increases the current through another of the Balanced outputs of output 358 decreases.

Also note that the voltage drop across resistor 346 is the same as the voltage drop across master FET 344. The voltage drop is the same because each voltage is one of the inputs to the op amp (operational amplifier) 348 The output of op amp (operational amplifier) 348 controls the resistance of master FET 344 so that the voltage drop across it is the same as the product of the current through resistor 346 and the value of resistor 346. that, as the current through the resistor 346 increases and the current through the master FET 344 decreases, the voltage drop across the resistor 346 increases. In response, the channel resistance of the master FET 344 must also increase so that the voltage drop remains the same. The same op amp output voltage 348 that is applied to the gate of the master FET 344 is also applied to the gate of the FET 237. The resistor 350 and the capacitor 351 provide a low pass filter between the amp op output 348 and the voltage of FET 237 gate but the DC voltage applied to the gate of the master FET 344 and to the gate of the FET 237 is the same. In the preferred embodiment, the master FET 344 and the FET 237 are very close to each other on a common substrate. Thus, although the process variations of part of VGA to part of VGA are significant, within a single VGA part, the gate voltage against the channel resistance characteristic of master FET 344 and FET 237 are closely followed by each other. . In this manner, the resistance of the FET 237 is set to be equal to the resistance of the master FET 344. As the channel resistance of the FET 237 decreases, the current flows through transistors 235 and 236. In this way, the present invention provides a way to exactly execute the variable emission degeneracy of the CDMA input stage 122. Figure 7 illustrates one embodiment of the current amplifiers 160A, 160B as shown in Figure 2. The input of the current amplifier 160 as shown in Figure 7 may be coupled to the output of the input stage 120 or to the output of another current amplifier 160. The current amplifier 160 comprises Darlington 510 differential amplifier, 520 hull differential amplifier and current generator 570. Current amplifier 160 is polarized by 508 and 506 power sources and 596 and 598 current sources. The Darlingto differential amplifier n 510 comprises BJTs 580, 586, 588 and 594 and resistors 582, 584, 590 and 592 in a topology shown in Figure 7 so that the Darlington 510 differential amplifier has resistive shunt-series feedback to provide increased current gain. and insensitivity in the process variation. In the present invention, it should be noted that the shunt-resistive series feedback provided by the resistors 582, 584, 590 and 592 of the present invention attempts to force the feedback current through the resistors to be equal to the current of the resistor. input through the input port 190. In this way, since they also provide a current divider, they increase the current gain of the Darlington 510 differential amplifier by means of the ratio of the feedback resistors. The cascode differential amplifier 520 provides a translineal circuit that supplies variable current amplification according to the ratio of tail currents 512 generated by tail current generator 570. The cascode differential amplifier comprises BJTs 500, 502, 504 and 506 in the topology of a differential current mirror (translineal circuit), which allows the gain of the current amplifier to vary by varying the tail currents 512. The gain of the current amplifier 160 is controlled by the tail current generator 570. The generator tail current 570, through the differential port 512 is connected to both the Darlington 510 differential amplifier and the cascode 520 differential amplifier. The current amplification of each of the current amplifiers 160 can be varied exponentially using the control current generated by the exponential function generator 360 of FIGS. 4 and 5 applied to the control ports 150. The tail current generator 570 is biased by a power source 509. FIG. 8 illustrates a mode of the tail current generator 570. The current generator queue 570 comprises an exponential function generator 861 which may be similar or the same element as the exponential function generator 360 (Figures 4 and 5) that produces the output 859 that is similar to or equal to the output 358 of the exponential function generator 360 The exponential function generator 861 is coupled to a pair of bipolar current mirrors 860. In FIG. uits are coupled to a power source 509, however they can also be coupled to different sources of power. A pair of bipolar current mirrors 860 are comprised of a first group BJT 822, 824 and 830 and a second group BJT 832, 834 and 840 and a first resistor group 826, 828 and 844 and a second resistor group 836, 838 and 842 The purpose of the pair of bipolar current mirrors is to take the control current provided by the exponential function generator 861 and to transform it into the tail currents 512. In one embodiment of the present invention, the exponential function generator 360 and 861 are the same element, so advantageously provides a simple control current that can be reflected to the CDMA input stage 122, as well as to the current amplifiers 160A and 160B. This mode provides even more DC efficiency by reducing the current gain (and thus the DC current consumption in the batteries) of the 160A and 160B current amplifiers at the same time and in the same proportion that the transconductance of the current is reduced. CDMA input stage 122. In addition, this arrangement ensures that all current amplification at all stages is exponentially related (linear in dB) to the control voltage of the AGC amplifier. Thus, the present invention provides a VGA having a high dynamic range both with respect to CDMA signals and FM signals, with a maximum of shared elements in both CDMA and FM modes. A mobile receiver that uses a VGA of these can detect signals at higher input power intervals. The VGA also consumes minimal DC power. Therefore, the VGA can be used in a mobile communication device and advantageously conserves the useful life of the batteries. Finally, the VGA gain can be varied linearly in dB by adjusting the DC control voltages. The above description of the preferred embodiments is given to allow any person skilled in the art to make or use the present invention. The various modifications of these modalities will be readily apparent to those skilled in the art and the generic principles defined herein may be applied to other modalities without the use of the inventive faculty. Thus, it is not intended that the present invention be limited to the modalities shown herein but be in accordance with the broadest scope consistent with the new principles and particularities set forth herein.

Claims (32)

1. NOVELTY OF THE INVENTION Having described the present invention, it is considered as a novelty and, therefore, the content of the following CLAIMS is claimed as property. 1. A variable gain amplifier comprising: a transconductance input stage that includes at least one transistor having variable emission degeneration, the transconductance input stage has a pair of differential voltage inputs to receive a signal that goes to be amplified and has a pair of differential current outputs; at least one current amplifier coupled to the differential current outputs to amplify the signal to be amplified; and a control circuit, coupled to the transconductance input stage and to the at least one current amplifier, for applying a control signal to the transconductance input stage and to the at least one current amplifier, the signal of control serves to exponentially vary a gain of the transconductance input stage and of the at least one current amplifier in response to a linear variation in the control voltage.
2. 2. The variable gain amplifier according to claim 1, wherein the transconductance input stage comprises: an analog modulation input stage having a fixed transconductance; and a digital modulation input stage having a variable transconductance, the variable transconductance varies by the control signal.
3. The variable gain amplifier according to claim 2 further comprising at least one mode selection switch for alternately coupling the analog modulation input stage and the digital modulation input stage to the at least one current amplifier, in response the mode selection signal.
4. The variable gain amplifier according to claim 1, wherein the transconductance input stage comprises: a first bipolar junction transistor having a base coupled to a first of the differential voltage inputs; and a second bipolar junction transistor having a base coupled to a second of the differential voltage inputs; and a slave field effect transistor having a source coupled to an emitter of the first bipolar junction transistor and a drain coupled to an emitter of the second bipolar junction transistor and a gate coupled to the control circuit to receive the control signal, whereby the control signal varies a channel resistance of the slave field effect transistor, whereby the variable emission degeneracy varies.
5. The variable gain amplifier according to claim 4, wherein the transconductance input stage further comprises an attenuator for limiting the differential current output.
6. The variable gain amplifier according to claim 4, wherein the control circuit comprises: an exponential function generator for translating a linear change in the control voltage to an exponential change in the control current; a first operational amplifier circuit, coupled to the exponential function generator and receiving the control current, the first operational amplifier circuit serves to control the channel resistance of the slave field effect transistor; a second operating amplifier circuit for controlling a drain-source voltage of the slave field effect transistor; and a current mirror to provide the signal to the first operational amplifier circuit and to the at least one current amplifier.
7. The variable gain amplifier according to claim 7, wherein the first operational amplifier circuit comprises a master field effect transistor coupled in parallel with a reference resistor; and an operational amplifier to make the channel resistance of the slave field effect transistor the same as the channel resistance of the master field effect transistor.
8. The variable gain amplifier according to claim 1, wherein the at least one current amplifier comprises: a differential Darlington amplifier having resistive shunt-series feedback; a differential cascode amplifier, coupled to the differential Darlington amplifier as a translineal circuit; and a tail current generator, coupled to the control circuit, to the differential Darlington amplifier and to the differential horn amplifier, the tail current generator generates a differential pair of tail currents, so that a gain of the current amplifier is proportional to a relationship of the differential pair of tail currents.
9. The variable gain amplifier according to claim 8 wherein the differential Darlington amplifier comprises: a first bipolar junction transistor having a base coupled to one of the differential current outputs of the transconductance input stage; a second bipolar junction transistor having a base coupled to another of the differential current outputs of the transconductance stage; a first current divider coupled in a first terminal to a collector of the first bipolar junction transistor and coupled in a second terminal to the base of the first bipolar junction transistor; and a second current divider coupled in a first terminal to a collector of the second bipolar junction transistor and coupled in a second terminal to the base of the second bipolar junction transistor, whereby a differential gain of the Darlington amplifier is increased in a resistance ratio within the first and second current dividers.
10. 10. An amplifier for processing an input signal comprising: an input stage including a transconductance amplifier; a current amplifier, coupled to the input stage; and means for applying a control voltage linearly adjusted to the current amplifier to exponentially vary the gain of the amplifier as a function of the applied control voltage.
11. 11. The amplifier according to the claim 10, wherein the transconductance amplifier has variable transconductance.
12. 12. The amplifier according to the claim 11, wherein the input stage further comprises an attenuator coupled to the transconductance amplifier.
13. 13. The amplifier according to the claim 12, where the attenuator is a Gilbert cell attenuator.
14. 14. The amplifier according to the claim 11, which further comprises a transconductance amplifier bias control circuit coupled to the transconductance amplifier.
15. The amplifier according to claim 14, wherein the input signal includes two balanced signals and wherein the transconductance amplifier further comprises: active devices, wherein each balanced signal is input to a respective input of the active devices; current sources respectively coupled to the active devices; and a variable resistor coupled to the active devices and current sources.
16. 16. The amplifier of claim 15, wherein the attenuator further comprises: second active devices; and third active devices, wherein the second active devices and the active third devices are coupled to the first active devices.
17. 17. The amplifier according to the claim 14, wherein the transconductance polarization control circuit further comprises: an exponential function generator; a first operational amplifier circuit coupled to the exponential function generator; a second operational amplifier circuit coupled to the first operational amplifier circuit; and a current source coupled to the first operational amplifier circuit.
18. 18. The amplifier according to the claim 17, wherein the transconductance bias control circuit comprises a low pass filter coupled to the first operational amplifier circuit.
19. 19. The amplifier of claim 17, wherein the exponential function generator comprises: a pair of active devices; a current source coupled to the active devices; and a pair of current mirrors respectively coupled to the active devices.
20. 20. The amplifier according to the claim 17, wherein the first operational amplifier circuit further comprises: a master active device; a reference resistor coupled to the master active device; and a differential amplifier having first and second inputs and an output, wherein the master active device is coupled to the first input and output of the differential amplifier and the reference resistor is coupled to the second input of the differential amplifier.
21. The amplifier according to claim 17, wherein the second operational amplifier circuit further comprises: a unitary gain amplifier without inversion having first and second inputs; a first input resistor coupled to the first input of the unity gain amplifier without inversion; and a second input resistor coupled to the second input of the unity gain amplifier without inversion.
22. 22. The amplifier according to claim 11, wherein the step of the current amplifier comprises: a Darlington differential amplifier; a cascode differential amplifier coupled to the Darlington differential amplifier; and a tail current generator coupled to the Darlington differential amplifier and the cascode differential amplifier.
23. 23. The amplifier according to the claim 22, wherein the Darlington differential amplifier comprises: a pair of first active devices; a pair of second active devices respectively coupled to the first active devices; a pair of first resistors respectively coupled to the first active devices and to the second active devices; a pair of second resistors respectively coupled to the first active devices and to the second active devices; and a pair of current sources respectively coupled to the first active devices and to the second active devices.
24. The amplifier according to claim 22, wherein the cascode differential amplifier comprises: a pair of first active devices; and a pair of second active devices respectively coupled to the first active devices.
25. The amplifier according to claim 22, wherein the tail current generator comprises: an exponential function generator; and a pair of current mirrors coupled to the exponential function generator.
26. 26. The amplifier of claim 25, wherein the exponential function generator comprises: a pair of active devices; a current source coupled to the active device; and a pair of current mirrors respectively coupled to the active devices.
27. 27. The amplifier according to the claim 25, wherein the pair of current mirrors comprises: a pair of first active devices; a pair of second active devices respectively coupled to the first active devices; a pair of third active devices respectively coupled to the first and second active devices; a pair of first resistors respectively coupled to the first active devices; and a pair of second resistors respectively coupled to the first, second and third active devices.
28. 28. A method for processing an input signal in an amplifier, wherein the amplifier includes a transconductance amplifier coupled to a current amplifier, comprising the steps of: applying the input signal to a transconductance amplifier; and modify the current amplitude of the input signal.
29. The method according to claim 28, further comprising the step of: applying a linearly variable control voltage to the amplifier to produce corresponding exponential changes in the current amplitude of the input signal.
30. 30. The method according to claim 28, further comprising the step of: generating a pair of currents, whose ratio of amplitudes varies exponentially with a control voltage, to vary the current amplitude of the input signal.
31. 31. The method according to claim 28, further comprising the step of: modifying the degenerative feedback in the transconductance amplifier to vary the current amplitude of the input signal.
32. 32. The step of the method according to claim 28 for modifying the current amplitude of the input signal, further comprising the steps of: applying a control voltage to the transconductance amplifier; converting the control voltage to a pair of currents whose amplitude ratio is exponentially proportional to the control voltage; convert the current pair to an internal voltage; and modifying the degenerative feedback in the transconductance amplifier with the internal voltage, such that a linear change in the amplitude ratio of the current pair linearly alters the current amplitude of the signal.