MXPA99004573A - Field identification system - Google Patents

Abstract

A digital television signal includes successive frames of two fields each comprising 313 data segments with the first data segment in each field functioning as a field sync. The field sync segment comprises a 511 pseudo-random number (PN) sequence and three 63 PN sequences, with the middle one of the 63 PN sequences alternating polarity in successive fields. A reference data segment is compared with the 511 PN sequence in each data segment and the data segment with the least number of errors is identified as the first data segment in the field. The corresponding portion of the reference segment is compared with the middle 63 PN sequences in the identified first data segments and that with the least number of errors is determined to be the first segment in the frame. Confidence counters are used to assure reliable determinations.

Description

FIELD IDENTIFICATION SYSTEM DESCRIPTION OF THE INVENTION This invention relates in a general way to television receivers and in particular to a field identification system used in a digital television receiver. The Advanced Television System (ATV) recently adopted by the FCC for use in the United States for both high definition television (HDTV) and lower resolution HDTV signals incorporates residual sideband (VSB) transmission. The transmission system VSB is characterized in both terrestrial and cable modes by a data block comprising two data fields of 313 data segments each with each data segment comprising 832 multi-level symbols. The first data segment in each field comprises a data field synchronization segment and each data segment is headed by a four symbol data segment synchronization followed by 828 data and anticipated error correction symbols. (Until now, the data field synchronization segments do not include early error correction symbols). The field and segment synchronization symbol facilitates the recovery of data in the ATV receiver and provides signals from REF .: 29446 synchronization for fields and segments. Each field synchronization segment also includes information that identifies the VSB mode. The transmission is via the suppressed modulation of the carrier. Three hundred ten kilohertz of the lower band edge, a small DC pilot, is added to the signal to be used by the VSB receiver to achieve the immobilization of the carrier. The data and bytes of advance error correction (FEC) are randomly distributed and interleaved to add protection against synchronization errors. The symbol range is approximately 10.76 MHz. The synchronization symbols are always at the level of two. In terrestrial mode, symbols encoded by trellis of level 8 (3 bits per symbol) are transmitted while the cable mode, symbols of level 16/8/4/2 (4/3/2/1 bits per symbol) are used , respectively). As mentioned, each field is headed by a data field synchronization segment. As more fully described in the copending application referred to above, the data field synchronization segment is characterized by a relatively long sequence of pseudorandom numbers (511 symbols) followed by three sequences of pseudo-random numbers (63). symbols) relatively short with half the sequences of pseudo-random numbers alternating polarity in successive fields. Both, the relatively long pseudo-random number sequence and the three relatively short pseudo-random number sequences are used as an instruction signal in terrestrial transmission applications and one of the relatively short pseudo-random number sequences is used as a leveling instruction signal in applications more benign, such as in the cable environment. In some applications it is advantageous to be able to identify the first field in a block. The presence of the inverted polarity in the middle of the sequence of pseudo-random numbers (PN) 63 is used in the present invention -For that purpose. A principal feature of the invention is that it provides a novel field identification system that includes a simple, low cost method for identifying the initial field of a block of two fields. The present invention therefore provides a method for identifying the first and second fields in a block of repetitive data segments where each field includes an identical long PN sequence and slightly different short PN sequences in their corresponding segments, which comprises comparing the portion of each segment that would coincide with the long PN sequence with a reference segment to find 'a segment in each field - with the PN sequences, and compare the short PN sequences with the segments found with a co-occurring portion of the reference segment to identify the first and second fields. Additional features and advantages of the invention will become apparent upon reading the following description of a preferred embodiment of the invention in conjunction with the drawings, in which: FIGURE 1 is a simplified block diagram of a television receiver incorporating the invention; FIGURE 2 illustrates a field segment synchronization signal with a long PN sequence and three short ones; FIGURE 3 is a simplified schematic diagram of the invention; and FIGURE 4 is a series of waveforms useful in explaining the operation of the circuit of FIGURE 3. FIGURE 1 illustrates a television receiver 10 constructed in accordance with the invention. A tuner / IF and demodulator 12 receives a multi-level digital signal, either by land or via cable, converts it to an intermediate frequency signal, demodulates it and supplies the demodulated signal to an analog-to-digital converter (A / D) 14 where the signal is converted to a series of corresponding symbol levels. The A / D 14 supplies the signal to a DC 15 removal circuit where the DC in the signal is removed. The signal of the DC removal circuit 15 is supplied to a back comb and to the disconnector 16, to an AGC circuit 17, which supplies the ascending gain and falling gain voltages to the block 12, and to the block synchronization recovery circuit 26 and the segment synchronization recovery circuit 27. The back comb includes a filter to minimize the interference of the NTSC co-channel signals. The output of the back comb and the disconnector 16 is coupled to an equalizer and phase tracker 18, where the signal is equalized, to compensate for tracking errors in a well-known manner, and is tracked in phase in a manner described in FIG. U.S. Patent No. 5,406,587, for example. The equalizer supplies the signal to an MPEG-2 Transport Decoder (Group of Experts of Moving Images) 20 where numerous operations are carried out including the compensation to pre-code the signal, decoding of symbols to convert the data into bytes or in the form of words, convolutional deintercalation of the data, correction of anticipated errors and descrambling of the data, and conversion into video and air data streams. The output of the blog 20 is further processed in a well-known way to play the accompanying video and audio on the received digital television signal. A synchronization blog 24 receives information from the synchronization recovery circuits 26 and 27 and provides synchronization signals, counting down from the symbol frequency, for use in data retrieval. A field segment reference generator 28, controlled by the synchronization block 24, generates a reference for each data segment, at an appropriate time as determined by the synchronization recovery of the segment, corresponding to the signal of Field synchronization known in the first segment of each field. The reference for each data segment, as will be seen, will be used to determine the first data segment (ie, the segment most similar to the reference) in each field and, according to the invention, the data segment number 1 in each block. The synchronization recovery circuit of block 26 functions, as will be described below, to produce an immobilization signal of Fld / Fr (field / block) when both field and block synchronizations have been achieved. FIGURE 2 illustrates the arrangement of a field synchronization data segment and the corresponding symbol levels, which range from -7 to +7. A data segment synchronization of four symbols is followed by a PN 511 sequence which in turn is followed by three PN 63 sequences, with half of the three PN 63 sequences alternating in polarity in successive fields. The alternating polarity of the PN 63 sequence is used to identify the two fields according to the present invention. The VSB mode of 24 symbols, the 92 reserved symbols and the 12 precoded symbols need not be discussed in connection with this invention. It should be noted that the output of the segment field reference generator 28 duplicates the field synchronization segment for each segment illustrated in FIGURE 2, with the appropriate modifications to compensate the effects of the filter 16 (if used) on the symbol levels. Also, it should be understood that the reference only compares one of the polarities of half of the PN 63 sequences. FIGURE 3 describes a simplified schematic diagram of the block synchronization recovery circuit constructed in accordance with the invention. The synchronization block 24 receives an input from a symbol counter, which has been synchronized with the signal received in accordance with the teachings of U.S. Patent No. 5,416,524, an input of a segment counter 42 and a signal input Fr of block. The synchronization block 24 generates a signal which activates the field polarity FldPolEn, a field signal 1 FldlS, a pair of electronic switching signals Egate and EClr, a field signal Fld, a reset signal of block FR, a signal SegrerrEn segment error activation, a segment field reference load signal, SegFldRefLd and a signal from the SMR system reset. A comparator 30 is supplied with a two-bit signal of the fractionator 16 (or a signal bit) and the reference signal of the segment field of the reference generator 28. The output of the comparator 30 is supplied to an input of a gate Y 32, and the other input of which is supplied with the electronic switching signal Egate. The reference generator 28 is synchronized by the signal SegFldRefLd to load the reference at the appropriate time to match each data segment that arrives. The reference is compared with each data segment in the comparator 30, but only a portion of the comparison is used as determined by the Egate. The gate 32 supplies an error counter 34 that is cleared by the EClr signal. The error counter 34 operates by counting the discrepancies (errors) between the individual symbol comparisons of the reference signal and the incoming signal. The output of the error counter 34 is coupled to a pair of circuit arrangements to find the smallest number of errors between the portions of the compared signal. As will be appreciated, a comparative portion is the PN 511 sequence and the other is half of the PN 63 sequence. The compared portion of the PN 511 sequence is processed by a comparator 36 and two registers 38 and 40, in the form of D. (The compared portion of the PN sequence 63 is processed by a similar combination of a comparator 74 and a pair of registers 72 and 76). Those skilled in the art will appreciate that the comparison is not limited to sequence 511 - the invention also contemplates comparing the first or last PN 63 sequence with the intermediate sequence in each field. The register 40 is readjusted by the EClr and activated by the SegErrEn. The Q output of the register 40 is coupled to the active input of the register 38 and the active input of a register 44 which is fed with the outputs of the segment counter 42. The segment counter 42 is fed with the inputs of the symbol clock, a symbol activation signal Sen and a master readjustment signal MR. As the name implies, the segment counter 42 counts the segments (1 to 313) in the received signal based on the field. The register of the segment counter 44 has its output Q coupled to the input D of another register 46, the output Q of which supplies an input to each of a pair of comparators 48 and 50. The other inputs of the comparators 48 and 50 they are supplied from the segment counter 42 and the Q output from the register 44, respectively.

The output of the comparator 50 is coupled to a reliable field counter 52 which is activated by the signal Fld and cleared by a signal from a Y gate 64 which receives inputs from an optional segment mobilization signal and a channel change signal . The reliable field counter 52 has a first output coupled to a Y gate with four inputs 54, a second output coupled to an inverter 60, a third output coupled to the input R of an RS 66 tilter and a Y 68 gate, and a fourth output coupled to the input S of a tumbler RS 66 and a gate Y 45. The signal FldlS is applied to the other gate input Y 45 and as a readjust signal to the register 38. The output of the gate Y 45 activates the register 46 and RS 66 jogger. Another input to the four input gate 54 is supplied from the output of the comparator 48. A third input to the gate is the master reset signal of the SMR system of the synchronization block 24. The fourth input is of the output Q of a flip-flop 58, which in conjunction with a flip-flop 56 constitutes a 'one-time' circuit A presetting of the reliable field counter 52 is supplied to the flip-flop 58 through the inverter 60. The flip-flop 58 is activated from the output Q of the jogger 56, which develops the MR signal. The signal FldPolEn is applied to a symbol 31 delayed jogger and to the active input of the register 76. The output Q of the jogger 70 is coupled to the active input of the register 72. The output Q of the register 76 is coupled to an input of an exclusive NI gate 78, the output from which a reliable block counter 84 is fractioned. The reliable block counter 84 is activated from the output Q of a tilter 82, the input D from which it receives the signal Fld. The output of the reliable block counter 84 is coupled to the gate 68 and the input T of a T 80 tilter, the output Fr of the block signal which is coupled to the gate 78. To explain the operation of the circuit , the reference in the diagrams in FIGURE 4 will be useful. The array determines the first data segment (which contains the field synchronization signal) in each field by successively comparing each data segment with the -generator reference of 28. The composition is on a symbol-by-symbol basis and is performed in comparator 30. The Egate signal in FIGURE 4 synchronizes gate 32 so that only comparisons corresponding to PN 511 sequence and half of PN 63 sequences are used. Every 313 segments, register 38 is loaded with a preset that is greater than the maximum error count that can occur for any segment. This corresponds to each compared symbol that is an error with the reference and in the preferred mode is equal to the hexadecimal 1FF. When errors are counted in each segment, the value in register 38 is changed only when a segment error is found that is smaller than the stored value. Since the value of the preset is greater than the number of possible errors in a segment, the value in register 38 is always changed over the composition of the initial segment. Subsequently, the value in register 38 is changed only when the segment with fewer errors is found in the group of 313 segments. At the end of each group of 313 segments, and in the absence of the noise register 38, there should be the smallest error count, which corresponds to segment number 1 in the field. This is because it contains the field synchronization which is identical to the generated reference. The signal EClr resets the error counter 34 before and after the Egate and the accumulation of errors during the composition of the PN 511 sequence is illustrated by the error curve. The lowest value of accumulated errors in register 38 is matched with the number of corresponding segments provided by segment counter 42 and this segment becomes segment number 1 when the segment counter is cleared by the reset signal MR . The reliable field counter is incremented once the segment with the least number of errors in a successive field is identified as the corresponding segment in the preceding field. The signal FldPolEn is used to make the comparison of the sequence PN 63. The comparison circuit consists of the jogger 70, registers 12 and 16 and comparator 74. Although the comparison is always made, the measurement is considered only when the block counter is released. As shown in FIGURE 4, the FldPolEn pulse shows only the results of the comparison of the half of the PN 63 sequence and ignores the comparison of the PN 511 sequence. Therefore, only the first segments in each field are compared to each other. and the one with the least number of errors can be easily determined since the polarity of half of the PN 63 sequences in the reference field segment is fixed. In this way the segment with the real number 1 in the block can be distinguished from segment number 314 in the block. The determination of the block is used to increase the reliable counter of block 68, which after an identification, results in the generation of the immobilization signal Fld / Fr, indicating that the immobilization of the field and the block has been achieved. It should be appreciated by those skilled in the art that the presence of the back comb will require a change at the start of the Egate to ensure that the effect of the subsequent combing on the first set of symbols in the PN 511 sequences compared is discarded. To summarize, the errors or disagreements per segment are compared with the reference to determine the segment that contains the least number of errors. At the start of each group of 313 segments the register 38 is loaded with a maximum value to ensure that the lowest value is found in each first compared segment. Subsequently any new error value less than the stored value ] Or in register 38 it replaces the stored value. The segment number containing the smallest number of errors in the field is then stored in a register of segment 46. In the next field, if the segment number in which the minimum error value was found matches the i "- , the number of the segment for which the previous field, the reliable field counter counts upwards.If the number of the segment is different, the reliable counter counts in descending order.The number of segments determined is changed only when the reliable counter reaches the zero, which also occurs via a reset whenever a channel change occurs When the reliable field counter reaches a count of two, the reliable block counter is activated Field immobilization is achieved when the reliable field counter reaches a count of four.

? The reliable field counter counts up to a maximum of 16, where the count stops, that is, does not advance. The reliable block counter 84 counts up when the tilter T 80 is in phase with the output of the comparator 36. When the reliable block counter reaches an account of one, the block immobilization and the field immobilization conditions are reached. and combined blocks generate the immobilization signal of the field and block Fld / Fr. When the reliable field counter reaches a count of two, it deactivates the reset circuit of the segment counter. The segment counter 42 is reset when the segment number for the present field matches the number of the segment stored in register 46. At this time, the segment number with fewer errors stored in register 46 becomes number one. The master reset signal MR loads register 46 with 001 and the trip reset circuit prevents a reset from occurring again unless the reliable counter has counted down to zero and again down to two. Finally, the comparator 74 compares the results of the error counter 34 by measuring half of the PN 63 sequence with those obtained in a first field. In field 1 of the block of two fields there is a minimum error value, while in field 2 of the block a maximum error value is obtained because half of the sequence PN 63 is inverted until half of the sequence PN 63 of the reference field segment. Therefore, field 1 is distinguished from field 2. What has been described is a novel arrangement to determine the first field of a block of two fields. It should be recognized that numerous changes to the described embodiment of the invention will occur to those skilled in the art without departing from true spirit and scope. The invention should be limited only by what is defined in the claims.

It should be noted that in relation to this date, the method known to the applicant to carry out the aforementioned invention is that which is clear from the present description of the invention.

Claims (8)

2. Having described the invention as above, the content of the following claims is claimed as property: 1. A method for identifying the first and second fields in a block of repetitive data segments where each field includes an identical long PN sequence and PN sequences slightly different slices in their corresponding segments, characterized in that it comprises comparing the portion of each segment that would coincide with the long PN sequence with a reference segment to find a segment in each field with the PN sequences, and comparing the short PN sequences in the segments found with a matching portion of the reference segment to identify the first and second fields. 2. The method according to claim 1, characterized in that the data segments comprise multiple-level symbols and wherein the comparisons are made on a symbol-by-symbol basis, and because they further comprise determining the segment with the PN sequences by finding the segment compared to the lowest number of symbol errors compared to the reference segment.
3. 3. The method according to claim 1 or 2, characterized in that the short PN sequences in successive fields have opposite polarities and in which the portion coincident with the reference segment has a fixed polarity.
4. 4. A block identification system including means for receiving data in the form of two fields or a repetitive data segment with a corresponding data segment in each field which includes a first data sequence and a second data sequence, the first sequences of data. data are identical and the second data sequences are different, a sequence of reference data having a first portion identical to the first data sequence and a second portion identical to one of the second 10 data streams, first means for comparing the data segments with the first portion of the reference data sequence to identify a first segment in each of the fields, and second means for comparing the second data sequences in the first segments from 15 data identified with the second portion of the reference data sequence to identify the individual fields. The system according to claim 4, characterized in that the data segments comprise multiple level symbols and wherein the first and second comparison means compare the individual symbols in the first and second data sequences with the corresponding symbols in the sequence of reference data. 6. The system in accordance with the ¿. D claim 4 or 5, characterized in that it includes an error counter for counting the symbol errors, and recording means for recording the smallest number of symbol errors in a data segment and for storing a corresponding segment number in each field, and signal means for restricting the operation of the error counter to the first and second portions. The system according to claim 6, characterized in that the first data sequence is relatively long and the second data sequence is relatively short, with the second data sequences alternating in polarity in successive fields and the system includes means for activating the first comparison members when the first relatively long data sequence occurs and to activate the second comparison means when the second relatively short data sequence occurs. The system according to claim 6, characterized in that it includes a reliable field counter, a reliable block counter, and means to increase the reliable counters in response to successive identical determinations of the first segments in each of the fields and in response to identical successive determinations of the identities of each of the fields.