MXPA99003641A - Sintonizac apparatus - Google Patents

Abstract

The present invention relates to a tuner for receiving a video broadcast signal comprising commendable circuits (6, 7, 8, 17) for selecting a tuned frequency, the tuner comprises a common interface connection (21) that receives bytes of data and within these bytes of data, bytes that represent a divisor percentage N and address bytes. The bytes received by the common interface connection (21) are processed through a divider comparator N (23) which compares the value of the divider percentage N received from the common interface connection (21) for values stored in the register (24). ), the comparator (23) extracts bytes of address and bytes of data to send them to the recommended circuit (6, 7, 8, 17) of the tuner to select a band and a tuned frequency. The tuner can be implemented in a chassis of a receiver without modifying the existing programming included with a microprocessor of the chassis. The values stored in the register (24) are values adapted from the tuned

Description

TUNING APPARATUS DESCRIPTION OF THE INVENTION This invention relates to a tuning apparatus for a frequency synthesizer tuner and, more particularly to the tuner used in a television receiver or video recorder - there is a satellite video receiver or a satellite receiver. upper consumer box set. As the stage enters the television receiver, the tuner provides the primary role of selecting the desired signal and extruding all others. The tuner typically provides a 9 Mhz pass band for a 6 Mhz channel. This pass band is usually achieved by means of four tuned circuits: a single-tuned input filter located between the antenna input and the RF amplifier, a double-tuned pass band filter located between the RF amplifier and the mixing stages, and an intermediate frequency (IF) circuit with a single tuning to the mixer output. The first three select the desired c an a 1 frequency by varying its inductance, capacitance, or both. The participation of VHF or UHF of hyper band, band between those non-standard stages and that varies according to each producer of tuners. The output of the mixer is always tuned to the IF frequency of 45, 75 or 38.9 Mhz according to the standard of the radio broadcast signal, the selectivity provided by the RF stage is to reduce or eliminate unwanted signals from the desired channel. for example image, whereby interference problems are eliminated or reduced in a typical tuner, such as a tuner to receive television broadcasting signals which are transmitted on receptive frequencies of broadcasting, the tuning condition of the tuner is determined by the frequency of the oscillating local signals which are mixed with the received broadcast frequencies to produce a predetermined intermediate frequency (IF) signal.The signal IF is then demodulated to obtain the video broadcasting signals and As the local oscillating frequency changes, the tuner is tuned to different frequencies of broadcasting to receive program data which is broadcast from there. Typically, a local oscillator includes a variable o-inducing capacitor which when the value of this varies, the local oscillation frequency correspondingly goes ri. to . By adjusting, for example, an inductance coil, an operator can change the local oscillator frequency as desired and, in this way, can establish any desired tuning condition of the tuner. _ The variable capacitor is generally constructed as a variable capacitance diode, whose capacitance value is determined by means of a control tuning voltage (v +) applied to it. Since the same control voltage will result in the same tuning condition, the tuners are known, in which the digital techniques are based on the storage of digital representations of respective control voltages, whose digital representations can be extracted, as desired, to set a capacitance value quickly which tuned to the tuner at a desired broadcasting frequency Currently, a so-called frequency synthesizer tuner has been widely used, in which the local oscillation signal is generated by means of a phase-locked loop, under the control of a digital frequency selection signal In the phase-locked loop, a variable frequency oscillator produces the local oscillation signal In addition to being supplied by the usual mixer in the tuner, the local oscillation signal is supplied through a program frequency separator It can be compared to a phase comparator where it is compared against a reference oscillation signal. Any phase difference between this results in an error signal which is re ected to the oscillator by means of a tuning voltage, as for adjusting the frequency of the local oscillation signal and thereby adjusting the tuning condition of the tuner. If the splitter percentage of the frequency separator changes, the divided frequency oscillation signal which is supplied to the phase comparator will change. By means of a well-known phase-locked loop operation, this changes the basic frequency of a local oscillation signal, resulting in the cancellation of the error phase signal.

In the present television broadcasting receiver, the control of the tuning frequency is made by means of a microprocessor. The processor sent to the tuner in a common connection of several bytes of data including for example two bytes to set the value of the separator and other bytes to control the connection to establish it in the tuner. Such tuners are generally made with a mixer oscillator and a phase locked loop integrated circuit. In addition, the change in the dividing value of the control microprocessor must send additional data so that the first stages of frequency selection and the outputs of the tuner are established according to the particular characteristics of the tuner included in the television broadcasting receiver. . Such bytes are processed in an integrated circuit tuner through a common connection interface. Each tuner of the particular manufacturers, as explained above, are made with a particular frequency band division so that according to the frequency chosen by the user, the connection in the circuit will be done in a particular way and the output of the tuner It will be available in one terminal or in another of the integrated circuit tuner. Despite the fact that it is now the so-called "World Standard Pining Frequency Synthesizer tuner", in which the size of the box and the connection terminals are standardized, a tuner of the 'integrated circuit is not easily interchangeable with a circuit of another maker. To use the alternative FST (Frequency Synthesizer Tuner). The tuner for the receiver chassis without any change in programming tuning is not possible for most applications today. The programming _in_clui_da_ in a processor that controls the tuner must include data such as tuner band division, reference division, control tuner __ bytes of the integrated circuit. Therefore, it is necessary in case of a change of tuner type, in particular if a tuner from another manufacturer is used to change the programming, and that is a serious disadvantage for the new tuner in the market. The present invention seeks to provide an improved tuning apparatus.

According to one aspect of the present invention, a tuner is provided for receiving a video broadcast signal, the tuner comprises recommendable circuits operable to select a tuned frequency, the tuner comprises a common connection interface operable to receive bytes of data and between these bytes of data, the bytes representing a divider proportion N and bytes in the direction, whereby the bytes received by the common connection interface are processed through an indexable comparator N comparator to compare the value of the divider percentage N received from the connection interface common to values stored in a register, said comparator being operable to access bytes of address and data bytes to send them to the recommended circuit of the tuner to select a tuned frequency. The preferred embodiment takes advantage of the fact that all tuners dedicated to a region have the same frequency ranges and the same intermediate frequency. In order for the splitter to obtain the desired frequency, it is the same for most tuners. What differs from one type of tuner to another is the frequency band division in RF stages. Thus, in accordance with the preferred embodiment, when there is programming data of any of the existing Frequency Integration Frequency Tuners, a common connection transceiver input is received with correct address byte data, the data divisors 1 and 2 will be transferred to the comparator logical table divider N. It should be noted that in general the divider percentage is given in two bytes, allowing a splitter percentage between 32767 and 256. The comparator inserts the divisor data and extracts all the necessary data bytes taking into account the particular technical characteristics of the tuner in which the comparator is included. The comparison will provide all the output data necessary to complete the tuning func- tions of the frequency synthesizer: a) the frequency band switch (usually> 2 band switch) and the data output gate b) the frequency divider N value c) the self-generated control byte data (The external control byte data that comes in the receiver's microprocessor by of a common I2C connection is not required anymore). As such, the output ports and control bytes that come in the microprocessor through a common I2C connection can be ignored. There are several advantages to using this Frequency Synthesizer Tuner: 1) Full compatibility with the World Standard Frequency Synthesizer Tuner is achieved in languor and programming. 2) Great flexibility in tuner design to achieve the best performance optimized in divisions _ of frequency band and circuit selection .integrated without restrictions to maintain the compatibility of the tuning programming 3) Most of the old tuning programs or existing ones can also be used with a tuner equipped with this universal tuning synthesizer ("UTS") 4) Great benefits to the user of the tuner in application, performance and cost One embodiment of the present invention is described below, by means of of examples only, with reference to the appended drawings, in which: Figure 1 is a block diagram of a tuner section according to the prior art Figure 2 is a block diagram of the tuner section shown in Figure 1, showing one embodiment of the additional circuit in accordance with the invention. With reference to Figure 1, a known tuner is described, then, in __r the ation to Figure 2, as this known version, is modified by one embodiment of the invention. Figure 1 is a section of a known tuner including a mixing oscillator and a phase locked loop 30 circuit. Said circuit 30 includes components 12-22 which will be described later.

The tuner includes an antenna 1, connected, to the band trap filter for use by individuals of trap IF 2. The output of the band trap filter for use of particulars 2 is connected to the inputs of three input filters 3, 4 , 5 for a first, second and third band respectively.

Each of the input types 3, 4, 5 are connected to the input of a corresponding amplifier 6, 7, 8 respectively. The output of each amplifier is fed to a pass band filter with corresponding dual tuning 9., 10, 11 respectively. The output of the dual tuning pass band filter 9 is fed to a UHF mixer 12, the passband filter outputs with dual tuning 10 and 11 are fed to a VHF mixer 13. Each of the mixers 12, 13 receive a signal coming from a local oscillator 14, 15- respectively, and the output of these mixers feed an intermediate frequency amplifier 16. The intermediate frequency amplifier 16 feeds downstream circuits well known in the art which are not represented . The control of the oscillation frequency is also done in a known manner by means of a phase locked loop (PLL) circuit. The PLL circuit also comprises in a known manner a first divider 17 which receives the signal from a local variable oscillator 14, 15 and outputs a split frequency signal. The divided frequency signal is fed to a phase comparator and a charge pump 18 which also receives a signal from a reference crystal oscillator 20. The signal from the reference crystal oscillator 20 is fed to the phase comparator 18 through of a second divider 19. Generally the reference crystal oscillator 20 oscillates at a frequency of 4 MHz and the reference divider percentage is equal to 29 or 2S with or without prescalar, so that the reference frequency received in the phase comparator 18 is 7.8125 KHz or 62.5 Khz while the pitch size of the oscillator frequency is 62.5 KHz. The output signal of the phase comparator 18 is fed back to the oscillators 1415 respectively by means of an integrated tuning voltage of Vt in order to maintain the oscillation frequency. In order to establish the different components of the tuner section at the frequency chosen by a user of the receiver, the data bytes are received from a microprocessor, which is not shown, in a common connection interface. The common connection interface 21 sends the data through a data control input and an output port 22 and through a common connection shown in dotted lines to the amplifiers 6, 7, 8 to deactivate or activate the output of one of the amplifiers, to the filters 3, 4, 5 to set the filter of the amplifier in one of a set of frequency ranges, to the oscillators 14, 15 to switch the oscillator 14 or 15 VHF or UHF towards the first frequency divider. frequency 17 to let in the frequency divider. the data to the amplifier filters, the variable frequency oscillator 14 and 15 depend on the organization of the circuit and can vary from one tuner circuit to another.In contrast, the majority of the frequency divisor percentages (Tuner Step Size) ) are the same from one tuner to another for the same frequency of operation.Thus, it is apparent to the inventor that which is more important in the bytes of data received from the microprocessor are the bytes of data that give the percentage divider for the splitter 17. Once this percentage is known, the operating frequency is known and the other control or connection can be established according to the particular characteristic of the tuner which is used.A preferred embodiment will now be described in connection with the Figure 2. In Figure 2, the components that have the same function as in Figure 1 have been given the same reference number. This is done with a mixer oscillator and a phase-loop loop integrated circuit 31 that includes components _12 through 24. As shown in Figure 2, when the data of an existing program of any FST tuning chassis is received at the input of the common connection interface 21 with data of correct address bytes, and between the data two bytes "of data divisors 1 and 2, the data bytes divisors 1 and 2 will be transferred to a comparator divider N 23" to compare it with a protocol of adapted band division and to predefine the reference dividing factors. The adapted protocol is stored in a register or memory 24. The output of the comparator 23 provides the following output data to a data control and the output and input ports 22 within the integrated circuit of the tuner 31: a) Switch frequency of band (usually >; 2 band switch) and output gate data b) Frequency divider N value c) Automated control byte data The output data is obtained by reading a given table for each range of width divisors. band and output gate data and control byte data. The table can be filled through a design of data exchanged between the tuner design and the manufacturer IC in the frequency band division and the reference divider or "can be filled through flexible designs by means of the programming of common connection in a tuner production location under a "production establishment mode." For the address bytes, since four common I2C connection addresses can be chosen through terminals of the physical equipment, there is no record of their compatibility The function recognition remains the same, as explained above, a step size of 62.5 Khz is usually the standard pitch size in the current tuners, however, in the case of a different reference crystal splitter which means a reference tuner, an optional "selectable reference factor divider" within the divider comparator N 23 can be activate to be able to modify the. value of the divider, of frequency 19, or to only allow the control bite, the function bit 1 and bit 2 (selection of reference divider) to receive the I2C data of an external I2C 'controller for au to se 1 e c oning the tuning step size. In the case of a tuner production alignment mode "UTS" it is possible to disable the "OS" bit to a high impedance mode for the. Manual tuning voltage adjustment for tuner alignment. An example of the table will be explained later. In this example, the data is given in a hexadecimal format. He . The tuner's existing programming protocol "Thomson CTT5000 global standard, tuned the CCIR 09 channel (RF frequency 203.25Mhz, oscillation frequency = RF + IF (38.9) = 242. 15 MHz) is as follows: Data to tune channel 9 - Address setting: C2 (hard terminal of tuner address - open circuit) - divider value N: F22 (for an oscillation frequency of 242.25MHz with step of 62.5KHz) - Control byte: 8E (operating mode, with low current tuning) - Output gate: 06 ~ for band selection # 2, channel 09 is designated in this band).

Table 1. Information format for channel 09 tuning X in table 1 above means that those bits marked with X are not taken into account to determine the exit doors. Yes the tuner. CTT: 5000 was replaced by a new tuner according to the preferred mode and adjusted with a N-divider comparator, the new tuner. only answer it to the N frequency divider and address value and the rest of the data is decoded by the UTS (please refer to the following table).

Table 2. Input information to the UTS tuner X- they are not important. If this same tuner was replaced with another tuner in a television, the adapted band division protocol included in register 24 based on the tuner Thomson WS CTT5000 with step size tuning to 62. 5 kh z serious: Table 3 For the data of the standard I2C connection data format of the Major Tuner / PLL IC manufacture, the data formats of control bytes are given in Tables 4 and 5 plus 1 ante.

Table 4. I2C standard common link data format Note: the address byte and frequency divider bite # 1 and 2 are universal for the RF PLL IC tuner except for _ the control byte. Table 5. Mavor / PLL IC tuning manufacturing control byte information format X- they are not important. Standard Bits Function: 1. The LSB bit is used to deactivate the tuner and put it in a high impedance mode for manual test / s. 2. Bit 6 is normally used for high or low pump loading for different tuning speeds. 3. Bits 3, 4 and 5 are used for production test mode / IC 4. Bits 2 and 1 are used to select different tuning step sizes by changing the glass reference divider or Prescaler to ON / OFF . Note: From the control bit of the table shown above, most bits are used only for the test mode or to improve the tuning speed and will not affect the tuner pitch size. (We can write in a special protocol within the UTS when the N value in "big change", bit 6 is activated to improve the tuning velocity). ~ "Except for the # 1 bits there are 2 that are used for the ON / OFF prescaler to select a crystal reference divider, which will affect the tuning step size, but we can solve this tuning error by means of a divisible reference factor that can be selected within the UTS.

Table 6 Control Bvte 4. function of bit # 2 v bit # 1 All step sizes refer to the 4.0 Mhz crystal oscillator. We can summarize the invention with a modality as described below. A Normal Frequency Tuner (FST) Tuner selects desired frequency channels by means of a phase locked loop function within the tuner. The tuner requires (a) frequency data by the user (Table 1, divisor N byte 2 and 3), (b) data of frequency band division in terms of an output door switch control IC for the requirement of particular tuner design (Table 1, control byte 5), (c) operational control data for the particular tuner design requirement (Table 1, control byte _ 4). This required internal and external desired data received by the I2C transceiver (inside the MOPLL IC or PLL IC tuner) by means of the. I2C protocol bytes received from the external microprocessor controller in the receiver instrument using this tuner (Table 4 and Table 5). A Universal Tuner (UTS) integer tuner according to the invention does not require the frequency band interrupt data and the operational control data (the aforementioned inputs (b) and (c)). The only input required is the user's input data (the aforementioned input (a)) which is independent of any internal tuner design requirements. All the required control data is completely and internally derived within the tuner itself from the data of the aforementioned frequency divider N (a). The two control bytes 4 and 5 can be safely ignored or omitted. The UTS tuner has a logic N divisor (23) and a stored register (24) with a predetermined frequency band division in terms of the adapted design N value (Table 3). The frequency data received in the form of divisor value N (byte 2 and 3 as mentioned above) should be compared with the value "N predetermined", such a comparator is operable to output the intended gate and the control function of according to the physical design of the particular tuner automatically and make the correct change of frequency band, (example band 1, band 2 and band 3_ in Table 3) and control the rest of the tuning circuits to achieve a tuner of s int Fully functional frequency etiz ac ion The UTS tuner only needs the desired frequency input by the user for the N-value of an external microprocessor of the receiving instrument It requires only 3 bytes (Table 2) to be fully functional as a tuner FST compared to the normal FST tuner "which requires 5 bytes (both included the standard I2C address byte). The two N-dividers are universal for all tuners (the tuner with the same tuning pitch size of 62.5khz) without taking into account their particular physical equipment design, while the "control bytes omitted or ignored 4 and 5 are non-standard data depending on a design of individual tuner hardware The new I2C developed programming for such UTS tuner can be shortened to a protocol of 5 bytes to 3 bytes to improve its simplicity and achieve standardization and compatibility. This will remove the programming constraints of using a new FST tuner to replace the current one.The UTS tuner may have flexibility to be extended to work in different tuner pitch sizes by accepting bit 2 (RSA) and bit 1 (RSB) of control byte 4 for the selection bits reference dividers (Table 5) while in all other bytes in the control bit 4 are still ignored and the control byte 5 is either ignored or omitted. As such, in addition to the "lack of capacity of 62.5 Khz tuner pitch size, the step size of 31.25khz, 50khz or others can be selected (if required by the user) by means of the standard practice of the RSA and RSB bits setting the MOPLL or PLL "IC (Table 6). A built-in oscillator phase-locked loop mixer circuit (MOPLL IC) or an integrated phase-locked loop (PLL IC) circuit in the tuner is included and integrated into the UTS tuner. The UTS tuner according to the invention will solve a programming compatibility problem by applying the FST tuner within a receiver instrument. Creates a total programming solution for the current world standard FST tuner and frees the design of restrictions in the physical design of the tuner to allow total flexibility in the division of frequency bands and design of the physical equipment for give the mejotes r end im? In this case, an existing receiver instrument with an existing I2C protocol programming can be applied to a UTS tuner without any modification of the parameters and costs in accordance with its design capability, "which is intended for purposes of this invention. programming to replace the existing "FST tuner and can benefit at a competitive cost, better performance, a shorter process evaluation, and take the risk of making the modification of schedule and time. - "

Claims (6)

1. A tuner for receiving a video broadcast signal, comprising recommendable circuits operable to select a tuned frequency, a common connection inferrable operable to receive bytes of data and between those bytes of data, bytes representing a percentage divisor N corresponding to an input frequency by the user of the tuner, characterized in that the tuner further comprises an indexable comparator N comparing the value of the divisor percentage N received from the common connection interface to values stored in a register, such The comparator is operable to take bytes of address and bytes of data to be sent to the recommended circuitry of the tuner to select a tuned frequency.

2. The tuner of claim 1, characterized in that the register contains predetermined frequency band divisions in terms of an adapted design value N, such as to allow the divider comparator N to take bytes of address and bytes of data depending on the result of the comparison to exchange the operating frequency band and control the recommended circuits to achieve a fully automatic and functional frequency synthesizer tuning.

3. The tuner of claim 1 or 2, characterized in that to achieve the tuning operation, it only needs the user to desire the frequency corresponding to the divisor percentage N from a microprocessor.

4. The tuner of any of claims 1 to 3, characterized in that the divider comparator N is connected in common connection to a frequency divider of a frequency output by a re fl ecting crystal oscillator.

5. The tuner of claim 4, characterized in that the divisor comparator N outputs a reference divisor factor s e 1 ecc i onab 1 e optional to modify the frequency value.

6. The tuner of any of claims 1 to 5, characterized in that the divider comparator N is included in an oscillator mixer and an integrated phase loop loop.